JPH02124660A - Modulator-demodulator - Google Patents

Abstract

PURPOSE:To send a double data in one carrier frequency and to attain high speed data transmission by applying MSK modulation to a data of the 1st bit of a transmission data divided for each 2-bit and applying amplitude modulation to the signal in response to the data of the 2nd bit of the transmission data. CONSTITUTION:When a transmission data of NRZ(Non-Return-to-Zero) form whose speed is, e.g., 2400bps is divided by a division circuit 13 for each 2-bit, an MSK(Minimum Shift Keying) modulation circuit uses a carrier frequency 1800Hz to apply MSK modulation when the 1st bit is data '0', and used a carrier frequency 1200Hz to apply MSK modulation when the 1st bit is data '1'. Then the amplitude modulation circuit 15 applies amplitude modulation having a signal from the MSK modulator 14 when the 2nd bit is data '0' and applies amplitude modulation to a signal from the MSK modulator 14 at a multiple of the unity when the 2nd bit is data '1'. An MSK demodulation circuit 19 in a demodulation section demodulates the signal into a reception data thereby demodulating the signal into the received data in 2 bits. Thus, high speed data transmission is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a modulation/demodulation device that is built into various devices equipped with a computer and is capable of transmitting wireless data at high speed to and from wireless devices.

2. Description of the Related Art Conventionally, this type of modulation/demodulation equipment has been used for NRZ (NonR
eturn-to-Zero) signal data [01
is modulated with a carrier frequency of 1,800Hz, and the data “1
MSK (
It is generally composed of a modulation section that modulates a signal of the Minimum 5hift Keying) modulation method, and a demodulation section that demodulates this modulation signal of the MSK method into a data string of an NRZ signal.

Problem 3 to be Solved by the Invention However, in the conventional modulation/demodulation device described above, when the upper limit frequency of the frequency band of data signals that can be transmitted via a wireless line is 3,000 Hz, the data can be transmitted at twice the high speed. In order to realize transmission, the carrier frequencies of data rOJJIJ must be 3,600 Hz and 2,400 Hz, respectively, which exceeds the upper limit frequency of the wireless line, making it impossible to transmit data at twice the speed. There is.

SUMMARY OF THE INVENTION In view of the above-mentioned conventional problems, it is an object of the present invention to provide a modulation/demodulation device that can realize high-speed data transmission.

Means for Solving the Problems In order to achieve the above object, the present invention performs MSK modulation on the first bit data of transmission data divided into every 2 bits, and modulates this MSK modulated signal into the transmission data. The amplitude is modulated according to the second bit data.

Effect: With the above configuration, the present invention can transmit twice as much data using the same carrier frequency, and therefore can realize high-speed data transmission.

EXAMPLES Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the modulation section of the modem device according to the present invention, FIG. 2 is a block diagram showing an embodiment of the demodulation section of the modem device according to the present invention, and FIG. FIG. 2 is an explanatory diagram showing a modulation signal of the modulation/demodulation device of FIGS. 1 and 2. FIG.

In FIG. 1, 11 has a speed of 2,400 bp, for example.
s's NRZ (Non-Return-to-Zero
) format transmission data input circuit, 1
2 is a transmission clock generation circuit that outputs a data latch timing signal for the transmission data input circuit 11, and 13 is a division circuit that divides the transmission data from the transmission data input circuit 11 into every 2 bits.

14 converts the first bit of the transmission data from the dividing circuit 13 to a carrier frequency of 1,800 Hz, 1
, MSK modulation circuit for MSK modulation at 200 Hz, 15
converts the modulated signal from the MSK modulation circuit 14 to the division circuit 1
16 is an output for outputting the transmission modulation signal from the amplitude modulation circuit 15; In FIG. 2, 17 is a reception modulation input circuit for receiving and taking in the modulation signal from the modulation section, and 18 is a reception modulation input circuit for receiving and taking in the modulation signal from the reception modulation input circuit 17. A reception filter 19 that removes high frequency components demodulates the modulated signal from the reception filter 18 into first bit data of the reception data by MSK demodulation.
This is an SK demodulation circuit.

20 is a full-wave rectifier circuit that performs full-wave rectification of the modulated signal from the reception filter 18; 21 is a full-wave rectifier circuit that integrates the modulated signal that has been full-wave rectified by the full-wave rectifier circuit 20 at a period of, for example, 1,200 bps, and performs reception modulation. 22 is an integrating circuit for extracting the amplitude modulation of the signal; 22 is a comparison circuit that demodulates the received data into second bit data by comparing the case integrated by the integrating circuit 21 with a reference signal; 23, MSK demodulation circuit 19, comparison 6...-/ A synthesis circuit 24 synthesizes the first and second bits demodulated by the circuit 22, respectively, and converts the received data synthesized by the synthesis circuit 23 from the reception clock generation circuit 25. This is a received data output circuit that outputs data based on the received clock.

Next, the operation of the above embodiment will be explained with reference to FIG.

First, in Fig. 1, for example, the speed is 2,400 bps.
When the NRZ format transmission data is divided into every 2 bits by the division circuit 13, the MSK modulation circuit uses a carrier frequency of 1,800 if the first bit is data "0".
MSK modulation is performed at Hz, and when the data is "1", MSK modulation is performed at a carrier frequency of 1,200H2.Next, the amplitude modulation circuit 15 performs MSK modulation at a carrier frequency of 1,200H2 when the data is "1". , MSK modulation 1
The signal from 4 is amplitude modulated by 0.5 times, and the second bit is "
1'', the signal from the MSK modulation 14 is amplitude modulated by a factor of 1.

Therefore, as shown in FIG. 3, if the 2-pit transmission data with a speed of 2,4007 bps is "00",
MSK modulated with a carrier frequency of 1,800Hz and 0.5
If the value is "01", the amplitude is modulated by a factor of 1 by MSK modulation at a carrier frequency of 1+800Hz, and similarly, if the value is "10", the carrier frequency is 1,200H.
MSK modulated with z, amplitude modulated with te 0.5 times, "11"
In this case, MSN modulation is performed at a carrier frequency of 1,200 Hz and amplitude modulation is performed by a factor of 1, so that transmission data of 2,400 bps can be transmitted within a range that does not exceed the upper limit frequency of the wireless channel of 3,000 Hz.

In the demodulation section shown in Oka, FIG.
, an integrating circuit 21, and a comparator circuit 22. By demodulating the received data into second bits of received data, it is possible to demodulate into two bits of received data.

As described in detail, the present invention performs MSK modulation on the first bit of transmission data divided into every two pits, and converts this MSK modulated signal into the second bit of the transmission data. Since the amplitude is modulated accordingly, twice as much data can be transmitted using the same carrier frequency, and therefore high-speed data transmission can be achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the modulation section of the modem device according to the present invention, FIG. 2 is a block diagram showing an embodiment of the demodulation section of the modem device according to the present invention, and FIG. , 1st
FIG. 4 is an explanatory diagram showing the modulation signal of the modulation/demodulation device of FIG. 2 and FIG. 2, and FIG. 4 is an explanatory diagram of the modulation signal of the conventional modulation/demodulation device. 13... Transmission data division circuit, 14... MSK modulation circuit, 15... Amplitude modulation circuit, 18... Reception filter, 19... MSK demodulation circuit, 20... Full wave rectification circuit, 21. ...Integrator circuit, 22...Comparison circuit, 24.
...Synthesis circuit.

Claims (3)

[Claims] (1) means for MSK modulating the first bit data of the transmission data divided into every 2 bits; means for amplitude modulating the MSK modulated signal according to the second bit data of the transmission data; means for demodulating the amplitude-modulated MSK modulated signal into first bit data of received data; and detecting the amplitude modulated MSK modulated signal and demodulating it into second bit data of the received data. A modem device having means. (2) The transmission data is 2,400 bps, and the MSK modulation means converts the first bit of the transmission data into carrier frequencies of 1,200 Hz and 1,800 Hz.
2. The modulation/demodulation device according to claim 1, wherein the modulation/demodulation device performs MSK modulation. (3) The amplitude modulation means amplitude modulates the MSK modulated signal at a ratio of 1:2 in accordance with the second bit of the transmission data. modem.