JPH02124656A - Synchronization recovery method in data bus system - Google Patents

Abstract

PURPOSE:To find out a pause period between packets on a data bus and to recover the synchronization early by allowing a data bus system to apply reception independently of the presence of synchronization. CONSTITUTION:It is taken as the completion of recovery of synchronization that a data bus system makes reception independently of the presence of synchronization and a normal packet is able to be received without absence of production of one packet error. That is, a serial data such as an error packet and a normal packet on a data bus HB is received at first and when the received data is not one packet error but a normal packet, it is taken that the synchronization of the data bus system is recovered. Thus, even when an individual packet is sent consecutively onto the data bus HB, the procedure of searching a pause period (22[bit]+10[ms]) is omitted. Thus, the synchronization of the said data bus system is recovered early.

Description

[Detailed Description of the Invention] [Summary] A synchronization recovery method in a data bus system, in particular, a method for recovering synchronization in a data bus system when communication synchronization is lost due to failure to return to the bus transmission standard during information transmission between each information communication device. In addition to the method of finding the pause period between packets on the data bus, the procedure for recovering synchronization is to find the pause period between packets on the data bus. In a data bus system that transmits serial data including periods, synchronization has been recovered when the data bus system performs a reception operation regardless of the presence or absence of synchronization, no single packet error occurs, and normal packets are received. Configure including setting the state.

[Industrial application field]

The present invention relates to a synchronization recovery method in a data bus system, and more specifically, the present invention relates to a synchronization recovery method in a data bus system. If so, it concerns the procedure for restoring its synchronization.

In recent years, various information and communication equipment (home appliances, AV (Audi)
(Visual) devices, security-related devices, etc.) are connected to a common transmission path, deepening organic ties between devices, and integrating various functions of society that is evolving beyond just the home. However, home bus systems are being introduced that position the home as part of the network and allow anyone to freely select all kinds of information inside and outside the home from anywhere at any time.

However, when transmitting information between each information communication device, the communication operation of the device may become out of synchronization with the communication operation of other devices due to noise, etc. There are some things that I can't do.

Therefore, there is a need for a method for recovering the synchronization of the device.

[Conventional technology]

FIGS. 32 and 33 are explanatory diagrams related to the conventional example.

FIGS. 32(a) and 32(b) are diagrams for explaining a synchronization recovery method according to a conventional example, and FIG. 32(a) shows a schematic diagram of the configuration of a standard home bus system.

In the figure, 1 is a home bus controller (HBC);
2 is information equipment (A-D) such as home appliances, AV (Audio Visual) equipment, and security-related equipment;
3 is a home bus (information transmission line), and HBD indicates home bus data.

These constitute a standard home bus system.

FIG. 2B is a diagram illustrating the transmission standard between packets in the home bus system.

In the figure, 4 is the packet (serial data group) having information data and control code data, and 5 is the packet immediately before the packet. In addition, in the case of broadcast communication, since the other party is not specified, there are no dummy codes and data control codes for ACK/NAK.
In the case of individual packets, a dummy code and ACK/NAK are attached in order to obtain a response of acknowledgment (A(J) or disapproval (NAK) data from the other party).

In addition, A is the rest period (22 (bit) + 10 (m
s) ), which indicates a pause period during serial data transmission between broadcast packets during broadcast communication.

Ta is the pause time (10 (ms)), which indicates the pause time during serial data transmission between individual packets during individual communication. Note that TF is synchronization recovery monitoring time (2
08 (μs), which is the time required for monitoring the home bus by the status register of the bus control circuit of the home bus controller 1 and each information device 2.

FIGS. 33(a) and 33(b) are diagrams illustrating problems of a conventional synchronization recovery method, and FIG. 33(a) is a diagram illustrating synchronization recovery.

In the figure, synchronization recovery is a standardized fixed period A (22(b
it) +10 (ms)) indicates that the communication operation of the information device is to be matched to
Send data on the home bus during F<A<B,
A communication operation such as receiving indicates that the information device is out of synchronization. In addition, when communication operation can be started B
The information device that performed the communication operation is now synchronized with the standardized home data bus.

In addition, with the conventional synchronization recovery method, synchronization cannot be achieved (out of synchronization) due to equipment startup or noise, etc.
In this case, it was determined whether synchronization was achieved or not by searching for a period in which no data existed in A for a certain period of time, for example, a pause period (22 (bit) + 10 (ms)).

FIG. 6(b) shows a state in which individual packets are continuously transmitted on the data bus and a pause period thereof.

[Problem to be solved by the invention]

Therefore, in FIG. 33(b), when an individual packet with ACK/NAK added is transmitted as serial data to a specific communication device, that is, the pause time = 10
If normal packets are continuously transmitted on the home bus at intervals of
0 (ms)).

Therefore, the information device that cannot find this period cannot recover synchronization until the transmission of this individual packet is completed.

As a result, if synchronization is out of order due to a "short noise" caused by starting up a device, etc., and trying to find a pause period from the end of the noise, only the device in question will be out of synchronization and will be synchronized early. The problem is that it cannot be recovered.

The present invention was created in view of the problems of the conventional example, and in addition to a method of finding a pause period between packets on a data bus, it also provides a method for quickly recovering synchronization even in a state where synchronization cannot be achieved. The purpose of this invention is to provide a method for recovering synchronization of a data bus system.

Still another object of the present invention is to provide a system that can easily cope with out-of-synchronization in such a synchronization recovery method, and at the same time is less susceptible to malfunctions caused by noise or the like.

[Means to solve the problem]

The principle flowchart of the synchronization recovery method for a data bus system of the present invention is shown in FIG. 1, and an example thereof is shown in FIG.
As shown in Figure 1, in a data bus system that transmits serial data including a standardized idle period via a data bus, the data bus system performs a receiving operation at Pl regardless of whether synchronization is performed, and one packet is transmitted at P2. If it is YES, return to P and perform the reception operation again.If NO and if a normal packet can be received at P3, the data bus system has regained synchronization at P4. It is characterized by making it a state, and achieves the above-mentioned meaning.

[For production]

According to the present invention, for synchronization recovery of the data bus system, serial data on the data bus is first received, and when the received data is not a single packet error but a normal packet, the data bus system It is assumed that synchronization has been recovered.

Therefore, the conventional procedure of searching for a pause period (22 (bit) + 10 (n's)) can be omitted even when individual packets are continuously transmitted on the data bus, for example. .

This makes it possible to recover the synchronization of the data bus system at an early stage.

Since the method described above may pick up noise, another synchronization recovery method according to the present invention applies the synchronization recovery method described above, and also uses the 34th synchronization method when synchronization is achieved for each packet. As shown in Figure 34 (a), reception data is not accepted during the pause period or the pause time, and when an error occurs and the synchronization is not achieved, the pause period or the This is to allow received data to be accepted during all parts of the pause period in order to quickly recover synchronization, and after that, once synchronization is achieved, no data will be accepted again.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

2 to 31 are diagrams explaining a synchronization recovery method in a data bus system according to an embodiment of the present invention, and FIG. 2 shows a configuration diagram of a data bus system according to an embodiment of the present invention. .

In the figure, 11 is a microprocessor, 12 is a bus control circuit, 13 is a home bus driver receiver, 14 is a fundamental frequency generator, and HB is a home bus.

Note that the microprocessor 11 and the bus control circuit 12 have a data bus (DATA (DO to D7)) line, an address bus (A o = At) line, and a chip select (τ
) line, write signal (WR) line, read signal (RD) line, reset signal (RE!5ET) line, interrupt signal (IRQ) line,
) are connected by wires. The terminals of the bus control circuit 12 connected to these signal lines are for the following purposes.

Terminals connected to address buses A0 to A2 are terminals for selecting internal registers (the bus control circuit 12 in the embodiment of the present invention has eight registers, as will be described later), and address signals A0 ~A2 register T
XDR, RXDR, AKR, CCR.

5TRI, 5TR2, MDR, and MLC noise deviations are selected.

The chip select signal terminal is a terminal selected by the microprocessor 11 to be added to the bus control circuit 12, and is set to “L”.
o'', and it becomes possible to write to and read from each register of the bus control circuit 12.

When writing data to each register, the write signal terminal is
The terminal to which the L I+ signal is applied and the read signal terminal are terminals to which "L"' is applied when reading data from each register. When L II is applied to the write signal terminal, the data applied from the data bus is stored in the register specified by the address value applied from the address signal terminal, that is, the register instruction value, and when "L" is applied to the read signal terminal, the address The contents of the register specified by the register instruction value applied from the signal terminal are output to the data bus.

The reset terminal is a terminal for resetting the bus control circuit 12, and when "L" is applied, the bus control circuit 12 initializes the values of each register.

The interrupt signal terminal is a terminal that the bus control circuit 12 outputs, and "Lo" is output from the terminal when, for example, 1 byte of data is received.

Although not shown in the microprocessor 11, there is a ROM and RA.
It executes a program stored in the ROM and transmits and receives control data and the like to a control channel (CH) of the home bus, which will be described later, via the bus control circuit 12. Note that the microprocessor 11 has an address bus A. - In addition to A2, the upper bits of the address bus are, for example, A Is ”= A 3, and ROM and R
AM etc. are connected to these address buses AIs-A 6 and operate as a processor circuit.

On the other hand, the bus control circuit 12 has terminals (HB data (RXD) input terminal, HB data (+) direction output terminal, HB data (-) direction terminal) connected to the home bus driver/receiver 13 in addition to the above-mentioned terminals. ), and further has a clock input terminal to which a clock signal CLK from the fundamental frequency generator 14 is applied.

Note that the fundamental frequency generator 14 has a frequency of 4.9 MHz or 614 MHz.
．． The bus control circuit 12 outputs a 4KHz clock signal, and when a signal with one of these two frequencies is added, it outputs a clock select signal (
It also has a clock select terminal to which C3EL) is added.

FIG. 3 is a circuit configuration diagram of the bus control circuit 12 of the data bus system according to the embodiment of the present invention. The aforementioned data (DATA), address signals A0 to A2, and write signal W
D, Read signal TT, Chip select signal D, Reset signal valve A, Clock signal CLK, Interrupt signal T D, Possible.
The clock select signal C3EL is sent to the buffer circuit 15 (C
PU-110), and the buffer circuit 15 applies these signals to each target circuit.

Clock signal CLK is applied to clock generation circuit 16 and edge detection circuit 17 as a master clock.

The clock generation circuit 16 generates a clock for each circuit, which will be described later, and applies it to each circuit.

The edge detection circuit 17 includes received data, that is, HB data such as broadcast packets and individual packets on the data bus, and when the edge detection circuit 17 detects an edge of data from the master clock, it pauses as described below. A counter 18 and a status counter (MDR) 19 output a message indicating that a data edge has been detected, that is, data reception has started.

In addition to the edge detection circuit 17, the HB data (RXD) is applied to a sampling circuit 20, the contention negative is applied to a detection circuit 21, and a non-short message interrupt detection circuit 22. For example, HB data is 9
This is 600 bps serial data, and the sampling circuit 20 sequentially reads the serial data bit by bit and adds it to the RX shift register 23.

The home bus HB is two twisted wires, for example, and the home bus driver/receiver 1 sends signals to the home bus HB or receives signals from other devices.
It is 3. The signal output to the home bus HB consists of 11 bits per piece of data.

Note that FIG. 4 shows a data configuration diagram according to an embodiment of the present invention. In the figure, 1 data consists of 1-bit start bit ST, 8-bit transfer information (transfer data BO to B7
), 1 parity bit (PA), and even 1
It consists of a stop bit (sp) of bits. On the home bus HB, a positive or negative pulse exists when it represents "L"("0"), and no pulse exists when it represents "H"("1").

Note that the start bit is always "L"("0"),
The stop bit is always “H” (“1 bit”), and data BO to B7 in FIG.
Such data is always converted into a 0.1 signal and applied to the bus control circuit 12 as received data RXD.

The sampling circuit 20 is a circuit that sequentially samples 0 and 1 signals. The RX shift register 23 receives each bit BO to B7 of 1 transfer information added in 1-bit units from the sampling circuit 20 and shifts it. At this time, RX
Every time the shift register 23 shifts data, it also outputs the data to the parity check circuit 24. The parity check circuit 24 counts the number of bits of 0 or 1 in 1 transfer information, and then outputs the data after 1 transfer information. Compare with the parity added.

This parity is the conventional even parity or odd parity, and each time one transfer information is received, it is determined whether the data is normal or not. Status register (
STR2) Store in 29.

The RX shift register 23 is a serial-in, parallel-out shift register, and every time transfer information is received, the 8-bit information is transferred to the reception data register (RXD).
R) Store in 30. As will be described later, when one piece of transfer information is stored in the receive data register (RXDR) 30, a signal is sent to the status register (STI) to turn on a flag that allows the microprocessor 11 to read this data.
I 1) Add to 31. This storage allows the processor, for example, to register this status register (STR1) 3
When reading 1 and the reception flag is on, it can be recognized that 1 byte of information has been transferred to the reception data register.

Each of the circuits described above can receive data such as broadcast packets and individual buckets from the home bus HB.

A register (TXDR/8KR) 28 is a transmission buffer when transmitting information, etc. to another device via the home bus HB. When the microprocessor 11 selects this register (TXDl?/AKR) 2B and stores transfer information, etc., the TX shift register 25 reads it, adds a start bit, and sequentially stores 1-bit serial data S.
The output is output to the AMI circuit 26 as O, and the competition negative output is output to the detection circuit 21.

Note that 8-bit data to be transferred is added to the parity generation circuit 27 via the TX shift register 25.
Parity is generated corresponding to the data to be transferred, and the parity is added to the TX shift register 25. This parity is inserted into the parity bit position following one transfer information BO to B7 as shown in the data configuration diagram shown in FIG.
TX shift register 25 outputs parity bit PA. After the parity bit PA, the TX shift register 25 inserts a stop bit SP and finishes transmitting one data.

A control signal is added to the transmission control section 33 from the control code register (CCR) 32.
3 is the register mentioned above (TXDR/AK) by this signal.
R) Data is read from 2B to the TX shift register 25, and a signal is applied to the TX shift register 25 to sequentially control transmission in units of 1 bit. With this control, the aforementioned serial data SO is transferred to the TX shift register 2.
Output from 5.

In addition, on the home bus HB, in order to eliminate the DC component of the current during serial data transfer, pulses in the positive and negative directions as shown in Figure 4 are repeatedly generated when the data is "0". . The AMI circuit 26 controls this repetition and generates a control signal to output pulses in the positive and negative directions.

Serial data SO is added to this AMI circuit 26, such as "oooooo" as shown in FIG.

When the serial data is "0001", the transmission data signals TYT and TXL sequentially generate positive and negative pulses to represent "0".

Note that this relationship is expressed as TY■ according to the embodiment of the present invention shown in FIG.
, 'T'Tr: Shown in the data explanatory diagram.

FIG. 6 shows a home bus driver according to an embodiment of the present invention.
3 is a transmitting circuit diagram of the receiver 13. FIG.

In the figure, transmission data 'TTT and TXT are applied to the bases of transistors Trl+Trz via inverters 11 and 12 and resistors R1 and R2, respectively.

The emitters of the transistors Tr++ and Trz are grounded,
The collector is connected to both ends of the primary side of the transformer L, whose intermediate point on the primary side is connected to the power supply v8. Both ends of the secondary side of the transformer L are connected to the home bus HB via capacitors CI and C2. Since the transmission data TXH is applied to the inverter 11, in the case of the configuration shown in FIG. 6, the bits STO, Bl, B3 . B5. At B7, the transistor Tr1 is turned on. Also, since the transmission data Tr is applied to the inverter 12, bits BO, B2 . B4. B6. Transistor T in PA
r is turned on.

When the transistor Trl is turned on, a current flows from the power supply VB through the intermediate point on the primary side to the side to which the transistor Tr is connected, and as a result, a pulse in the positive direction is output to the home bus HB. Ru. On the other hand, when the transistor Trz is turned on, the opposite is true,
A negative direction pulse is output to the home bus HB. In addition,
Capacitors CI and C2 are elements for setting with a DC set or a low frequency band. Since there are cases where power is supplied via the home bus HB, the DC component is cut by this capacitor.

When transmitting each piece of information on the home bus HB, an acknowledgment signal ACK or a not-acknowledged signal NAK is sent to determine whether the device to which the data was transmitted has received the data. This acknowledge signal ACK or NACK signal NAK
- In boat fishing, it is treated as data to be transmitted, that is, a piece of information. Therefore, conventionally there is one register for storing data to be transmitted, but in the present invention, there are two registers.
It is divided into one for this data and one for access.

FIG. 7 shows the cash register of FIG. 3, l (
TXDR/AKR) 2B is a configuration diagram.

In the figure, 8-bit data input from the buffer circuit 15 is sent to the data register 28-1 and ACK/NAK.
It is divided into registers 2-2 and stored. As will be described later, this data system (TXDR) 28-1 and AC
The data is separately stored in the K/NAK register 28-2 via the buffer circuit 15.

The transmission control unit 33 applies a selection signal for selecting these registers to the register (TXDR/AKR) 2B, and this selection signal is input to the selector 28-3 in FIG. Selector 28-3 is data register 28-1
The selected data is added to the TX shift register 25 using this selection signal.

As a result, data, which is information to be transmitted, is stored in two registers, and when necessary, that register is selected and transmitted. The selection of this register is made depending on the purpose of sending out information or an ACK signal, etc. Depending on the purpose, writing from the microprocessor 11 to the register may not only be a conversion of the write, but also data or an ACK signal. It is possible to create a program without detecting the steps.

The bus control circuit according to the embodiment of the present invention shown in FIG. 3 has eight registers, and these registers are read or written via the buffer circuit 15. Data is written to the registers CCR and TXDR/AKR, and is written to the respective target registers according to instructions from the buffer circuit 15, that is, write instructions from the microprocessor 11. Read from registers RXDR, CCR, 5
TRI, 5TR2, MDR, and MLC, and the data select circuit 34 selects the respective outputs according to the values of the address signals A0 to A2 and outputs them to the data (DATA) bus of the microprocessor 11 via the buffer circuit 15.

Transmission data register TXDR is a write-only 8-bit register. The data to be sent onto the data bus HB, except for ACK/NAK, is written into this register by the microprocessor 11.

Also, by writing data to this register, a series of data transmission operations is started.

The reception data register RXDR is an 8-bit register dedicated to reading home bus data. Register AKR (CK/NAK transmission register) is a write-only 8-bit register for ACK/NAK transmission. When a value is written to this register, data is sent during the next ACK/NAK transmission possible period.

However, if transmission is unnecessary due to a circular, short message interruption, or packet error (data reception error, write lost data error), it will not be sent. Also, it is not transmitted over the next packet. control code register C
CR is a readable and writable flag register for control. Mode 1 is selected by setting the upper 4 bits to 0H (hexadecimal), and mode 2 is selected by setting the upper 4 bits to 6H. Also, when canceling the reset, use the RES
CCR flags other than flags are ignored.

FIG. 8 is a bit configuration diagram of register OCR in mode 1 according to the embodiment of the present invention.

In the figure, bits bit7 to bit4 are an area for instructing mode 1, and mode 1 is set by writing OH in this area. Bit 3 is the short message interrupt flag SMI, and when this flag is “1”,
Section where short message interrupts are possible (MDR = 8 for long messages)
) generates a short message interrupt. It is also possible to interrupt the long message that the user is transmitting, and the short message interrupt operation can be performed completely independently of the transmission.

This flag is set when the status counter (MDR) becomes ``1'' or during the synchronization recovery period.
When it reaches "2", it becomes "0゛°.

Bit bit2 is a reset flag RES, and when this flag becomes "0", all states are returned to the initial state and operation is stopped.If this flag becomes "0" during transmission, transmission is aborted at that point. , if there are any remaining bits after that, those bits are not transmitted.

In addition, when this flag reaches 1°, it starts operating (synchronization recovery period begins).When the reset terminal is used to reset the IC, or when the power is turned on, the IC starts operating. It is necessary to set 1°.

Bit bitl is a reception interrupt mask flag RIM, and when this flag is “0”, reception, short message interrupt, data reception error, read lost data, framing error, parity error, A
Stop generation of CK/NAK error interrupts. however,
This flag only masks the output of the IRQ terminal.
The TR flag itself operates normally. Also, °“1°
When this happens, an interrupt is generated normally. This flag becomes "1" when the status counter (MDR) becomes "1" or when the period with no data on the bus continues for 10111s + 22bi and the synchronization recovery period is released. Even during the recovery period, an interrupt can be generated by writing "1°" to this flag.

Thereby, the receiving operation can be performed without waiting for the idle period of 10m5+22 bits.

Bit bitO is a transmission interrupt mask flag TIM, and when this flag is "0°", no transmission, contention loss, or write lost data interrupt is generated within one packet. However, this flag only masks the output of the IRQ terminal, and the 1NTR flag operates normally.

Also, when it is 1'', an interrupt is generated normally.This flag is set to IoIIIs + 22 when the status counter (MDR) reaches ``1°'' or when there is no data on the bus.
bi and becomes 1 when the synchronization recovery period is released.However, even during the synchronization recovery period, this flag does not change to “1°”.
An interrupt can be generated by writing .

FIG. 9 is a bit configuration diagram of register CCH in mode 2 according to the embodiment of the present invention.

In the figure, mode 2 is entered when bits bit7 to bit4 are OH. In this mode, bit bitl is broadcast WBRC, and if this flag is set to "1", the packet currently being sent/received will operate as a broadcast packet from now on.If it is set to "0", on the contrary, Operates as a packet.

Bit bitO is the long message flag LMf! S, and if this flag is set to 1''', the packet currently being sent and received will thereafter be treated as a long message packet.

'If "0" is set, it operates as a short message packet.

Status register (STR1) 31 is a read-only flag register indicating the status of the bus, packets, etc.

Note that FIG. 10 shows a bit configuration diagram of the status register (STR1) 31 according to the embodiment of the present invention.

In the figure, bit bit7 is an interrupt flag lNTR. This flag is a signal similar to the IRQ terminal, and becomes "1°" when an interrupt such as data input/output is required, and interrupts the CPU, that is, the microprocessor 11.The microprocessor 11 uses the status register (STR1 ) By reading 31, the IRQ terminal becomes "Ho" and this flag becomes "0".The state counter (MDR) of this flag becomes "1".

The status counter (MDR)
becomes "1" when becomes "2".

Bit bit6 is the short message interrupt flag R3MI.

It becomes "1" when a short message interrupt is detected (when the stop bit becomes "0" in the data part of a long message). Also, this flag has a status counter (MDR) of “1”.
The status counter (MDR)
becomes “'0°” when becomes “2°”. The determination of long messages is made using the "priority code", and when this flag becomes "1" (when a short message interrupt occurs), the FE (
Framing error) flag is not set.

Bit bit5 is a conflict negative flag CD. Competitive loss will be explained later, but if the sent data and received data are different in the "priority code" and "self address", it will be considered a "competitive loss", and this flag will be "1°". Therefore, the parity bit Even if the stop bits and stop bits are different, it will be a “competition loss”.

Bit 4 is the transmitting SORAG TX and becomes "1"' when transmitting data. Also, this flag is set to ``0'' when the status counter (MDR) reaches ``1'' or when the status counter (MDR) reaches ``2'' during the synchronization recovery period.
become. It also becomes "0" when the competition is lost (when the CD flag is set) or when a short message interrupt occurs (the part where MDR changes from 0 to 1 after the short message interrupt occurs).

However, when sending ACK/NAK after data reception, '1
'' (initial value: 0). Bit bit 3 is the error flag ERR and is the status register (ST
R2) 29 error flags (RDE, WLD.

RLD, PR, PE, AKB) is °“1°
This flag becomes “1” when the temperature reaches °. This flag is the result of ORing the error flags of STR2. It also becomes "011" when the status register (STR2) 29 is read or when the status counter (MDR) reaches "'1" or when the status counter (MDR) reaches "2" during the synchronization recovery period.

Bit bit2 is a broadcast flag BRC. When this flag is "1", it indicates that the message being received is a "broadcast" packet, and when it is "°0°", it indicates an "individual" packet. This flag is set to the value of bit 6 of the priority code when the status counter (MDR) reaches ``4''. Also, when the status counter (MDR) reaches ``1'' or during the synchronization recovery period, the value of bit 6 of the priority code is set. The counter (MDR) is “
When it becomes “2”, it becomes “OI+”.

Bit bitl is a data reception completion flag RXRDY. It becomes "°1°" when data can be passed to the microprocessor 11. microprocessor 1
1 becomes “0” when data is received, and when the status counter (MDR) reaches “°1” or when the status counter (MDR) reaches “2°” during the synchronization recovery period. “It becomes 0゛.

The bit bit is the transmission completion flag TXRDY.

When data can be received from the microprocessor 11, it becomes "°1", and the microprocessor 1
When data is received from 1, it becomes “0” (initial value: 1)
.

A status register (STR2) 29 is a read-only flag register indicating errors on the bus and packets.

Note that FIG. 11 shows a bit configuration diagram of the status register (STR2) 29 according to the embodiment of the present invention.

In the figure, bits bit 7 to bit 2 are error flags, which are set when an error packet occurs.

RDE and WLD read this register or when the status counter (MDR) reaches “2°” during the synchronization recovery period.
0°゛, and RLD, FE, PR, AKE
reads this register or the status counter (MDR) is “1”.
'' or during the synchronization recovery period, the status counter (MD
When R) becomes 2°°, it becomes 0pa.

Bit bit7 is a data reception error flag RDE, and in the embodiment of the present invention, synchronization is achieved with a start bit for each character during reception. At this time, if the start bit cannot be detected normally, this flag will be set to “1”.
become. It also becomes "I II" when more data than the message length code is received.However, this flag does not operate in the case of an error in ACK/NAK reception.In addition, when this flag becomes "1", the synchronization recovery period starts. enter.

Bit 6 is a write lost data flag WLD, and if character data has not been written to the transmission data register (TXDR) before the start of transmission of the next character, this flag becomes "'1". When this error occurs, transmission stops and a synchronization recovery period begins.

Bit bit5 is the read lost data flag RLD, and when data exists in the reception data register (RXDR), if the next data is input from the bus (at this time, the value of RXDR changes to new data). “
Become a bi. However, if you read status register (STR2) 29 and set it to "'0" without reading RXDR, the cause of the error has not been cleared, so this flag will be set again when the next interrupt occurs.The cause of the error is RXD
Clear by reading R (initial value: 0).

Bit bit4 is the framing error flag FE, and the stop bit is “1” except for the data part of the long message.
If it becomes 1°, it becomes 1°.

Bit bit3 is a parity error flag PE,
When the parity check circuit 24 described above detects a parity error, it becomes "1". In the embodiment of the present invention,
Parity is even parity.

Bit bit2 is the ACK/NAK error flag AKE, and the start bit of ACK/NAK is ±13
If it cannot be detected within the 11SO range, it will be "1°".

Bit BITO is a synchronization recovery period flag DRE, and immediately after reset or when a data reception error (RDE) or write lost data error (WLD) occurs, this flag becomes "'1" and the synchronization recovery period begins.

When the synchronization recovery period ends, this flag becomes "0" and the mode becomes normal mode.

Register 19 (status counter) MDR indicates the status of the broadcast packet, individual packet, etc. being received on the data bus HB. This is a read-only register that takes values from O (OOH) to 11 (OBH). In the embodiment of the present invention, data which is information in units of packets consisting of a plurality of codes is transmitted and received, and the status counter MDR also indicates the status of transmission and reception of these codes.

12 to 15 are state explanatory diagrams of the state counter according to the embodiment of the present invention, and FIG. 14 is an explanatory diagram of the operation of the status counter during the synchronization recovery period according to the embodiment of the present invention. FIG. 15 is an explanatory diagram of the operation of the status counter during the synchronization recovery period according to the embodiment of the present invention. FIG. 6 is an explanatory diagram of the operation of the status counter at the time of an ACK/NAK error according to the embodiment.

Each figure shows the value of the status counter and the status of the bus data at the time when the lNTR flag is set.

During the start bit, the previous state counter value continues.

A bit counter 35, an edge detection circuit 17, a pause counter 18, and a short message interrupt detection circuit 22 are connected to the state counter, that is, the register 19. Although not shown, the bit counter 35 receives signals from the sampling circuit 20 and the RX shift register 23, and calculates the currently received bit position. This bit counter 35
The current state of the data is determined based on the bit detection signal of the received data.

Note that FIG. 16 shows a state counter value and its state diagram according to an embodiment of the present invention, and FIG. 17 shows a state transition diagram according to an embodiment of the present invention.

Here, when the state counter value is 0, that is, the state SO is reset release, data exists on the bus, or the subsequent 2
A 2-bit or 44-bit period is a bus vacant detection period. In the state SO, a period of 208 μsec corresponding to 10 m5ec-22 bits after data is no longer received is an idle period (state Sl), and after this period, the state becomes S2.

The outputs of the bit counter 35, the edge detection circuit 17, and the packet status register 39 are added to the pause counter 18, and the pause counter 18 calculates the pause time from these outputs.

Status counter (MDR) 19 in the first half of the pause time is “°
In the "0" part, even if there is data on the bus, it is not recognized as a packet. If the time without data continues for 22 bits normally, or 44 bits in the case of broadcasting, the state changes to the next state.

This is for packets where the "telegram length code" and actual data length do not match, or for synchronization adjustment immediately after reset. In addition, in the embodiment of the present invention, the pause period 2
When a packet comes in at 2bit + 10m5, reception is performed in the same way as in normal times, and if the reception is successful without any errors, synchronization is restored.

Also, when transmitting, transmission starts after the pause time ends. However, if another device starts transmitting during the contention monitoring period, it will transmit accordingly.

If data is received while the status counter 19 is at "0", a data reception error occurs and a synchronization recovery period begins.

Thereafter, the status counter 19 becomes "2".

When the status counter 19 is “2”°, the home bus) (
When a transmission request is added from B, the state becomes 32'. Note that at this time, the value of the status counter 19 does not change. State S2 is a contention monitoring period and a data input waiting state. When data is present on the bus, state 33, 3
4,35. S6 and S37 are passed sequentially, that is, the value of the state counter 19 sequentially advances from 3 to 7, resulting in state S8.

Condition 33. S4, 35, 36. -37 is a priority code period, a self address period, a destination address period, a control code period, and a message length code period corresponding to the priority code, self address code, destination address code, control code, and message length code of the packet, respectively. States 82 to S8 are states in which data is received, and when the own address is received during the other party's address period, a normal packet is received. This results in a state in which synchronization has been recovered.

State 8 is a data period. In this state, when a short message interrupt exists in the data or information, the state counter 19 becomes 0. That is, the state is SO.

As shown in FIG. 30, which will be described later, the short message interruption detection circuit 22 receives the output of the state S8 of the state counter 19 and the received data R.
XD and the output of the stop bit signal detection of the bit counter 35 are added, and from the AND circuit AND,
When the value of the status counter 19 is 8 and the received data at that time is "θ' (it is "1" because it is inverted) at the stop bit position, "1" is output and the value is stored in the status register (STR1) 31. join. This allows detection of short message interruptions.

In the home bus HB system, short message interrupts can be generated from devices connected to the home bus.

In a home bus system, a short message interrupt can be performed by a device that interrupts the stop bit SP by outputting "0", that is, generating a pulse.This short message interrupt is detected by the short message interrupt. This is the detection circuit 22. That is, when the short message interrupt detection circuit 22 detects an interrupt, the detection signal is added, and the state counter 19 is reset to 0 (state SO).

Also, at this time, an interrupt detection signal is output to the transmission control section 33 to stop subsequent transmission control. At the same time, the short message interruption detection signal is also added to the status register (STRi) 31, and bit 6, the short message interruption flag R3, is added to the status register (STRi) 31.
Turn on MI to “1”.

When the data period (or data reception if it is reception) ends, the process moves to state S9. State 9 is a check code period, and after receiving the check code, state S10 is entered, which is a dummy code period.

Incidentally, when broadcasting is performed, the state is set to 0, that is, the state counter value is set to O. After the dummy code is an ACK/NAK period, during which the ACK/NAK signal is sent. After that, the state becomes SO.

On the other hand, when there is a transmission request in state S2, the state is 82' (the value of the state counter does not change) as described above.
Thereafter, state 33' (priority code period) is entered.

If a transmission request is issued to multiple devices at the same time and they send data, etc. at the same time, a conflict will occur. The home bus HB is configured to set a priority for each device when this conflict occurs, and when a conflict occurs, the device with the highest priority among the competing devices is given priority.

Priority is determined by priority code. Priority is DO
~D7, consisting of a total of 8 bits, with "oooooooo" being the highest and "11111111" being the lowest. When high priority and low priority codes simultaneously send out priority codes within the priority code period, each bit is output on the bus at the same time. Each bit is output at the same time, but as mentioned above, on the home bus, a pulse is output at “0”, and a pulse is output at “°1”.
Since the pulse is not output at “°”, “0”
The device that outputs the output forcefully sets the home bus bit to “0”.

On the other hand, a device with a low priority level is not “0°” but “1°”.
Since the data is sent out, the data will be different from the data on the path line. The competition detection circuit 21 detects this change in data.

In addition, the serial output SO of the TX shift register 25,
If the received signal RXD of the home bus driver/receiver 13 is in conflict with the received signal RXD, it is applied to the detection circuit 21 . Negative conflict means that the detection circuit 21 compares these two signals, that is, the received signal TYT and the serial output SO, and if SO and the received signal m match, the priority is high or there is no conflict. , it will not be a competitive loss.

However, if the priority code of another device is high, the code with the higher priority code is added as the received signal TY■, so the detection circuit 21 detects a mismatch and the higher level of the priority code is sent out. detects that
A mismatch signal is added to the transmission control section 33. As a result, the transmission control section 33 stops transmitting the priority code currently being transmitted.

At the same time, the status register (STR1) 31 is notified that the competition has been lost. In other words, the status register (ST
R1) Conflict negative on bit 5 of 31 turns flag CD on C
1''). FIG. 18 shows an explanatory diagram of competition according to the embodiment of the present invention.

In the figure, when a high-level priority code is sent from another device (IFU) and a low-level priority code is output from this device (IFU), this device outputs “°0” at code Do. Since there is no such thing, the competition will be lost.

Due to this competition loss, the lNTR flag of this device is further turned on at the next start bit. Furthermore, the transmission flag is turned off at the next start bit after the contention point. Further, the above-mentioned CD flag is turned on at the next start bit.

For example, if an interrupt is released, an interrupt IRQ is applied to the microprocessor 11.

The flag information of the register CCR32 is added to the interrupt control unit 36, and the flag information of the status register (STR1>31 is also added to the control unit 36.Interrupt control unit 36
This information is output to the microprocessor 11 via the buffer circuit 15 as an interrupt signal T11f.

Now, returning to the state transition diagram of the state counter according to the embodiment of the present invention shown in FIG. 17, if a contention loss occurs in state S3', the next transmission is not possible, so it is considered a contention loss. Therefore, the state S in the above-mentioned receiving state
3, and thereafter enters the receiving state.

Incidentally, FIG. 29 shows a logic circuit diagram of the competition negative detection circuit 21 according to the embodiment of the present invention. In the figure, when the home bus system is transmitting and the value of the status counter 19 is 3 or 4, an H (1") signal is applied to the AND circuit. Also, the received data
circuit, and its output is added to an AND circuit.

Also, if it is being sent and the status counter 19 is 3 or 4,
AN when the received data and the sent data are different.
If the contention is negative from the D circuit, the signal is sent to the status register (STR).
1) Added to 31 and stored. Conflicts are detected by such operations.

On the other hand, if no competitive loss has occurred, state 34'
Then, the self-address period begins. During the self-address period, when the bus control circuit in FIG. 3 transmits its own address, for example, the bus control circuit of FIG. 3 transmits the self-address of the home bus system. Also in the self-address period, a competition loss may occur as described above. For example, if a plurality of devices with the same level of priority codes exist on a single home bus, they compete in the priority code period, but none of the devices loses the competition.

Therefore, conflict must be detected again during the self-address period. Since there are no two identical addresses on one home bus, conflicts can be completely detected in this self-address detection. Detection of this conflict is also similar to the operation described above, and if the conflict is negative, the detection circuit 21
done by. When a competition loss occurs in this state 11s4', the above-mentioned receiving state S4 is entered.

On the other hand, when no competition loss is detected, the next state is S5', ie, the other party address period, in which the other party's address to be transferred is sent. When the transmission of the destination address is completed, a control code and a message length code are sequentially sent in a control code period (state 86') and a message length code period (state 87'), respectively. After that, data or information is sent out.

This data transmission occurs during the data period (state 88'). During data transmission (state 88') is the same as during data reception (state S8), and a short message interrupt may occur from another device. When this short message interruption occurs, it is detected by the short message interruption detection circuit 22 in the same way as in the receiving state, and the state counter 19 is set to 0. That is, at this time, the state is SO. When the data ends in the data period (state 88'), the next check code period (state 89') ends.
') and sends a check code. Then, after passing through a dummy code period (state 310'), an ACK/NAK period begins, in which an ACK or NAK signal is received from the receiving device, and the state becomes SO.

All changes in the count value of the state counter 19 mentioned above are made by the data edge signal from the edge detection circuit 17.

Note that there may be no change if the conditions are not satisfied.

For example, in the data period (state S8, 3B'),
It does not change until all data is completed or a short message interrupt occurs. Further, the period of state 1 is detected by a timer 38, and when a time-over signal is added to the state counter 19, the state counter 19 changes. The timer 38 is added to the transmission control unit 33, and the transmission control unit 33 starts transmission control in response to a time-over signal input from the timer 38.

The packet status register 39 includes the parallel output of the RX shift register 23, and is a circuit that detects the status of packets being transmitted and received, and includes statuses such as individual, broadcast, short message, and synchronization recovery. This state is added to the state counter 19 via the pause counter 18, and the state counter 19 changes accordingly.

In addition, Figures 12 to 15 are for individual time, broadcast time, and
FIG. 6 is an explanatory diagram of the operation of a state counter during an ACK/NAK error during a synchronization recovery period. At any time, the status counters 19 are sequentially 0, 1, 2, 3, 4 degrees 5.6, 7, 8.9.
and changes. In Figures 3 to 9, the bus data sequentially changes to a priority code, a self-address address, a control code, a message length code, data (information), and a check code. And when the synchronization recovery period is individual, it is 10
．． 11, there is a dummy code period and an ACK/NAK period.

Note that the synchronization recovery period is a period during which the device of this embodiment performs synchronization recovery. During this time, the bus data changes sequentially, and for example, this bus data is data transfer between other devices. Note that there may be cases where there is no transfer between other devices, no data is transferred, and the bus data does not change.

On the other hand, when broadcasting, the check code period is “0′”.
It becomes. This is because it is not necessary to send an ACK/NAK signal, and at this time there is no dummy code period and ACK/NAK period, and the 90th order is 0. Further, if an error occurs during the ACK/NAK signal, the state counter 19 does not change from the state of 10, but directly changes from 10 to 0.

The parallel output of the RX shift register 23 is added to the message length counter (MLC) 50, which takes in the parallel output of the RX shift register 23 when the status register 19 is 7 (state S7) in the receiving state, and converts the parallel output of the RX shift register 23 to 1 in the device S8.
It is a counter that decrements each time data or information is received.

For example, by reading the contents of the message length counter (MLC) 50 from the microprocessor 11, it can be determined how many more pieces of reception data should be received.

Incidentally, FIG. 28 shows an explanatory diagram of the operation of the bus data and message length counter (MLC) 50 according to the embodiment of the present invention. In the figure, when n is received as message length data, n is loaded into the message length counter (MLC) 50, and thereafter -1 (
(decrement) and becomes 0 when this code is received.

FIG. 19 is a data transmission operation chart according to an embodiment of the present invention, and the transmission operation will be explained based on the operation chart. In the figure, when the microprocessor 11 writes data to the transmission data register (TXDR), TXRDY decreases and preparation for transmission is completed (see FIG. 19). At this time, if the SMI flag is set, in the case of a long message, it can be transmitted sequentially by interrupt. Then, when it becomes possible to transmit, it automatically starts transmitting (see FIG. 19 - ). Thereafter, the TXRDY flag and the 1NTR flag become "'1" and an interrupt is generated to request the next transmission data (self address) from the microprocessor 11 (see FIG. 19 (2)). Thereafter, writing of transmission data is repeated in the same manner.

When the data being transmitted reaches a check code, the transmission and reception of the next character (dummy code) is stopped (Fig. 19).
Reference) Transmits and receives ACK/NAK.

Furthermore, the transfer of the transmission data to the microprocessor 11 ends when the last character of the data section is transmitted (the first
(See Figure 9 ■). Also, when data is written to TXDR after this, the first character (priority code) of the next packet
becomes.

Note that since the receiving operation is performed at the same time as the transmitting operation, manual interruption may occur after the "priority code" is transmitted (see FIG. 19 (2)).

On the other hand, the transmission operation in circular communication is as shown in the data transmission operation (circular) chart according to the embodiment of the present invention in FIG. This is similar to Figure 19.

FIG. 21 is a data reception operation chart according to the embodiment of the present invention, and the reception operation will be explained based on the operation chart.

In the figure, a reception operation is started when data on the data bus is input. After receiving one character, the RXRDY flag and the 1NTR flag become "1" and an interrupt IRQ is generated to prompt the microprocessor 11 to input data. The received data is passed to the microprocessor 11 after receiving one character, so the microprocessor receives the first character (priority code) in the MDR.
= 4 (see Figure 21 ■). The last data will be received when MDR=O (see Figure 21 -).

Furthermore, although AKR is used to transmit ACK/NAK, no special register is prepared for reception, and RXDR is used in the same way as other data. In addition, judgments regarding circulars and long messages are made in the second
This is done using a "priority code" as shown in the condition diagram for long messages and broadcasts according to the embodiment of the present invention in Figure 2.

The reception operation in broadcast communication is similar to that in Figure 21, as shown in the data reception operation (circular) chart according to the present invention in Figure 23, with individual reception only eliminating the transmission of ACK/NAK. It is.

The ACK/NAK transmission operation is performed by providing a dedicated register for ACK/NAK output as described above, and setting data in the ACK/NAK transmission register (8Ki+) after inputting the check code (Fig. 21). reference).

Also, if data is being transmitted or received, it will be transmitted no matter when it is set. (However, in the case of a circular message or a short message interrupt, the data must be set in advance.51) It will not be sent even if it is set. ) The reset flag (RES
) changes from "0" to "1" (when reset is released), and when a single packet error such as a data reception error or write lost data error occurs, the synchronization recovery process is performed again. At this time, the transmission/reception interrupt mask flag is “0”
', and no interrupt is generated to the microprocessor 11. These flags become "1°" when the synchronization recovery process is completed, and an interrupt is generated.

Furthermore, regarding transmission, synchronization recovery processing is not performed.

In addition, the synchronization recovery process is performed when the status counter (MDR) is “0”.
” → “2′” (status counter (MDR) is “
If data comes in when the status counter (MDR) is "0°", the data is received, but it is not recognized as a packet and is treated as a data reception error (ROE).If data comes in when the status counter (MDR) is "°2" (1) The synchronization recovery process is a normal packet (no parity error (PE) has occurred).

) is received or (2) the period with no data on the bus continues for Ioms+22 bits. However, if a parity error (PE) occurs in (1), the packet is treated as being out of synchronization, and the synchronization recovery process continues under either of the two conditions (1) or (2). This re-synchronization recovery process continues until this holds true.

In embodiments of the present invention, data reception error (RDE)
, Write Lost Data Error (LD), Read Lost Data Error (RLD), Framing Error (
FE), parity error (PE), ACK/NAK
Six errors (AKE) were detected. When a framing error (FE) or a parity error (PE) occurs, the flag is set to "1" and the error is notified to the microprocessor 11 by an interrupt.The reception operation then continues.

Write lost data error (WLD) and read lost data error (RLD) are checked at the time of transmitting and receiving the next data, and the flag is set to "1" to notify the microprocessor 11 of the error by an interrupt.

In the case of a read lost data error (RLD), the reception operation continues as is, but if a write lost data error (RLD) occurs, the reception operation continues as is.
WLD), the transmission operation is stopped and the synchronization recovery period described above begins.

When a data reception error (RDE) occurs, the flag is set to “1°”.
.

The state counter (MDR) is
) is set to "O" and the simultaneous recovery flag (DRE) is set to "1" to enter the synchronization recovery period.

When an ACK/NAK error occurs, the flag is set to "1" and an interrupt is generated. When this error occurs, the status counter (MDR) changes from "10" to "10" to "0". That is, when ACK/NAK cannot be detected, the period of MDR=10 becomes 22 bits.

In the case of any error flag, either read the status register (STR2) 29 or check the status counter (MD
It becomes "0" when R, ) becomes "1" or when the state counter (MDR) becomes "2" during the synchronization recovery period.

On the other hand, causes of interruption to the microprocessor 11 include input of transmission data, output of reception data, short message interruption, loss of competition, and error.

Detection of interrupt factors is performed using the TXRDY flag and RXRDY flag.
flag, short message interrupt flag, conflict negative flag, error flag, or status register (STR2)
This can be determined based on 29. Also, to reset the interrupt,
Either factor can be reset by reading the interrupt flag.

In the bus control circuit according to the embodiment of the present invention shown in FIG. 3, the edge detection circuit 17 is a circuit that detects the edge of data, that is, the start bit, and this circuit defines the start bit detection range and its width. to remove noise and detect data reception errors (
packet error).

Note that FIG. 24 is a circuit diagram of the start bit detection circuit, that is, the data edge detection circuit 17 according to the embodiment of the present invention.

In the figure, if this circuit is divided into functions, it determines the start bit position detection range and the start bit width detection range, respectively, and determines whether the start bit is within the range.

Note that it is added to the fall detection circuit 40 and rise detection circuit 41 of the received signal m. Further, the outputs of the falling detection circuit 40 and the rising detection circuit 41 are applied to a pulse width detection counter 43, and the pulse width detection counter 43 starts counting operation from the fall of the received signal to the rise of the received signal. Count the number of. Then, the counter number during that time is added to the range/pulse width comparison circuit 42.

Note that FIG. 25 shows an explanatory diagram of the start bit width detection range according to the embodiment of the present invention. In the figure, the start bit is 52μsec + 39μs after falling.
ec is specified as a range of -11.2 μsec, and the range
The pulse width comparator circuit 42 regards the bit within this range as a start bit. Then, it is output as a start bit valid, ie, data edge detection signal.

The start bit valid signal is also applied to the start bit detection range counter 44, which starts counting operation after the start bit becomes valid, and when the count value is in a specific range, a signal indicating the range is sent to the range counter 44. It is added to the pulse width comparison circuit 42.

The detection output of the falling detection circuit 40 is applied to the range/pulse width comparison circuit 42, and the range/pulse width comparison circuit 42 outputs the detection signal from the falling detection circuit 40 from the start bit detection range counter 44. It is detected whether the start bit is within the range indicated by the effective range instruction signal.

If an instruction is given, the pulse when a falling edge is detected from the falling edge detection circuit 40 is added as H, and if a signal that becomes H at the time representing within the range is added from the start bit detection range counter 44, the range/pulse is added. The width comparison circuit 42 calculates the AND logic of the two signals, and outputs a start bit valid signal when the result is "H" and the pulse width is within a specified value.

The above-mentioned "within the start bit effective range" defines the range of positions where the start bit falls.

Note that, as shown in the explanatory diagram of the start bit position detection range according to the embodiment of the present invention in FIG.
The period is valid.

Also, the start bit is not detected for all data, but for the second bit.
As shown in the explanatory diagram of the start bit position detection range according to the embodiment of the present invention in FIG. 7, the range is from X1 to X9.

The start bit detection circuit described above prevents noise and turns on the data reception error flag for incorrect messages, thereby increasing the effectiveness of data for packet errors and normal packets.

These constitute the home bus system according to the embodiment of the present invention, and regarding synchronization recovery of the data bus system,
As shown in the explanatory diagram of the synchronization recovery method according to the embodiment of the present invention in FIG. However, if the packet is a normal packet (2), it is assumed that the synchronization of the data bus system has been recovered.

Therefore, the conventional procedure of searching for a pause period (22 (bit) + 10 (ms)) even when individual packets are continuously transmitted on the data bus HB, for example, can be omitted. becomes possible.

Next, other specific examples of the present invention will be explained.

In other words, in the above-mentioned synchronization recovery method, the data received during the idle period or idle time is accepted regardless of whether the data bus system is synchronized or not, that is, the reception operation is performed. are easily influenced by it.

In terms of circuitry, a filter may be provided to remove pulse data with a certain width or less as noise, but there is a high possibility that pulse data with a width greater than that will be picked up and may cause the operation.

Therefore, in this specific example, in the above data bus system,
Only when the synchronization of each packet is out of synchronization, as shown in FIG. 34(b), the data transmitted during the pause period or the pause period is accepted, that is, the data transmitted is performed, and the above-mentioned method is used. When synchronization is restored and synchronization is established, data transmitted within that period is not accepted, that is, no reception operation is performed, as shown in FIG. 34(a).

Now, a case will be explained in which synchronization is achieved for each packet in the data system. Although this specific example can be used for both individual packets and broadcast packets, the broadcast packet will be explained. As shown in FIG. 35, the terminal FCC of the transmitted packet is received, and the count value of the status counter (MDR) at that time is "'9". Thereafter, the status counter is switched to 0 as the counter counts up. This state counter is “
When it is 0'', it indicates the bus empty detection period as shown in Figure 16, and is a period to detect whether or not extra data has arrived after a normal packet, and is set as a 44-bit time. .

This time may be set to 22 bits. This part corresponds to the part Tc in FIG. 34. Therefore, if no data is input during this period (when the status counter is O), it is determined to be normal as shown in FIG. 35, and the subsequent status counter is set to 1 to enter the suspension time or suspension period. During this period, even if data is input, no reception operation is performed and it is ignored. Therefore, even if noise occurs during this period, the system will not malfunction thereafter.

-Kichiji 36 As shown in the diagram, a malfunction occurs in the packet, and some extra data D appears after the FCC of the packet. Consider the case where is added. In this case, the synchronization is out of sync. Therefore, when a start bit of, for example, error data D is detected while the state counter is "0", a data reception error signal SE is generated, a synchronization recovery period signal K is generated, and a synchronization recovery period begins. Here, data reception error signal S
When E is detected, the status counter (MDR) is set to "2" by skipping "1" (point P) after the counter "0°" period (44 bits) has elapsed, and the status counter (MDR) is set to "2", waiting for data input. state.

In this specific example, the data acceptable period during this idle period is 10m5+22 bits-208u+DE period (22 bits).

In this specific example, all data input during this data acceptance period is received, but this data is simply used as a means of restoring synchronization between packets, and the data itself is not recognized, so it is not accepted in subsequent stages. This received data is not sent to the circuit.

That is, if this input data is normal packet data, it is determined that the position delayed by 10m5+22 bits from the end position of the input data is synchronized. Also, if noise comes in during this period, the pulse width can be selected by a width detection circuit and if it is noise, it can be removed.

In this specific example, we explained an example in which the packet data was longer than the normal data length, but it can also be applied when the packet data length is shortened due to reasons such as a connector being disconnected or the power being cut off. Similarly to the above, the pause period or the pause time may be taken from the last part of the packet data, and the status counter may be set to "0" by separately determining that the data is short, and then set to "2°".

A block diagram for implementing such a specific example is shown in FIG. In this figure, the same means as in FIG. 3 are given the same numbers.

A lock signal necessary for determining the detection range of the start bit is sent from the master clock for synchronizing the entire system to the edge detection section 17 via the clock generation circuit 16.
The receiving section 100 is also supplied with a clock signal (2) for data sampling. The received data is supplied to an edge detection section 17 and a reception section 100.

When the edge detecting section 17 detects the start bit of the extra data section in the packet data section of FIG. 36, an abnormality occurrence signal (2) is generated.

The conditions for abnormality to occur are (a) The start bit did not come where it was supposed to.

(b) When noise comes where the start bit should come.

(C) The start bit came in a place it shouldn't have come.

and so on.

The destination location is determined based on the values of byte counters, bit counters, etc.

When this signal ■ occurs, each counter 18.102°19
, 35 are reset, and counting is started by the output (■) of the bit counter 35.

As described above, when the edge detection section 17 detects an excess data portion and generates an error signal (2) (due to detection of a start bit), the pause counter (44-bit counter) 18 is reset.

When the pause counter 18 counts 44 bits during the period with no data, it outputs a count end signal (2), and the status counter changes from 1 to 2 depending on the presence or absence of an abnormality. Furthermore, the output (2) of the state counter is input to the edge detection section. 10m on the other hand
The 5-22 bit-208 μs counter 102 counts the pause period or pause time after the pause counter counts 44 bits. If the value of the state counter at that time is 1, the value of the state counter changes to 2, and if it is 2, the value of the state counter is maintained as it is by the count-up signal (2) of the counter 102. The edge detection section recovers from the out-of-synchronization state by this count-up signal (2), and ends the synchronization recovery period.

On the other hand, the receiving section 100 determines whether or not to receive the input data based on the output (2) of the edge detecting section.

〔Effect of the invention〕

As described above, according to the present invention, when the received data is not a one-packet error but a normal packet, it is possible to restore the synchronization of the data bus system.

This makes it possible to quickly restore the synchronization of the data bus system.

Furthermore, according to the present invention, it is possible to prevent data from being accepted while no synchronization is occurring, so that the influence of noise can be significantly reduced.

[Brief explanation of drawings]

FIG. 1 is a principle flowchart of a synchronization recovery method in a data bus system of the present invention, FIG. 2 is a block diagram of a data bus system according to an embodiment of the present invention, and FIG. 3 is a flowchart of the principle of a synchronization recovery method in a data bus system of the present invention. A configuration diagram of a bus control circuit of a data bus system. FIG. 4 is a data configuration diagram according to an embodiment of the present invention. FIG. 5 is an explanatory diagram of TYT and TXL data according to an embodiment of the present invention. is a home bus driver according to an embodiment of the present invention.
The transmitting circuit diagram of the receiver 13, FIG. 7, is a register (TXDR/
AKR) 2B; FIG. 8 is a bit configuration diagram of register 0CR (mode 1) according to the embodiment of the present invention; FIG. 9 is a bit diagram of register 0CR (mode 2) according to the embodiment of the present invention. 10 is a bit configuration diagram of status register STR1 according to an embodiment of the present invention. FIG. 11 is a bit configuration diagram of status register STR2 according to an embodiment of the present invention. FIG. 12 is a diagram of the bit configuration of status register STR2 according to an embodiment of the present invention. FIG. 13 is an explanatory diagram of the operation of the status counter at the time of an individual packet according to the embodiment of the present invention. FIG. 14 is an explanatory diagram of the operation of the status counter at the time of a broadcast packet according to the embodiment of the present invention. FIG. 16 is a state counter value and its state diagram according to the embodiment of the present invention; FIG. 17 is a state transition diagram of the state counter according to the present invention; FIG. 18 is an explanatory diagram of competition according to the embodiment of the present invention, the first
9 is a data transmission operation chart according to an embodiment of the present invention, FIG. 20 is a data transmission operation (circular report) chart according to an embodiment of the present invention, and FIG. 21 is a data reception operation chart according to an embodiment of the present invention. Operation chart, FIG. 22 is a condition diagram of long message and broadcast according to the embodiment of the present invention, FIG. 23 is a receiving operation (circular message) chart according to the embodiment of the present invention, and FIG. 24 is a diagram of the present invention. FIG. 25 is an explanatory diagram of the start bit width detection range according to the embodiment of the present invention. FIG. 26 is a diagram of the start bit position detection range according to the embodiment of the present invention. FIG. 27 is an explanatory diagram of the start bit position detection range according to the embodiment of the present invention. FIG. 28 is an explanatory diagram of the operation of the message length counter according to the embodiment of the present invention. FIG. 30 is a logic circuit diagram of a competition loss according to an embodiment of the present invention. FIG. 31 is a logic circuit diagram of a short message interrupt according to an embodiment of the present invention. Such explanatory diagrams, FIG. 32 (aL) (b) are diagrams explaining the synchronization recovery method according to the conventional example, and FIGS. 33 (a) and (b) explain the problems of the synchronization recovery method according to the conventional example. Fig. 34 is a diagram illustrating another embodiment of the present invention. Fig. 35 is a diagram illustrating operation in a state where no synchronization shift occurs in another embodiment of the present invention. Fig. 36 is a diagram illustrating the operation in a state where synchronization has occurred in another embodiment of the present invention. Fig. 37 is a block diagram embodying another embodiment of the present invention. (Explanation of symbols) 11... Microprocessor, 12... Bus control circuit, 13... Home bus driver/receiver, 14...
Fundamental frequency generator, 1... Home bus controller, 2... Information equipment, 3. HB: Home bus, 4: The relevant packet, 5: Previous packet, A-: Pause period, fixed period (22 (bit) +
10 (ms)) T a ... Pausing period (10 (ms)
), TF...Synchronization recovery monitoring time (208 (μs)
]), 17... Edge detection unit, ■9... Status counter, 35... Bit counter, 100... Receiving unit, 101... Check code counter, 102 = 4
0ms-22bit-208u counter.

Claims (1)

[Scope of Claims] 1. In a data bus system that transmits serial data including a standardized idle period or idle time via a data bus, the data bus system performs a receiving operation regardless of whether or not synchronization is performed, and one packet A method for recovering synchronization in a data bus system, characterized in that a state in which synchronization has been recovered is achieved when no errors occur and normal packets are received. 2. In a data bus system that transmits serial data that includes a standardized idle period or idle time via a data bus, when each packet is out of synchronization, the data that is received during the idle period or idle time is A state in which synchronization has been achieved is when data is accepted, no single packet error occurs, and normal packets are received.On the other hand, when synchronization is established, the received data is stored for that period. A method for recovering synchronization in a data bus system, characterized in that data bus systems are not accepted within the data bus system.