JPH01122228A - Bus control circuit - Google Patents

Abstract

PURPOSE:To detect transfer of data due to noise or malfunction by obtaining the width and the position of a start bit of serial data to discriminate whether the start bit is effective or not. CONSTITUTION:A pulse width detecting circuit 1 obtains the pulse width of the start bit of serial data. A pulse position detecting circuit 2 detects the positions of the rise and the fall of the start bit. These detection results are applied to a pulse position and width comparing circuit 3, and the circuit 3 compares the pulse width of the start bit with a preliminarily determined specific width. The circuit 3 discriminates whether the start bit is placed in a specific time position from the position of the preceding start bit. If it is within a specific range as the result of comparison, the circuit 3 outputs an effective start bit signal.

Description

[Detailed Description of the Invention] [Summary] An object of the present invention is to provide a bus control circuit that detects a start bit without error and ensures data reception with respect to a bus control circuit that receives serial data via a data bus. In a data bus system that transmits serial data via a data bus, a pulse width detection circuit detects the pulse width of a start bit of the serial data to which the serial data is added; A pulse position detection circuit detects the time position of the start bit of the pulse width detection circuit, and the detection results of the pulse width detection circuit and the pulse position detection circuit are added, and the pulse width detection result is compared to see if it is a specific pulse width. , a pulse position/width comparison circuit that compares whether the start bit position detection result exists within a specific time period and outputs a valid start bit signal when the condition is satisfied.

[Industrial application field]

The present invention relates to a data bus system that transmits serial data via a data bus, and more particularly to a bus control circuit that receives serial data via a data bus.

[Traditional technique]

In home bus (HB) systems, a serial data transfer method is generally used. Serial data transfer is a method of sequentially transmitting parallel data bit by bit, and is used in each direction because it requires fewer transmission paths.

In this serial data transfer, a start bit and a stop bit indicating the start of data are added before and after the data. The start and stop bits allow the start and end of serial data to be detected. For example, the data is each logic, and the start bit is "L" and the stop bit is H, which are added before and after the data, so the receiving device detects the "L" start bit and determines the starting point of the data. .

[Problem that the invention seeks to solve]

Conventionally, the aforementioned start bit "H" simply detected a change from "L" to "H". Therefore, if a pulse exists in the vicinity due to noise or the like, that pulse may be mistakenly used as the start pulse.

SUMMARY OF THE INVENTION In view of the above-described drawbacks of the prior art, it is an object of the present invention to provide a bus control circuit that detects a start bit without error and ensures data reception.

[Means for solving problems]

FIG. 1 is a block diagram of the present invention. The pulse width detection circuit 1 is a circuit that detects the pulse width of the start bit of serial data added from the data system, and the pulse position detection circuit 2 is a circuit that detects the position of the start bit of serial data added from the data system.
The width comparison circuit 3 compares the width information added from the pulse width detection circuit 1 to see if the width of the pulse is within a specific range, and also calculates, for example, the expected position of the next start bit from the position of the previous start bit. This circuit compares whether the position is within a specific range from that position and outputs an unchanged start bit signal when the position is within the specific range.

[For production]

When serial data is applied from the data bus to the pulse width detection circuit 1 and pulse position detection circuit 2, the pulse width detection circuit 1 determines the pulse width of the start focus of the serial data. Further, the pulse position detection circuit 2 detects the falling and rising positions of the start bit. For example, if the start bit is "O", the position of change from "1" to "O" is determined. The detection results of these pulse widths and pulse positions are applied to a pulse position/width comparison circuit 3, and the pulse position width comparison circuit 3 compares whether the pulse width of the start bit is a pulse of a predetermined specific width. Then, it is further compared whether the start bit is at a specific time position from the previous start bit position, for example. In this comparison, when the pulse position and width comparison circuit 3 is within a specific range, the pulse position and width comparison circuit 3 outputs a valid start bit signal. It determines whether the width of the start bit is within the specified width position, then determines the next position based on the relationship with the previous start bit, and determines whether that position is within the specified range. Therefore, data transfer due to noise or malfunction can be detected.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 2 is a system configuration diagram of an embodiment of the present invention. The microprocessor 11 and the bus control circuit 12 are connected to a data bus (
DATA (Do-D7)) line and address bus (Ao=
A2) line, chip select (]) line, write signal (W bottom) line, read signal (RD) line, reset signal (RESE)
T) line and an interrupt signal (IRQ) line. Bus control diagram 1 connected to these signal lines? i! 12
The terminals are for the following. The terminal connected to the address bus Ao=A2 is an internal register (the bus control circuit 12 in the embodiment of the present invention will be described later).
This is a terminal for selecting the registers TXDR, RX
DRSAKR, CCR, 5TRI, 5TR2, MDR,
One of the MLCs is selected. The chip select signal terminal is a terminal that is added to the bus control circuit 12 when the microprocessor 11 selects it, and is selected when the signal is "L", allowing writing to and reading from each register of the bus control circuit 12.The write signal terminal is The read signal terminal is a terminal that applies an "L" signal when writing data to each register, and the read signal terminal is a terminal that applies an "L" signal when reading data from each register.When "L' is applied to the write signal terminal, the address The data applied from the data bus is stored in the register specified by the address value applied from the signal terminal, that is, the register specified value, and when "L" is applied to the read signal terminal, the register specified by the register specified value applied from the address signal terminal is stored. Output the contents to the data bus.

The reset terminal is a terminal for resetting the bus control circuit 12, and when "L" is applied, the bus control circuit 12 initializes the values of each register.

The interrupt signal terminal is a terminal to which the bus control circuit 12 outputs, and for example, when 1 byte of data is received, L'' is output from the terminal.

Although not shown in the microprocessor 11, there is a ROM and RA.
It executes a program stored in the ROM and transmits and receives control data and the like to a control channel (CH) of the home bus, which will be described later, via the bus control circuit 12. In addition to the address buses Ao to A2, the microprocessor 11 has upper bits of the address bus, for example, AI5 to A3, and the ROM-? )RAM
etc. are connected to these address buses A+5 to Ao and operate as a processor/nosa circuit.

On the other hand, the bus control circuit 12 has terminals (HB data (RXD) input terminal, HB data (+) direction output terminal, HB data (-) direction terminal) connected to the home bus driver/receiver 13 in addition to the above-mentioned terminals. ), and further has a clock input terminal to which a clock signal CLK from the fundamental frequency generator 14 is applied. Fundamental frequency generation 114 is 4.9M
The bus control circuit 12 outputs a clock signal of Hz or 614°4KIIz, and when a signal of one of these two frequencies is added, the bus control circuit 12 outputs a clock signal to which a clock select signal (C3EL) indicating the frequency is added. It also has a select terminal.

FIG. 3 is a circuit diagram of the bus control circuit 12.

The aforementioned data (DATA), address signal A.

~A2, write signal WR, read -fRD, chip select signal C8, reset signal RESET, clock signal CLK, interrupt signal IRQ, clock select signal C3
EL is added to a buffer circuit 15 (CPtJ-110), which applies these signals to each intended circuit.

Clock signal CLK is applied to clock generation circuit 16 and edge detection circuit 17 as a mask clock. The clock generation circuit 16 generates a clock for each circuit, which will be described later, and applies it to each circuit.

The edge detection circuit 17 receives received data, that is, HB data (RX D), and when the edge detection circuit 17 detects the edge of data from the master clock, it outputs the data edge to a rest counter 18 and a status counter (MDR) 19, which will be described later. It outputs that it has been detected, that is, that it has started receiving data.

In addition to the edge detection circuit 17, the LI B data (RX D) is applied to a sampling circuit 20, the contention quality is applied to a detection circuit 21, and a short message interrupt detection circuit 22.

The HB data is, for example, serial data of 9600 bps, and the sampling circuit 20 sequentially reads the serial data bit by bit and adds it to the RX shift register 23.

The home bus HB in FIG. 2 is, for example, two twisted wires. The home bus driver/receiver 13 sends signals to the home bus HB or receives signals from other devices. The signal output to the home bus HB consists of 11 bits per piece of data. Figure 4 shows
This is a data configuration diagram, where 1 data is a 1-bit start bit ST.

゛ 8-bit transfer information (transfer data BO-B7),
It consists of one parity bit (PA) and one stop bit (SP). Home bus HB
In this case, there is a pulse in the positive or negative direction when it represents "L"("O"), and there is no pulse when it represents "H"("1'). Note that the start bit is always "L"(O"), the stop bit is always "H"("1"), and the data BO-87 in FIG.
is always converted into an Oll signal by the home bus driver/receiver 13, and the received data R
It is added to the bus control circuit 12 as XD. The sampling circuit 20 is a circuit that sequentially samples 0.1 signals. RX shift register 23 is sampling circuit 2
Each bit of 1 transfer information added in 1 bit units from 0) BO
- Receive and shift BT. At this time, each time the RX shift register 23 shifts data, the data is also output to the parity check circuit 24, and the parity check circuit 24 counts the number of O or 1 bits in one transfer information, and Compare with the parity added after the transfer information. This parity is a conventional even number parity or odd number parity, and each time one transfer information is received, it is determined whether the data is normal or not, and if it is not normal, the data abnormality is stored in the status register (STR2) 29. .

The RX shift register 23 is a serial-in, parallel-out shift register, and every time one transfer information is received, the 8-bit information is transferred to the reception data register (RXD).
R) Store in 30. As will be explained later, the receive data register (
When one transfer information is stored in the status register (STRI) 30, the microprocessor 11 transmits a signal that turns on a flag that allows reading this data.
)Add to 31. By this storage, for example, when the processor reads the status register (STRI) 31 and the reception flag is on, it can recognize that 1 byte of information has been transferred to the reception data register.

Each of the circuits described above can receive data from the home bus HB.

The register (TXDR/AKR) 28 is a transmission buffer for transmitting transfer information and the like to other devices via the home bus HB. The microprocessor 11 uses this register (
When TXDR/AKR) 2B is selected and transfer information etc. is stored, the TX shift register 25 reads it, adds a start bit, and sequentially outputs 1-bit serial data SO.
The contention negative signal is output to the AM1 circuit 26 and the detection circuit 21. Incidentally, 8-bit data to be transferred is added to the parity generation circuit 27 via the TX shift register 25, and parity is generated corresponding to the data to be transferred.
The parity is added to the TX shift register 25. As shown in the data configuration diagram shown in FIG. 4, this parity is inserted into the parity bit position following one transfer information BO-BT, and the TX shift register 25 outputs the parity bit PA. After the parity bit PA, the TX shift register 25 inserts a stop bit SP and finishes transmitting one data.

A control signal is added to the transmission control section 33 from the control code register (OCR) 32.
3 is the register mentioned above (TXDR/AK) by this signal.
Data is read from R) 28 to the TX shift register 25, and a signal is applied to the TX shift register 25 to control transmission in units of one bit sequentially. Through this control, the aforementioned serial data SO is transferred to the TX shift register 25.
is output from. In the home bus HB, in order to eliminate the direct current component of the current during serial data transfer, the data is transmitted by pulses in the positive and negative directions as shown in Figure 4.
The AMI circuit 26 is responsible for controlling this repetition and generating control signals to output pulses in the positive and negative directions.This AMI circuit 26
For example, when the serial data is "00000000001" as shown in Fig. 4, the transmitted data signals TXH and TXL are as shown in Fig. 5, and TXHSTXL is sequentially pulsed in the positive direction and negative direction. is generated to represent "0".

FIG. 6 is a transmitting circuit diagram of the home bus driver/receiver 13. Transmission data TXH and TXL are applied to the base of transistor T r l % T r 2 via inverters 1 and 2, respectively, and resistors R1 and R2. The emitters of the transistors Tr+ and Tr2 are grounded, and the collectors are connected to both ends of the primary side of the transformer L, whose intermediate point on the primary side is connected to the power supply V. Both ends of the secondary side of the trunk L are connected to the home bus HB via capacitors C1 and C2. Transmission data TXH
is added to inverter ■1, so in the case of the configuration shown in Figure 6, bits 5TO1B1, B3, B5, B
At 7, transistor Tr+ is turned on. Furthermore, since the transmission data TXL is applied to the inverter 2, the transistor Tr2 is turned on at bits BO, B2, B4, B6, and PA.

When the transistor Tr+ is turned on, a current flows from the power supply ■ to the terminal connected to the transistor Tr+ via the intermediate point on the primary side, and as a result, a pulse in the positive direction is output to the home bus HB. Ru. On the other hand, when the transistor Tr2 is turned on, the opposite is true.
A negative direction pulse is output to the home bus HB. Incidentally, the capacitors C1 and C2 are elements for connecting to a DC set and a low frequency band. Since there are cases where power is supplied via the home bus HB, the DC component is cut by this capacitor.

In the transmission of each piece of information on the home bus HB, an acknowledgment signal ACK or a NACK signal NAK is sent to determine whether or not the device to which the data was sent has received the data. This acknowledge signal ACK and NACK signal NA
K is treated as data to be transmitted, that is, a piece of information in boat fishing. For this reason, conventionally there is one register for storing data to be transmitted, but in the present invention two registers are provided, one for this data and one for an anchor. FIG. 7 is a configuration diagram of the register (TXDR/AKR) 28.

8-bit data from the buffer circuit 15 is stored in a data register 28-1 and an ACK/NAK register 28-2. As will be described later, this data register (TXDR) 28-1 and ACK/NAK register 28
-2, the data is stored separately via the buffer circuit 15. The transmission control unit 33 adds a selection signal for selecting these registers to the register (TXDR/AKR) 2B, and this selection signal is applied to the selector 2 in FIG.
Enter in 8-3. The selector 28-3 selects the data of the data register 28-1 or the ACK/NAK register 2.
The selected data is added to the TX shift register 25. Conventionally, the configuration is such that the data in one register is sent out as described above, but as shown in the configuration shown in Figure 7, the data that is the information to be sent out is stored in two registers, and the data as needed is stored in two registers. At the appropriate time, the register is selected and sent. The selection of this register is made depending on the purpose of sending out information or an ACK signal, etc., and writing from the microprocessor 11 to the register is not only a conversion of the write, but also a writing process depending on the purpose.
You can create a program without detecting the data or ACK signal procedure.

The embodiment of the invention shown in FIG. 3 has eight registers, and these registers are read or written via a buffer circuit 15. Write to register CCR,
TXDR/AKR, and are written to the respective target registers in response to instructions from the buffer circuit 15, that is, write instructions from the microprocessor 11. Read from registers RXDR, CCR, 5TRI, 5TR2,
MDR and MLC, and the data select circuit 34 selects the output of each according to the value of the address signal Ao=A2, and outputs the selected output to the data (DATA) bus of the microprocessor 11 via the buffer circuit 15.

Transmission data register TXDR is a write-only 8-bit register. Data sent on the bus is ACK/N
Other than AK, the microprocessor 11 writes to this register. Also, by writing data to this register, a series of data transmission operations is started. The reception data register RXDR is an 8-bit register dedicated to reading home bus data. Register AKR (ACK/
The NAK transmission register is a write-only 8-bit register for ACK/NAK transmission. When a value is written to this register, data is sent during the next ACK/NAK transmission possible period. However, if transmission is unnecessary due to broadcast, short message interruption, or error (data reception error, write lost data error), it will not be transmitted, and it will not be transmitted over the next packet. The control code register OCR is a readable and writable flag register for control purposes. Mode 1 is selected by setting the upper 4 bits to 0H (hexadecimal), and mode 2 is selected by setting the upper 4 bits to 6H. Further, when canceling the reset, OCR flags other than the RES flag are ignored.

FIG. 8 is a bit configuration diagram of register OCR in mode 1. Bits bit 7 to bit 4 are an area for indicating mode 1, and mode 1 is set by writing OH to this area. Bit 3 is the short message interrupt flag SMI, and when this flag is “1”, the interval in which short message interrupts are possible (MDR-8 for long messages)
) generates a short message interrupt. It is also possible to interrupt the long message that the user is transmitting, and the short message interrupt operation can be performed completely independently of the transmission.

This flag is set when the status counter (MDR) becomes "1" or when the status counter (MDR) becomes 2 during the synchronization recovery period.
”, it becomes “O゛”.

Bit 2 is a reset flag RES, and when this flag becomes "O", all states are returned to the initial state and the operation is stopped. If this flag becomes "0" during transmission, the transmission is aborted at that point, and if any bits remain, those bits are not transmitted. Further, when this flag becomes "1", the operation starts (synchronization recovery period begins). It is necessary to set 1'' from the microprocessor 11 in order to start the operation of this IC when a reset is applied by the reset terminal or when the power is turned on.

Bit 1 is the reception interrupt mask flag RIM, and when this flag is “O”, reception, short message interruption, data reception error, read lost data, framing error, parity error, A
Stop generation of CK/NAK error interrupts. however,
This flag only masks the output of the IRQ terminal.
The NTR flag itself operates normally. Also, “1”
An interrupt is generated normally. This flag becomes "1'" when the status counter (MDR) becomes "1" or when the synchronization recovery period is canceled after a period in which there is no data on the bus continues for 10m5+22 bits. However, even during the synchronization recovery period, an interrupt can be generated by writing "1" to this flag.

Bit BITO is a transmission interrupt mask flag TIM, and when this flag is "0", no interrupt for transmission, contention loss, or write lost data is generated within one packet. However, this flag only masks the output of the IRQ terminal, and the 1NTR flag operates normally. Also, when it is "1", an interrupt is generated normally. This flag is set when the status counter (MDR) becomes "1" or when there is no data on the bus.
Then, it becomes "1" when the synchronization recovery period is released. However, even during the synchronization recovery period, an interrupt can be generated by writing "1" to this flag.

FIG. 9 is a bit configuration diagram of register OCR in mode 2. Mode 2 is entered when bits bit7 to bit4 are OH. In this mode, bit 1
is a broadcast WBRC, and when this flag is set to "1", the packet currently being transmitted and received thereafter operates as a broadcast packet. Conversely, if "0" is sent, the packet operates as an individual packet.

Bit BITO is the long message flag L, MES, and if this flag is set to 1'', the packet currently being sent/received will operate as a long message packet from now on.If it is set to 0, it will be used as a short message packet. It works as.

The status register (STRI) 31 is a read-only flag register that indicates the status of the bus, packets, etc. FIG. 10 is a bit configuration diagram of the status register (STRI) 31.

Bit bit 7 is the interrupt flag lNTR. This flag is a signal similar to the IRQ terminal, and becomes "1" when an interrupt such as data input/output is required, and interrupts the CPU, that is, the microprocessor 11. The microprocessor 11 registers the status register (STRI).
) 31, the IRQ terminal becomes 'H' and this flag becomes 10''. This flag becomes 1'' when the status counter (MDR) becomes ``1'' or when the status counter (MDR) becomes ``2'' during the synchronization recovery period.

Bit 6 is the short message interrupt flag R3MI.

It becomes 111 when a short message interrupt is detected (when the stop bit becomes "0" in the data part of a long message).

Also, this flag is set when the status counter (MDR) reaches 1 or when the status counter (MDR) reaches 2 during the synchronization recovery period.
”, it becomes “0”.Long messages are determined by the “priority code”, and when this flag becomes “1” (when a short message interrupt occurs), an FE (framing error) is detected. No flags are set.

Pinto bit 5 is the conflict negative flag CD. We will discuss losing the competition later, but this flag is the "priority code"
If the transmitted data and received data are different in the ``self address'' and ``self address'', it is assumed that the ``competition has been lost'' and this flag becomes ``1''. Therefore, even if the parity bit and stop bit are different, it will be a "competition loss".

Bit 4 is a transmitting flag TX, which becomes "1" when transmitting data. Further, this flag becomes "0" when the state counter (MDR) becomes "1" or when the state counter (MDR) becomes "2" during the synchronization recovery period. It also becomes "O" when the competition is lost (when the CD flag is set) or when a short message interrupt occurs (the part where MDR is 0-1 after the short message interrupt occurs). However, ACK/
It does not become "1" when sending a NAK (initial value: O).

Bit 3 is the error flag ERR, and the error flag (RDF
, WLDSRLD, FBSPHSAKE) becomes "1", this flag becomes 11. This flag is the OR of the error flags of 5TR2. Also, the status register (STR2) 29 It becomes 0'' when the status counter (MDR) becomes ``1'' or when the status counter (MDR) becomes ``2'' during the synchronization recovery period.

Bit bit 2 is the broadcast flag BRC. When this flag is "1", it indicates that the message being received is a "broadcast" packet, and when it is '0', it indicates an "individual" packet. This flag has a status counter (MDR) of 4.
”, the value of bit 6 of the priority code is set.Also, when the status counter (MDR) reaches 61'' or during the synchronization recovery period, the value of bit 6 of the priority code is set.
When it becomes ``O''.

Bit 1 is a data reception completion flag RXRDY. When data can be passed to the microprocessor 11, “11” appears.Microprocessor 11
When it receives data, it becomes “OS” and becomes “0” when the status counter (MDR) becomes “1” or when the status counter (MDR) becomes “2” during the synchronization recovery period. Become.

Bit bit O is the transmission completion flag TXRDY.

It becomes "1" when data can be received from the microprocessor 11, and the microprocessor 11
When data is received from , it becomes "O" (initial value: 1).

The status register (STR2) 29 is a read-only flag register indicating errors on the bus and packets. Figure 11 shows status register (STR2) 29
FIG. bit bit 7 to bit 2
is an error flag, and is sent as a cent when an error occurs.

RDE and WLD read this register or when the status counter (MDR) becomes "2" during the synchronization recovery period, the value is 10'.
In addition, RLDSFE, PE, and AKE read this register or when the status counter (MDR) becomes “1” or when the status counter (MDR) becomes “2” during the synchronization recovery period.
When it becomes 10”.

Bit 7 is a data reception error flag RDE, and in the embodiment of the present invention, synchronization is achieved with a start bit for each character during reception. At this time, if the start bit cannot be detected normally, this flag will be set to “1”.
”. Also, it becomes “1” when more data than the message length code is received. However, this flag does not operate in the case of an error in receiving ACK/NAK. Furthermore, if this flag becomes “1”, Entering the synchronization recovery period.

Bit 6 is a write lost data flag WLD, and if character data has not been written to the transmission data register (TXDR) before the start of transmission of the next character, this flag becomes "1". When this error occurs, transmission stops and a synchronization recovery period begins.

Bit 5 is the read lost data flag RLD, and if the next data is input from the bus while there is data in the receive data register (RXD R) (at this time, the RXDRO value changes to new data). ) becomes “1”. However, if the status register (STR2) 29 is read and set to "0" without reading RXDR, the cause of the error has not been cleared, and this flag will be set again when the next interrupt occurs. The cause of the error is cleared by reading RXDR (initial value 20).

Bit bit 4 is the framing error flag FE, and the stop bit is 1″ outside the data part of the long message.
If it becomes, it becomes “1”.

Bit 3 is a parity error flag PE, which becomes "1" when the above-mentioned parity check circuit 24 detects a parity error. In embodiments of the invention, the parity is even parity.

Focus bit 2 is ACK/NAK error flag AKE
The start bit of ACK/NAK is ±13μs.
If it cannot be detected within the range, it becomes "1".

Bit bit O is the synchronization recovery period flag DRE,
Immediately after resetting or when a data reception error (RDE) or write lost data error (WLD) occurs, this flag becomes "1" and a synchronization recovery period begins. When the synchronization recovery period ends, this flag becomes 10'' and the normal mode is entered.

Register 19 (status counter) MDR indicates the status of the packet being received on the bus. 0 (OOH) ~ 11 (OB
This is a read-only register that takes values up to H). In the embodiment of the present invention, data, which is information, is transmitted and received in units of packets consisting of a plurality of codes, and the status counter MDR also indicates the status of transmission and reception of these codes.

12 to 15 are state explanatory diagrams of the state counter. Each figure shows the value of the status counter and the status of bus data at the time when the lNTR flag is set. During the start bit, the previous state counter value continues.

A focus counter 35, an edge detection circuit 17, a pause counter 18, and a short message interrupt detection circuit 22 are connected to the state counter, that is, the register 19. Although not shown, the focus counter 35 receives signals from the sampling circuit 20 and the RX shift register 23, and calculates the currently received bit position. This bit counter 35
The current state of the data is determined based on the bit detection signal of the received data. FIG. 16 is a state counter value and its state diagram, and FIG. 17 is a state transition diagram. When the state counter value is 0, that is, state s.

is a period in which a reset is released, data is present on the bus, or a subsequent 22 bit or 44 bit period is detected as an empty bus. In that state SO, 105m5ec - 22 bits of time - 12 since no data was received
08 μsec is a rest period (state Sl), and after this period, the state becomes S2.

The outputs of the focus counter 35, the edge detection circuit 17, and the packet status register 39 are added to the pause counter 18, and the pause counter 18 calculates the pause time from these outputs.

Status counter (MDR) 19 during the first half of the pause time is “0”
In this section, even if there is data on the bus, it is not recognized as a packet. When the time without data continues for 22 bits normally, or 44 bits in the case of broadcasting, the state changes to the next state. This is for packets where the "telegram length code" and actual data length do not match, or for synchronization adjustment immediately after reset.

When sending, start sending after the pause time ends. However, if another device starts transmitting during the contention monitoring period, it will transmit accordingly.

If data is received while the status counter 19 is at "0", a data reception error occurs and a synchronization recovery period begins.

Thereafter, the status counter 19 becomes 2''.

When the status counter 19 is 12'' and a transmission request is added from the home bus HB, the state becomes S2'. At this time, the value of the status counter 19 does not change. Status rA3
2 is a contention monitoring period and a data input waiting state. When there is data on the bus, states S3, S4,
S5, S6, and S7 are passed sequentially, that is, the state counter 19
The value progresses sequentially from 3 to 7, resulting in state S8.

States S3, S4, S5, S6, and S7 are the priority code period, self address period, destination address period, and control code period corresponding to the priority code, self address code, destination address code, control code, and message length code of the packet, respectively. , is the message length code period. States is2 to S8 are states in which data is received, and when the own address is received during the other party's address period, data is received.

State 8 is a data period. In this state, the state counter 19 becomes 0 when there is a short message interrupt in the data or information. That is, the state is SO.

As shown in FIG. 30, the cover layer message interrupt detection circuit 22 includes the output of the state S8 of the state counter 19, the received data RXD, and the output of the stop bit signal detection of the bit counter 35, and from the AND circuit AND, When the value of the status counter 19 is 8 and the received data at that time is “O” (it is 1 because it is inverted) at the stomp bit position, “1” is output and the status register (S
TRI) Join 31. This allows the layered message interrupt to be detected.

In the home bus HB system, short message interrupts can be generated from devices connected to the home bus. A short telegram interrupt can be performed in a home bus system by having an interrupting device in the stop bit SP generate an "O" output, ie, a pulse. The layered message interrupt detection circuit 22 detects this short message interruption. That is, when the cover layer message interrupt detection circuit 22 detects an interrupt, the detection signal is added, the state counter 19 is reset, and the state counter 19 is reset to 0 (state 3).
0). Also, at this time, an interrupt detection signal is output to the transmission control section 33 to stop subsequent transmission control. At the same time, the layered message interrupt detection signal is also added to the status register (STRI) 31, and the layered message interrupt flag R3MI of bit 6 is turned on ``1''.

When the data period (or data reception if it is reception) ends, the process moves to state S9. State 9 is a check code period, and after receiving the check code, state S10 is entered, which is a dummy code period. Incidentally, when broadcasting is performed, the state is O, that is, the state counter value is set to 0. After the dummy code is an ACK/NAK period, and during this period ACK
/NAK signal is sent. After that, the state becomes SO.

On the other hand, when there is a transmission request in state p52, the state is 82' (the value of the state counter does not change) as described above.
After that, the state 83' (priority code period) is entered.

If a transmission request is issued to multiple devices at the same time and they send data, etc. at the same time, a conflict will occur. The home bus HH is configured to set priorities for each device when this conflict occurs, and when a conflict occurs, priority is given to the device with the highest priority among the competing devices. Priority is determined by priority code. The priority consists of a total of 8 bits of Do-D7, and “oooooooo” is the highest, and “
11111111" is the lowest. If high priority and low priority codes simultaneously send priority codes within the priority code period, each pinto will be output on the bus at the same time. Each bit will be output at the same time, but as mentioned above In the home bus, a pulse is output at "0" and no pulse is output at 11", so the device that outputs 10" will forcibly set the home bus bit to "0". −
On the other hand, since a device with a low priority level is transmitting "1" instead of "0", the data is different from the data on the path line. The competition detection circuit 21 detects this change in data. Serial output S of TX shift register 25
O and the received signal R of the home bus driver/receiver 13
If XD is contention negative, it is added to the detection circuit 21. If the contention is negative, the detection circuit 21 detects these two signals, that is, the received signal RXD.
and serial output SO, SO and received signal RXD
If they match, it means that the priority is high or there is no competition, and this does not mean that the competition is lost. However, if the priority code of another device is high, the code with the higher priority code is added as the received signal RXD. detects that there is a discrepancy, and applies a mismatch signal to the transmission control unit 33. As a result, the transmission control unit 3
3 stops sending out the priority code currently being sent. At the same time, it notifies the status register (STRI, 31) that the competition has been lost.In other words, the status register (STRI)
) 31 bit 5 contention negative turns on flag CD (“1”)
). FIG. 18 is an explanatory diagram of competition. Other equipment (
If a high-level priority code is sent from the IFU, and a low-level priority code is output from the device (IFU), the device loses the competition because it does not output "O" in the DO code. Due to this competition loss, the INTR flag of this device is further turned on at the next start focus. Furthermore, the transmission flag is turned off at the next start bit after the contention point. Further, the above-mentioned CD flag is turned on at the next start bit. For example, if an interrupt is released, an interrupt IRQ is applied to the microprocessor 11.

The flag information of the register CCR32 is added to the interrupt control unit 36, and the flag information of the status register (STR1) 31 is also added to the control unit 36.The interrupt control unit 36 sends this information to the interrupt signal iRQ and the microprocessor 1.
1 via the buffer circuit 15.

The explanation will be returned to FIG. 17. In state S3', if a competition loss occurs, the next transmission cannot be performed, so the competition is lost and the state shifts to state S3 in the above-mentioned reception state, and thereafter becomes the reception state.

FIG. 29 is a logic circuit diagram of the competition negative detection circuit 21.

During transmission, when the value of the status counter 19 is 3 or 4, a signal of H (11'') is applied to the AND circuit.Reception data RXD and reception data SO are also applied to the EOR circuit, and the output is sent to the AND circuit. During transmission, when the status counter 19 is 3 or 4 and the received data and the transmitted data are different, a conflict negative signal is added from the AND circuit to the status register (STRI) 31 and stored.

Conflicts are detected by such operations.

On the other hand, if no competitive loss has occurred, state 34'
Then, the self-address period begins. During the self-address period, the self-address to be transmitted, for example, when the circuit shown in FIG. 3 transmits, the self-address of the present device is transmitted. Also in the self-address period, a competition loss may occur as described above.

For example, if a plurality of devices with the same level of priority code exist on one home bus, each device will not lose the competition, although they will compete during the priority code period. Therefore, conflict must be detected again during the self-address period. 1 (Since there are no two identical addresses on the II's home bus, conflicts can be completely detected in this self-address detection. The detection of this conflict is also the same as the operation described above, and the conflict negative This is done by the detection circuit 21. When a competition loss occurs in this state 34', the above-mentioned reception state S4 is entered.

On the other hand, when no competition loss is detected, the next state is S5', ie, the other party address period, in which the other party's address to be transferred is sent. When the transmission of the destination address is completed, a control code and a message length code are sequentially sent in a control code period (state 86') and a message length code period (state 87'), respectively. After that, data or information is sent out.

This data transmission occurs during the data period (state 88').

During data transmission (state, 1938') and data reception (state f)
! This is the same as S8), and a short message interrupt may occur from another device. When this short message interruption occurs, it is detected at the layered message interruption detection time v1r22, and the state counter 19 is set to O, similarly to the reception state.

That is, at this time, the state is SO. When the data ends in the data period (state 88'), the next check code period (state 9') begins and a check code is sent out. Then, after a dummy code period (state 310'),
During the ACK/NAK period, no ACK or N is received from the receiving device.
It receives the AK signal and enters the state SO.

All changes in the count value of the state counter 19 mentioned above are made by the data edge signal from the edge detection circuit 17.

Note that there may be no change if the conditions are not satisfied.

For example, in the data period (state 38.S8'), it does not change until all data is completed or a short message interrupt occurs, and the period of state 1 is detected by the timer 38, and a time-over signal is sent to the state counter 19. When added, the status counter 19 changes. The timer 38 is added to the transmission control unit 33, and the transmission control unit 33
Transmission control is started by a time-over signal input from 8.

The packet status register 39 includes the parallel output of the RXX shift register 2, and is a circuit that detects the status of packets being sent and received. The state is added to the state counter 19 via the pause counter 18, and the state counter 19 changes accordingly. Figure 12~
Figure 15 shows the individual time, broadcast time, synchronization recovery period, and
FIG. 4 is an explanatory diagram of the operation of the status counter at the time of an ACK/NAK error. At any time, the sequential status counter 19 is 0.
1.2.3.4.5.6.7.8°9. In the figures 3 to 9, the bus data is the priority code,
Self address, partner address, control code, message length code,
Data (information) and check codes change sequentially.

When the synchronization recovery period is separate, there is a dummy code period and an ACK/NAK period in 10.11. Note that the synchronization recovery period is a period during which the apparatus of this embodiment performs synchronization recovery. During this time, the bus data changes sequentially, and for example, this bus data is data transfer between other devices. Note that if there is no transfer between other devices (no data is transferred and the bus data does not change), on the other hand, when broadcasting, the value is "θ" after the check code period. teeth,
This is because it is not necessary to send an ACK/NAK signal,
At this time, there is no dummy code period and ACK/NAK period, and the period after 9 is 0. Further, if an error occurs during the ACK/NAK signal, the state counter 19 does not change from the state of 10, but directly changes from 10 to O.

The parallel output of the RX shift register 23 is added to the message length counter (MLC) 50, which takes in the parallel output of the RX shift register 23 when the status register 19 is 7 (state S7) in the receiving state, and converts the parallel output of the RX shift register 23 to 1 in the device S8.
For example, by reading the contents of the message length counter (MLC) 50 from the microprocessor 11, which is a counter that decrements each time data or information is received, it can be determined how many more pieces of received data should be received. Figure 28 shows the bus data and message length counter (
5 is an explanatory diagram of the operation of MLC) 50. FIG. When n is received in the message length data, n is loaded into the message length counter (MLC) 50, and thereafter in state S9, it is decremented by 1 each time data is received sequentially, and when this code is received, O is loaded. Become.

In the transmission operation, the microprocessor 11 writes data to the transmission data register (TXDR), thereby lowering TXRDY and completing preparation for transmission ((2) in FIG. 19). At this time, if the SMI flag is set to OFF, long messages can be sent sequentially by interrupt. Then, when transmission becomes possible, transmission starts automatically (Fig. 19 ■). After that, the TXRDY flag and the INTR flag become 1'', an interrupt is generated, and the next transmission is sent to the microprocessor 11. Request data (own address) (Fig. 19 ■). After that, write the transmission data in the same way. When the data being transmitted becomes a check code, it stops transmitting and receiving the next character (dummy code) (Fig. 19). (Figure 19 ■) ACK/NAK is transmitted and received. Also, the transmission of the transmission data to the microprocessor 11 ends when the last character of the data section is transmitted (
Figure 19 ■). Also, when data is written to TXDR after this, the first character (priority code) of the next packet
becomes.

Since the receiving operation is performed at the same time as the transmitting operation, an input interrupt may occur after the "priority code" is transmitted (FIG. 19O).

On the other hand, as shown in FIG. 20, the transmission operation in synchronous communication is the same as in FIG. 19, except that the individual transmission does not receive ACK/NAK.

The reception operation starts when data is received. After receiving one character, the RXRDY flag and the lNTR flag become "1" and generate an interrupt IRQ to prompt the microprocessor 11 to input data.
1, the first character (priority code) is received by the microprocessor only when MDR1=4 (Figure 21 -). And the last data is MDR
When = 0, Uke will take (Figure 21 ■). Also,
ACK/NAK transmission uses AKR, but for reception, no special register is prepared and RXD is used like other data.
Performed by R. In addition, as shown in Fig. 22, the judgment of broadcast and long messages is made by the "priority code", and the reception operation in broadcast communication is different from individual reception as shown in Fig. 23, and the transmission of ACK/NAK is The rest is the same as in FIG. 21 except that it disappears.

For the 80/NAK transmission operation, a dedicated register is provided for the ACK/NAK output as described above, and the ACK/NAK transmission register (AKR) is normally input after the check code is input.
This is done by setting data to (Fig. 21 -).Also, if data is being sent/received, it will be sent at any time. (However, in the case of broadcast or short message interrupts, data will not be sent even if it has been sent in advance.

Reset flags (RE, S
) goes from 'O' to '1' (when reset is released), and when a data reception error or write lost data error occurs, the synchronization recovery period begins.

At this time, the transmit/receive interrupt mask flag becomes “O”,
No interrupt is generated to the microprocessor 11. These flags are set to “1” when the synchronization recovery period ends.
” and an interrupt will be generated. Furthermore, transmission will not occur during the synchronization recovery period.

Also, during the synchronization recovery period, the status counter (MDR) is 0''.
- Operates as “2” (status counter (MDR) is “0”)
If data comes in at this time, the data will be received, but it will not be recognized as a packet and will be treated as a data reception error (RDE). If data comes in when the status counter (MDR) is "2", the data is received and synchronization recovery is performed. ) and (11 synchronization recovery period is normal packet (
No parity error (PE) has occurred. ) is received or (2) there is no data on the bus for 1 period.
It ends with 01113+22 bits. However, if a parity error (PE) occurs in (1), the packet is treated as unsynchronized, and the synchronization recovery period continues under either of the two conditions (1) or (2). This period continues until this is achieved. In an embodiment of the invention, a data reception error (RDE).

Write lost data error (WLD), Read lost data error (RLD), Framing error (
FE), parity error (PE), and ACK/NAK error (AKE) are detected. When a framing error (FE) or parity error (PE) occurs, the flag is set to “
1'' to notify the microprocessor 11 of the error through an interrupt.

Then, the reception operation continues as it is.

A write lost data error (WLD) and a read lost data error (RLD) are checked at the time of transmitting and receiving the next data, and the flag is set to "1" to notify the microprocessor 11 of the error by an interrupt. In the case of a read lost data error (RLD), the reception operation continues as is, but in the case of a write lost data error (WLD), the transmission operation is stopped and the synchronization recovery period described above begins.

When a data reception error (RDE) occurs, the flag is set to “1” and an interrupt is generated while the status counter (MDR)
is set to 10" and the synchronization recovery flag (DRE) is set to "1" to enter the synchronization recovery period.

When an ACK/NAK error occurs, the flag is set to "1" and an interrupt is generated. When this error occurs, the status counter (MDR) changes from "10" to "10" to "0'". That is, when ACK/NAK cannot be detected, the period of MDR=10 becomes n bits.

In the case of any error flag, read the status register (STR2) 29 or check the status counter (MDR).
When the status counter (
MDR) becomes "O" when it becomes "2".

On the other hand, causes of interruption to the microprocessor 11 include input of transmission data, output of reception data, short message interruption, loss of competition, and error.

Detection of interrupt factors is performed using the TXRDY flag and RXRDY flag.
flag, layered message interrupt flag, contention negative flag, error flag, or status register (STR2>2
It can be determined based on 9. Furthermore, an interrupt can be reset by reading the interrupt flag for any factor.

In the embodiment of the present invention shown in FIG. 3, the edge detection circuit 17 is a circuit that detects the edge of data, that is, the start bit. This circuit defines the start bit detection range and its width, eliminates noise, and indicates a data reception error in response to an incorrect message. FIG. 24 is a circuit diagram of the start bit detection circuit, that is, the data edge detection circuit 17. Dividing this circuit into functions, it determines the position detection range of the start bit and the width detection range of the start bit, and determines whether the start bit is within the range.

The received signal RXD is applied to a fall detection circuit 40 and a rise detection circuit 41. Falling detection circuit 40
The output of the rising edge detection circuit 41 is also applied to a pulse width detection counter 43.
3 starts a counting operation from when the received signal falls until it rises, and counts the number of mask clocks. Then, the count number during that time is added to the range/pulse width comparison circuit 42. FIG. 25 is an explanatory diagram of the start focus width detection range. Start focus is 5 after falling
The range is defined as 2 μsec + 39 μsec s -11, 2 μsec, and the range/pulse width comparison circuit 42 uses the bit within this range as the start bit. Then, it is output as a start bit valid, ie, data edge detection signal. The start bit valid signal is also added to the start bit detection range counter 44, and after the start bit becomes valid, it starts counting operation, and when the count value is in a specific range, a signal indicating the range is sent to the range/pulse. It is added to the width comparison circuit 42. The detection output of the falling detection circuit 4o is applied to the range/pulse width comparison circuit 42, and the range/pulse width comparison circuit 42 outputs the detection signal from the falling detection circuit 40 from the start bit detection range counter 44. It is detected whether the start bit is within the range indicated by the effective range instruction signal. If an instruction is given, the pulse when a falling edge is detected from the falling edge detection circuit 40 is added as H, and if a signal that becomes H at the time representing within the range is added from the start bit detection range counter 44, the range/pulse is added. The width comparison circuit 42 calculates the AND logic of the 2fli signal, and the result is "H".
Further, when the pulse width is within a specified value, a start bit valid signal is output. The above-mentioned "within the start bit effective range" defines the range of the position where the start bit falls, and as shown in Figure 26, the falling edge of the start bit is within ±13 from the position where it should be input.
It is valid for a period of μsec. Also, the start bit is not detected for all data (as shown in Figure 27, X1
It is in the range of ~X9.

The start bit detection circuit described above prevents noise and turns on the data reception error flag for incorrect messages, thereby increasing the validity of the data.

〔Effect of the invention〕

As described above, the present invention determines the width and position of the start bit of serial data and determines whether it is a valid start bit or an invalid start bit.
According to the present invention, it is possible to detect data transfer due to noise or malfunction, and it is possible to obtain a bus control circuit that performs reliable transfer.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the present invention, Figure 2 is a system configuration diagram of the present invention, Figure 3 is a bus control circuit, Figure 4 is a data configuration diagram, Figure 5 is TXH, TXL data, Figure 6 is Transmission circuit diagram, Figure 7 is a configuration diagram of the register (TXDR/AKR), Figure 8 is a bit configuration diagram of register OCR (mode 1), Figure 9 is a bit configuration diagram of register OCR (mode 2), Figure 10 is a bit configuration diagram of status register 5TR1, Figure 11 is a bit configuration diagram of status register 5TR2, Figure 12 is a diagram explaining the operation of the status counter at individual time, and Figure 13 is a diagram of the bit configuration of status register 5TR2.
Figure 14 is an explanatory diagram of the operation of the status counter during broadcasting, Figure 14 is an explanatory diagram of the operation of the status counter during the synchronization recovery period, Figure 15 is an illustration of the operation of the status counter at the time of an ACK/NAK error, and Figure 16 is an illustration of the operation of the status counter during the ACK/NAK error. State counter value and its state diagram, Fig. 17 is a state transition diagram, Fig. 18 is an explanatory diagram of conflict, Fig. 19 is a data transmission operation chart, Fig. 20 is data transmission operation (broadcast), and Fig. 21 is Data reception operation, Figure 22 is a long message and broadcast condition diagram, Figure 23 is data reception operation (broadcast), Figure 24 is a start focus detection circuit diagram, and Figure 25 is an explanation of the start bit width detection range. Figure 26 is an explanatory diagram of the start bit position detection range, Figure 27 is an explanatory diagram of the start bit position detection range, Figure 28 is an explanatory diagram of the operation of the message length counter, and Figure 29 is a logic circuit for losing competition. Figure 30 is a logic circuit diagram of layered message interrupt. 1...Pulse width detection circuit, 2...Pulse position detection circuit, 3...Pulse position/width comparison circuit. Patent Applicant Fujitsu Limited Child Area Diagram Figure 4 TXH, TXL De'-y Figure 5 8 Day ■ Imiya Circuit Diagram Figure 6 Register (TXDR/AKRI jAs, w Figure 7 Register CCR (7-G 1) No. 1. G Structure A Fig. 8 Register CCR (7-G 2) and' = t Todoroki A Fig. 9 (In 0 (G state) Transition diagram Figure 17 Conflict! 4-kegin 7ya, ↓ lNTR flag
---------- Figure 18 of Kabuto Menkura no Ieshi Yumi (0 time 1S each, 9 long telegrams 2 broadcasts and series) Long telegrams, persistent clauses Figure 22 Exemption 1 Figure 29 ND Figure 30 Logic circuit for lighted message interrupt

Claims (1)

[Claims] In a data bus system that transmits serial data via a data bus, the serial data is added to a pulse width detection circuit (1) that detects the pulse width of a start bit of the serial data.
), a pulse position detection circuit (to which the serial data is added and which detects the time position of the start bit of the serial data);
2), the detection results of the pulse width detection circuit (1) and the pulse position detection circuit (2) are added, and the pulse width detection result is compared to see if it is a specific pulse width, and the position of the start bit is determined. 1. A bus control circuit comprising: a pulse position/width comparison circuit (3) which compares whether a detection result exists within a specific time and outputs a valid start bit signal when the condition is satisfied.