JPH0212360A - Multi-processor device - Google Patents

Abstract

PURPOSE:To shorten the waiting time of an arithmetic processor and to attain a high-speed processing action for a multi-processor device by setting the priority just with the change of a ROM in case a certain arithmetic processor uses frequently a shared memory. CONSTITUTION:When an arithmetic processor 1a is used as a main device, the frequent chances are secured to the processor 1a for shared memory accesses to ensure the higher priority of the processor 1a. At the same time, the priority is changed with the change of the data stored in a ROM 15 and the shared memory permission signals Qa-Qc are applied to the processors having the order of applications decided to a shared memory 4 in accordance with the processing order. In such a way, the ROM values changed in response to a system and the order of transmission is changed for signals Qa-Qc. Thus it is possible to minimize the waiting time of the arithmetic processors that desire the application of the memory 4 and to realize a high-speed processing action for a multi-processor device.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a multiprocessor device that shares a single memory among a plurality of arithmetic processing units.

[Conventional technology]

FIG. 4 is a configuration diagram showing a conventional multiprocessor device disclosed in, for example, Japanese Unexamined Patent Publication No. 52-103935.
In the figure, 1a to 1c are arithmetic processing units, and 2a to 2c and 3a to 3c are read-only memories and continuous write memories corresponding to the arithmetic processing units 1a''-1c, respectively.Furthermore, 4 is the arithmetic processing unit. A shared memory that can be shared by 1a to 1c, and 5a to 5c are the arithmetic processing units 1, respectively.
An admission control circuit receives a shared memory request signal outputted when a to lc wish to use the shared memory 4, and 6 is a scanning circuit that outputs a cyclic shared memory permission signal to each of the admission control circuits 5a to 5c. , this scanning circuit 6 is composed of a ring counter. Further, lla to llc are provided corresponding to each of the arithmetic processing units 1a to IC, and are used to send predetermined data and data signal registers 7a to 7c when the 8fA arithmetic processing units 1a to 1c want to use the shared memory 4. Data bus, 10a~
Reference numeral 10c denotes an address bus for sending an address signal for specifying which block of the shared memory 4 the data sent via the data buses 11a to 11c is to be input to the corresponding address signal registers 8a to 8C. In the figure, arrows indicate signal lines, which are treated here as signal flows. RaxRc is a shared memory request signal output from each arithmetic processing device 1a to IC, and Q a -Q c is a shared memory permission signal sent from the scanning circuit 6 to each arithmetic processing device 1a to 1c. Next, the operation will be explained. Hereinafter, shared memory access by the plurality of arithmetic processing units tla to 1c will be explained in three cases. First, a case will be described in which none of the arithmetic processing units 1a to 1c accesses the shared memory 4. in this case,
The scanning circuit 6 sends high-speed cyclic shared memory permission signals Qa-Qc to the respective admission control circuits 5a to 5C. During this time, each arithmetic processing device 1axlc is connected to read-only memories 2a to 2c and write/read memories 3a to 3 provided corresponding to the arithmetic processing devices 18 to 1c, respectively.
address buses 10a to 10c and data bus ll to
Data is transferred via a to llc and predetermined arithmetic processing is executed. Therefore, the processing units 1a to 1c do not need to use the shared memory 4, and do not output the shared memory permission signals Qa to Qc to the admission control circuits 5a to 5C. Meanwhile, the scanning circuit 6 only continues to generate the cyclic shared memory enable signals Q a -Q c described above. Next, a case where only one arithmetic processing unit, for example 1a, accesses the shared memory 4 will be described. Here, suppose that a write request occurs to the shared memory 4 while the arithmetic processing unit 1 is executing arithmetic processing using exclusively available memories (read-only memory 2a, continuous write memory 3a). At this time, the arithmetic processing unit 1a outputs the shared memory request signal Ra to the admission control circuit 5a, and also outputs the shared memory request signal Ra to the data bus l.
The data is sent to the data signal register 7a via the data signal register 7a. At this time, an address signal indicating which block of the shared memory 4 the data is to be input to is simultaneously sent to the address signal register 8a via the address bus loa. The data signal and address signal sent from the arithmetic processing unit 1a in this way are held in the data signal register 7a and address signal register 8a, respectively, and the shared memory permission signal Qa is sent from the scanning circuit 6 to the reception control circuit 5a. Wait for input. When the shared memory permission signal Qa is input from the scanning circuit 6 to the admission control circuit 5a, the admission control circuit 5a receives the cyclic shared memory permission signal Qa from the scanning circuit 6.
This state is held in the reception control circuit 5a. Further, the reception control circuit 5a is connected to the arithmetic processing unit 1a.
On the condition that the shared memory request signal Ra from 1 and the shared memory permission signal Qa from the scanning circuit 6 are input, the shared memory permission signal Qa is sent to the data signal register 7a and the address signal register 8a. The data signal register 7a and address signal register 8a that have received the shared memory permission signal Qa input the data signal and address signal held as described above to the shared memory 4 to perform a write operation. Thereafter, when the write operation is completed, the reception control circuit 5a sends a write completion signal to the arithmetic processing unit 1a and the scanning circuit 6. In response to this operation, the scanning circuit 6 uses this write completion signal to restart the cyclic operation of the shared memory enable signals Qa-Qc, which had been blocked by the admission control circuit 5a. The scanning circuit 6 is connected to each arithmetic processing unit 1a to
It waits for shared memory request signals Ra-Rc to be sent again from 1c. Next, a case will be described in which two arithmetic processing units, for example, 1b and 10 access the shared memory 4 simultaneously. In this case, both the arithmetic processing units 1b and lc send shared memory permission signals Qb and Qc to the reception control circuits 5b and 5C, as in the case where the arithmetic processing unit 1a described above performs a write operation to the shared memory. At the same time, data signals and address signals are input to data signal registers 7b and 7C and address signal registers 8b and 8C via data buses llb and llc and address buses 10b and 10c, respectively. Of each reception control circuit 5b and 5C, the scanning circuit 6
Shared memory permission signal Qb issued from. Either one of the admission control circuits to which Qc is input first, for example 5b, holds the shared memory permission signal and prevents the cyclic operation in the scanning circuit 6. Subsequently, the same operation as when one arithmetic processing unit 1a accesses the shared memory 4 described above is performed, and when the shared memory 4 completes the write operation, the reception control circuit 5b controls the arithmetic processing unit 1b and the scanning circuit 6. Sends a write completion signal to Therefore, the scanning circuit 6 resumes its cyclic operation and inputs the shared memory permission signal Qc to the other admission control circuit 5c. Therefore, the admission control circuit 5c
A data signal and an address signal are sent to the device to perform a write operation. Thereafter, when this arithmetic processing device 1c completes the write operation, the scanning circuit 6 performs a cyclic operation again, and the reception control circuits 5a to 5C control each arithmetic processing device 1a to 1.
Wait for the shared memory request signal to be output from c.

[Problem to be solved by the invention]

Since the conventional multiprocessor device is configured as described above, each of the arithmetic processing units 1a to IC is sequentially and sequentially given shared memory permission signals Qa to Qc by the scanning circuit 6 which operates cyclically. However, even when it is desired to allocate the shared memory 4 with priority to a certain arithmetic processing unit it, or when the order of shared memory use 1 of the arithmetic processing units is determined, the scanning circuit 6 performs arithmetic processing that does not use the shared memory 4. Since the shared memory permission signals Q a -Q c are also sent to the devices, there is a problem that the arithmetic processing device that originally wants to use the shared memory 4 is forced to wait for that amount of time. This invention was made to solve the above-mentioned problems, and even when the frequency of use of the shared memory of arithmetic processing units differs, the waiting time of frequently used arithmetic processing units can be shortened, and high-speed processing can be achieved. It is an object of the present invention to provide a multiprocessor device in which the order in which shared memory permission signals are sent can be easily changed depending on the system.

[Means to solve the problem]

A variable scanning circuit of a multiprocessor device according to the present invention includes a read-only memory (ROM) that stores arithmetic processing unit numbers in the order in which shared memory permission signals are sent, and corresponds the shared memory permission signals to addresses on the read-only memory. A selection circuit is provided to send the data to an arithmetic processing unit.

[Effect]

In the multiprocessor device according to the present invention, a cyclic signal is sent from a ring counter in a variable scanning circuit to a control circuit, and the control circuit that receives the signal reads data on a read-only memory (ROM) corresponding to the input signal. The read data, ie, the arithmetic processing unit number, is output to the selection circuit. Further, the selection circuit sends a shared memory permission signal to the admission control circuit corresponding to the input data.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, the same parts as in FIG. 4 are designated by the same reference numerals. In FIG. 1, reference numeral 12 is a variable scanning circuit. Further, FIG. 2 is a diagram showing an embodiment of the variable scanning circuit 12 according to the present invention, and the ring counter 13 has the same component as the scanning circuit 6. In FIG. 14 inputs the signal from the ring counter 13,
A control circuit that controls access to the memory; 15 is a read-only memory (ROM) that stores the numbers of the processing units 1a to 1c; 16 receives data from the control circuit 14; Shared memory permission signal Qa to reception control circuits 5a to 5c of each arithmetic processing unit 1a to 1c
-Q This is a selection circuit that sends out c. Next, the operation will be explained. First, in FIG. 1, the operation is the same as the conventional one except for the variable scanning circuit 12. Here, as an example, a case will be considered in which priorities are assigned based on the usage status of the shared memory of each arithmetic processing unit. Now, it is assumed that the arithmetic processing unit 1a is used as the main unit and the shared memory 4 is accessed many times. As shown in FIG. 3, on the read-only memory 15, arithmetic processing unit numbers 0, 0,
1.2 is stored. Here, arithmetic processing unit number 0,
1.2 correspond to the arithmetic processing units 1a to IC, respectively. Next, the main functions of the circuits within the variable scanning circuit 12 will be explained. In FIG. 3, it is assumed that the ring counter 13 repeatedly sends out the output signals of SO to S3 in order. When the control circuit 14 receives the output signals SO to S4,
Data (processing unit number) at addresses aO to a3 on the corresponding read-only memory 15 (ROM) is read, and the data is sent to the selection circuit 16. When the arithmetic processing unit number 0.01.2 is received from the control circuit 14, the selection circuit 1
6 is a shared memory permission signal Q a to the corresponding arithmetic processing unit.
-Q Outputs a signal to reception control circuits 5a to 5C to send c. Specifically, the procedure for sending the shared memory permission signals Q a -Q c based on the data on the ROM will be explained next. First, the ring counter 13 sends the signal SO to the control circuit 14.
Enter. When the control circuit 14 receives the signal SO, it reads the data at the address aO on the read-only memory 15 (ROM), here the number "1" of the arithmetic processing unit 1a. Next, the data "1°" is input to the selection circuit 16, and the selection circuit 16 that has received the data "1°"
A shared memory permission signal Qa is sent to the admission control circuit 5a of a. Similarly, the ring counter 13 is sequentially set to SL, S2, S3.
．． When the control circuit 14 sends the signal So, 31, the control circuit 14 correspondingly sends data 0.1, 2, 0.0... to the selection circuit 16, which selects the arithmetic processing unit 1a. ,
Shared memory permission signals are sent to the corresponding admission control circuits in the order of lb, lc, la, and la. In this way, the arithmetic processing unit 1a is given many opportunities to access the shared memory, and the priority can be increased.Also, by changing the data on the read-only memory 15 (ROM), the priority can be changed. Or, if the usage order of the shared memory 4 is fixed, the shared memory permission signals Q a -Q c can be given according to the processing order. In this way, the ROM values can be changed according to the system. However, by changing the order in which the shared memory permission signals Qa-Qc are sent, the waiting time of the arithmetic processing unit that wants to use the shared memory 4 is reduced to the necessary minimum.In addition, in the above embodiment, the shared memory request signal Ra ~An example was shown in which a read-only memory (ROM) was provided as a part for storing the order of sending Rc, but if random access is acceptable, processing can be faster if the ring counter 13 is used directly. Therefore, by providing a switching device for performing switching between the ring counter 13 and the control circuit 14, the ring counter 13 and the reception control circuits 5a to 5c, the reception control circuits 5a to 5c
By connecting the ring counter 13 and disconnecting the control circuit 14 side, only the ring counter 13 can be used.

【Effect of the invention】

As described above, according to the present invention, a read-only memory (ROM) is provided in the variable scanning circuit, and the arithmetic processing unit number written in the read-only memory is referred to, and the arithmetic processing unit corresponding to that number is In addition, the configuration is configured to send a shared memory permission signal, so when a certain processing unit frequently uses shared memory, it is possible to prioritize the processing by simply changing the read-only memory. This has the effect of shortening the waiting time of the device and enabling high-speed processing operations.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a multiprocessor system according to an embodiment of the present invention, FIG. 2 is a block diagram showing a variable scanning circuit according to an embodiment of the present invention, and FIG. 3 is a block diagram showing a variable scanning circuit according to an embodiment of the present invention. A block diagram showing the operation of the embodiment, and FIG. 4 is a configuration diagram showing a conventional multiprocessor system. 1a to 1c are arithmetic processing units, 4 is a shared memory, 5a to 5
c is a reception control circuit, 12 is a variable scanning circuit, 13 is a ring counter, 14 is a control circuit, and 15 is a read-only memory (
ROM), 16 is a selection circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. 1Q~Ic' operation

Claims (1)

[Claims] A processor that executes various types of arithmetic processing, has a shared memory that can be shared by each of the arithmetic processors, is provided corresponding to each of the arithmetic processors, and wants the corresponding arithmetic processor to use the shared memory. and a scanning circuit that outputs a shared memory permission signal to the admission control circuit, and the shared memory request signal and the shared memory permission signal are input to the admission control circuit. In a multiprocessor device in which an arithmetic processing unit corresponding to the condition can use the shared memory, a variable scanning circuit for making a shared memory permission signal outputted from the scanning circuit variable, and a ring as a configuration of the variable scanning circuit. a control circuit that receives a cyclic signal output from the counter; a read-only memory that stores numbers corresponding to each processing unit in the order in which the shared memory is accessed; and a read-only memory that reads the signal from the ring counter. a control circuit that converts the data into the above address, reads the data at the address, and outputs the data; and a control circuit that receives the data from the control circuit and outputs a shared memory access permission signal to an arithmetic processing unit corresponding to the data. A multiprocessor device comprising a selection circuit.