JPH02123116U - - Google Patents
Info
- Publication number
- JPH02123116U JPH02123116U JP3155889U JP3155889U JPH02123116U JP H02123116 U JPH02123116 U JP H02123116U JP 3155889 U JP3155889 U JP 3155889U JP 3155889 U JP3155889 U JP 3155889U JP H02123116 U JPH02123116 U JP H02123116U
- Authority
- JP
- Japan
- Prior art keywords
- switch
- power
- mute
- circuit
- state
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Control Of Amplification And Gain Control (AREA)
Description
第１図は本考案の一実施例を示すブロツク図、
第２図はその一実施例中の制御回路の回路図、第
３図は各部の電圧波形図、第４図は各トランジス
タのオン／オフ状態を示す図、第５図は第１図に
示す実施例の回路図、第６図及び第８図は従来例
を示すブロツク図、第７図及び第９図は従来例の
各部の電圧波形図である。
１…整流回路、２…制御回路、３…電源スイツ
チ、４…アンプ、５…間接電源スイツチ、６…電
源プラグ、Ｃ５…時定数回路を構成するコンデン
サ、Ｄ２…ダイオード、Ｑ１…電源スイツチ状態
検出用のＮＰＮトランジスタ、Ｑ２…間接電源ス
イツチ制御用のＮＰＮトランジスタ、Ｑ３…ミユ
ートトランジスタ制御用のＰＮＰトランジスタ、
Ｑ４…ミユートＮＰＮトランジスタ、Ｒ９…時定
数回路を構成する抵抗。
FIG. 1 is a block diagram showing an embodiment of the present invention.
Fig. 2 is a circuit diagram of the control circuit in one embodiment, Fig. 3 is a voltage waveform diagram of each part, Fig. 4 is a diagram showing the on/off state of each transistor, and Fig. 5 is shown in Fig. 1. The circuit diagram of the embodiment, FIGS. 6 and 8 are block diagrams showing the conventional example, and FIGS. 7 and 9 are voltage waveform diagrams of various parts of the conventional example. 1... Rectifier circuit, 2... Control circuit, 3... Power switch, 4... Amplifier, 5... Indirect power switch, 6... Power plug, C5... Capacitor forming time constant circuit, D2... Diode, Q1... Power switch state detection Q2... NPN transistor for indirect power switch control, Q3... PNP transistor for controlling mute transistor,
Q4...Miute NPN transistor, R9...Resistor that constitutes the time constant circuit.
Claims (1)
源を供給する間接電源スイツチと、 前記増幅器の出力側に接続されたミユートスイ
ツチと、 前記電源スイツチに接続され前記電源スイツチ
のオン／オフ状態を検出する検出部と、前記間接
電源スイツチに接続され前記検出部からの検出信
号に応じて前記電源スイツチがオン状態のときの
み前記間接電源スイツチをオン状態とする第１の
制御部と、前記ミユートスイツチに接続され、前
記検出部からの検出信号に応じて前記電源スイツ
チがオフ状態のとき常に前記ミユートスイツチを
ミユート動作状態とすると共に、前記電源スイツ
チがオフ状態からオン状態となつた所定時間後に
前記ミユートスイツチのミユート動作状態を解除
する第２の制御部とを有し、前記電源回路から直
接電源が供給される制御回路とより構成したこと
を特徴とするミユーテイング回路。[Claims for Utility Model Registration] A power switch connected to a power circuit; an indirect power switch connected to the power circuit and supplying power to an amplifier when turned on; and a mute switch connected to the output side of the amplifier. a detection section connected to the power switch and detecting the on/off state of the power switch; and a detection section connected to the indirect power switch that detects the indirect power supply only when the power switch is in the on state according to a detection signal from the detection section. a first control section that turns on the switch; and a first control section that is connected to the mute switch, and that always puts the mute switch in the mute operation state when the power switch is off in response to a detection signal from the detection section; a second control section that releases the mute operation state of the mute switch after a predetermined period of time after the switch changes from the off state to the on state, and a control circuit that is directly supplied with power from the power supply circuit. Features a muting circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3155889U JPH02123116U (en) | 1989-03-20 | 1989-03-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3155889U JPH02123116U (en) | 1989-03-20 | 1989-03-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02123116U true JPH02123116U (en) | 1990-10-09 |
Family
ID=31257495
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3155889U Pending JPH02123116U (en) | 1989-03-20 | 1989-03-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02123116U (en) |
-
1989
- 1989-03-20 JP JP3155889U patent/JPH02123116U/ja active Pending