JPH021229B2 - - Google Patents
Info
- Publication number
- JPH021229B2 JPH021229B2 JP60076743A JP7674385A JPH021229B2 JP H021229 B2 JPH021229 B2 JP H021229B2 JP 60076743 A JP60076743 A JP 60076743A JP 7674385 A JP7674385 A JP 7674385A JP H021229 B2 JPH021229 B2 JP H021229B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- shutter
- sputtering
- thin film
- shutter mechanism
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 68
- 238000004544 sputter deposition Methods 0.000 claims description 56
- 239000010409 thin film Substances 0.000 description 33
- 239000010408 film Substances 0.000 description 32
- 238000010586 diagram Methods 0.000 description 22
- 238000000034 method Methods 0.000 description 21
- 150000004767 nitrides Chemical class 0.000 description 13
- 239000003990 capacitor Substances 0.000 description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 8
- 239000012212 insulator Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 239000006185 dispersion Substances 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 239000007789 gas Substances 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Landscapes
- Physical Vapour Deposition (AREA)
- Electrodes Of Semiconductors (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、高融点の酸化物薄膜等の形成を行う
スパツタリング装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a sputtering apparatus for forming a high melting point oxide thin film or the like.
スパツタリング法は、高密度集積回路などの半
導体装置作製において、SiやGaAsなどの半導体
基板上に絶縁物薄膜や金属薄膜を形成する上で重
要な役割を果している。特にSiO2がTa2O5などの
酸化物絶縁体薄膜やSi3N4などの窒化物絶縁体薄
膜は、半導体装置作製上、その重要性が高まつて
いるが、融点が1000℃以上と非常に高いために、
抵抗加熱方式や電子ビーム加熱方式を用いた真空
蒸着法で薄膜を形成することは困難である。これ
に対しスパツタリング法は、低真空中で放電をお
こすことにより雰囲気のガスをイオン化し、付着
させる薄膜の構成材料の焼結体であるターゲツト
に、上記イオン化したガス分子を電界で加速して
衝突させて、ターゲツトから構成原子をはじきと
ばし半導体素子を形成する基板上に堆積させるた
め、基板の温度を低く保つた状態で、高融点の酸
化物薄膜や窒化物薄膜を形成することが可能であ
る。
Sputtering plays an important role in forming insulator thin films and metal thin films on semiconductor substrates such as Si and GaAs in the production of semiconductor devices such as high-density integrated circuits. In particular, oxide insulator thin films such as SiO 2 Ta 2 O 5 and nitride insulator thin films such as Si 3 N 4 are becoming increasingly important in the fabrication of semiconductor devices, but they Because it is very high
It is difficult to form a thin film using a vacuum evaporation method using a resistance heating method or an electron beam heating method. On the other hand, in the sputtering method, gas in the atmosphere is ionized by generating an electric discharge in a low vacuum, and the ionized gas molecules are accelerated by an electric field and collide with the target, which is a sintered body of the constituent material of the thin film to be attached. This makes it possible to form high melting point oxide or nitride thin films while keeping the temperature of the substrate low, as the constituent atoms are repelled from the target and deposited on the substrate where the semiconductor device will be formed. .
従来から用いられているスパツタリング装置の
構成を第８図に示し、薄膜形成の手順の一例を示
せばつぎの通りである。真空槽１を10-6Torr以
下の真空に排気したのち、アルゴンなどの不活性
ガスを10-2Torrから10-3Torrの真空度に達する
まで満たす。SiO2、Ta2O5やSi3N4などの絶縁体
薄膜を形成する場合、上記SiO2、Ta2O5やSi3N4
の焼結体をターゲツト３として用い、形成する薄
膜の酸素欠陥や窒素欠陥を補償するため、雰囲気
ガス中に酸素や窒素を０〜50％の比率で混合す
る。その後、ターゲツト電極２と基板電極６との
間に電圧を印加し放電を発生させる。第８図にお
けるシヤツタ４はターゲツト３と基板電極６に設
置した基板５との中間に位置し、上記ターゲツト
３からはじき飛ばされた原子が基板５に到達する
量を制御する。 The configuration of a conventional sputtering apparatus is shown in FIG. 8, and an example of the procedure for forming a thin film is as follows. After evacuating the vacuum chamber 1 to a vacuum of 10 -6 Torr or less, it is filled with an inert gas such as argon until a vacuum level of 10 -2 Torr to 10 -3 Torr is reached. When forming an insulator thin film such as SiO 2 , Ta 2 O 5 or Si 3 N 4 , the above-mentioned SiO 2 , Ta 2 O 5 or Si 3 N 4
The sintered body is used as the target 3, and oxygen and nitrogen are mixed in the atmospheric gas at a ratio of 0 to 50% in order to compensate for oxygen defects and nitrogen defects in the thin film to be formed. Thereafter, a voltage is applied between the target electrode 2 and the substrate electrode 6 to generate a discharge. The shutter 4 in FIG. 8 is located between the target 3 and the substrate 5 placed on the substrate electrode 6, and controls the amount of atoms repelled from the target 3 that reach the substrate 5.
上記手順によつて薄膜を形成する場合は、まず
シヤツタ４を閉じた状態で放電を開始する。この
過程はプリスパツタリングと呼ばれるもので、タ
ーゲツト３の表面に吸着した水分などの不純物を
除去し、ターゲツト３の表面を清浄化するための
ものである。すなわち一定時間上記プリスパツタ
リングを行つたのち、シヤツタ４を開き、基板５
上への薄膜形成を行う。 When forming a thin film using the above procedure, discharge is first started with the shutter 4 closed. This process is called pre-sputtering and is intended to remove impurities such as moisture adsorbed onto the surface of the target 3 and to clean the surface of the target 3. That is, after performing the pre-sputtering for a certain period of time, the shutter 4 is opened and the substrate 5 is
Form a thin film on top.
従来用いられていたシヤツタ４は単にターゲツ
ト３から基板５への粒子の流れを遮る機能だけが
要求されていたため、ターゲツト３とほぼ同じ大
きさの金属製平面板を用い、真空槽１の外から前
後に移動させることによつて、シヤツタ４の開閉
を行つていた。上記のようなシヤツタ４には基板
５の下面だけが覆われているため、ターゲツト３
から基板５への粒子の飛来を遮ることは可能だ
が、プリスパツタリングの過程で上記基板５が雰
囲気ガス中に露出されるのを防ぐことができな
い。したがつて、上記シヤツタ４を閉じた状態で
も、酸化物薄膜形成時は酸素プラズマを含む雰囲
気に、また窒化物薄膜形成時は窒素プラズマを含
む雰囲気に、基板５の表面がさらされてイオン化
した高エネルギーの酸素や窒素が基板５の表面に
到達するため、上記基板５の表面の酸化や窒化が
進行する。このようにして形成された基板５の表
面の酸化膜や窒化膜は多数の欠陥を含んでいる。
第９図は酸素分圧５×10-6Torrの条件下におい
て、従来のシヤツタ機構を有するスパツタリング
装置を用いプリスパツタリングを行つた場合にお
ける、Si基板上の表面酸化膜の膜厚とプリスパツ
タリング時間との関係を示したものである。酸化
膜厚の初期値は、上記基板をスパツタリング装置
に装填する時点でSi基板表面に存在する自然酸化
膜の膜厚である。同図より、僅か30分のプリスパ
ツタリングで28Åにもおよぶ表面酸化膜が成長し
ていることが判る。このように従のシヤツタ機構
では、プリスパツタリング過程での表面酸化膜や
表面窒化膜の成長を防止できないことは明確であ
る。
The conventionally used shutter 4 was only required to have the function of blocking the flow of particles from the target 3 to the substrate 5. Therefore, a flat metal plate of approximately the same size as the target 3 was used, and a shutter 4 from outside the vacuum chamber 1 was required. The shutter 4 was opened and closed by moving it back and forth. Since only the bottom surface of the substrate 5 is covered by the shutter 4 as described above, the target 3
Although it is possible to prevent particles from flying to the substrate 5, it is not possible to prevent the substrate 5 from being exposed to atmospheric gas during the pre-sputtering process. Therefore, even when the shutter 4 is closed, the surface of the substrate 5 is exposed to an atmosphere containing oxygen plasma when forming an oxide thin film, and to an atmosphere containing nitrogen plasma when forming a nitride thin film, and is ionized. Since high-energy oxygen and nitrogen reach the surface of the substrate 5, oxidation and nitridation of the surface of the substrate 5 progresses. The oxide film or nitride film on the surface of the substrate 5 formed in this way contains many defects.
Figure 9 shows the thickness of the surface oxide film on the Si substrate and the pre-sputtering when pre-sputtering is performed using a conventional sputtering device with a shutter mechanism under the condition of an oxygen partial pressure of 5 × 10 -6 Torr. It shows the relationship with sputtering time. The initial value of the oxide film thickness is the thickness of the natural oxide film existing on the surface of the Si substrate at the time the substrate is loaded into the sputtering apparatus. The figure shows that a surface oxide film as thick as 28 Å was grown in just 30 minutes of pre-sputtering. As described above, it is clear that the conventional shutter mechanism cannot prevent the growth of a surface oxide film or a surface nitride film during the pre-sputtering process.
第１０図は従来のシヤツタ機構を有するスパツ
タリング装置を用いて、Si基板上に30分間のプリ
スパツタリングを行つたのち、形成したTa2O5薄
膜を絶縁体薄膜とするMIS型キヤパシタの断面構
造図を示したもので、集積回路に用いられるキヤ
パシタの多くは、第１０図に示したように、半導
体基板７上に絶縁体薄膜８を形成し、さらに金属
電極９および１０を順次形成した構造である。上
記MIS型キヤパシタの電流電圧特性を示した図が
第１１図である。５×105V／cmの電界印加時に
おける漏れ電流は1.7×10-2A／cm2であり、集積回
路等の半導体装置で要求される10-8〜10-9A／cm2
以下という要求基準に比較して極めて高い。また
上記値はTa2O5本来の漏れ電流値と比較しても極
めて高い。このように表面酸化膜上に形成した絶
縁体薄膜の特性が非常に低下し、また、プリスパ
ツタリング過程での表面窒化膜も同様に悪影響を
及ぼすため、その成長を抑制することが必要であ
る。 Figure 10 shows a cross section of an MIS type capacitor using a Ta 2 O 5 thin film formed as an insulator thin film after 30 minutes of pre-sputtering on a Si substrate using a conventional sputtering device with a shutter mechanism. This is a structural diagram showing the structure of most capacitors used in integrated circuits, as shown in FIG. It is a structure. FIG. 11 is a diagram showing the current-voltage characteristics of the MIS type capacitor. The leakage current when an electric field of 5 x 10 5 V/cm is applied is 1.7 x 10 -2 A/cm 2 , which is 10 -8 to 10 -9 A/cm 2 required for semiconductor devices such as integrated circuits.
This is extremely high compared to the required standards below. Furthermore, the above value is extremely high compared to the original leakage current value of Ta 2 O 5 . In this way, the properties of the insulating thin film formed on the surface oxide film are greatly degraded, and the surface nitride film formed during the pre-sputtering process has a similar negative effect, so it is necessary to suppress its growth. be.
一方、スパツタリングには、ターゲツト表面を
清浄化するために最低30分程度のプリスパツタリ
ングが必要である。したがつて従来のシヤツタ機
構を有するスパツタリング装置では、プリスパツ
タリングによつて、表面酸化膜や表面窒化膜によ
る悪影響を抑制することが不可能である。 On the other hand, sputtering requires at least 30 minutes of pre-sputtering to clean the target surface. Therefore, in a sputtering apparatus having a conventional shutter mechanism, it is impossible to suppress the adverse effects of a surface oxide film or a surface nitride film by pre-sputtering.
本発明は、上記の問題点を解決するために、ス
パツタリング装置におけるシヤツタ機構を改め、
上記シヤツタが閉じた際には、基板電極に設置し
た基板の表面を、該基板の側面も含めて包み込む
ように遮蔽できるシヤツタを設け、イオン化した
雰囲気粒子が基板表面に到達しないようにしたも
のである。
In order to solve the above problems, the present invention modifies the shutter mechanism in the sputtering device,
When the shutter is closed, a shutter is provided that can cover the surface of the substrate placed on the substrate electrode, including the sides of the substrate, to prevent ionized atmospheric particles from reaching the surface of the substrate. be.
スパツタリング装置における従来のシヤツタ機
構は、シヤツタの開閉状態にかかわらず基板表面
がプラズマを含む雰囲気中に露出しているのに対
し、本発明によるスパツタリング装置のシヤツタ
機構は、ターゲツトに対向して設けられた基板電
極または該基板電極に接近して真空槽の上部など
に取付けられた側壁と、該側壁の下部開放端を蔽
うように設けたシヤツタ部とからなり、上記シヤ
ツタが閉じた状態において、プラズマを含む雰囲
気から上記基板を隔離し、プリスパツタリングの
過程で基板表面に酸化膜または窒化膜が形成され
るのを防いだものである。
In the conventional shutter mechanism of a sputtering apparatus, the substrate surface is exposed to an atmosphere containing plasma regardless of whether the shutter is open or closed, whereas the shutter mechanism of the sputtering apparatus according to the present invention is provided facing the target. It consists of a substrate electrode or a side wall attached to the top of a vacuum chamber in close proximity to the substrate electrode, and a shutter section provided to cover the lower open end of the side wall. This method isolates the substrate from an atmosphere containing carbon dioxide and prevents the formation of an oxide film or nitride film on the surface of the substrate during the pre-sputtering process.
つぎに本発明の実施例を図面とともに説明す
る。第１図は本発明によるスパツタリング装置の
一実施例を示す構成図、第２図は上記スパツタリ
ング装置におけるシヤツタ機構を示す図で、ａは
下面図、ｂは正面図、第３図はシヤツタの開閉状
態を示す図で、ａは閉状態、ｂは開状態、第４図
はプリスパツタリングの過程におけるSi基板表面
の表面酸化膜の形成状態を、従来装置と本発明に
よる装置と比較した図、第５図はSi基板上に同一
条件で形成したTa2O5を絶縁体薄膜とするMIS型
キヤパシタの電流―電圧特性を従来装置と本発明
による装置と比較した図、第６図は作製したそれ
ぞれのMIS型キヤパシタの静電容量の周波数分散
を示す図、第７図は本発明の他の実施例を示す構
成図である。第１図において排気管を有する真空
槽１内でターゲツト電極２に設けたターゲツト３
に対向して基板電極６を設け、該基板電極６に設
置した基板５を包み込むようにして、シヤツタ機
構１１を直接上記基板電極６に取付けている。上
記シヤツタ機構１１は第２図ａおよびｂに示すよ
うに、基板電極６に取付けられ基板５の周囲を取
巻く側壁１２を有し、ターゲツト３に対向する下
方開放面は、第２図ａの下面図に示すように、開
閉自在に可動する複数のブレード１３を備えたシ
ヤツタ１１′を構成している。第３図は上記シヤ
ツタ１１′の開閉状態を示し、ａはシヤツタ１
１′が閉じた状態、ｂはシヤツタ１１′が開いた状
態を示している。上記シヤツタ１１′を構成する
各ブレード１３は、上記シヤツタ機構１１の側壁
１２に内蔵されたマグネツトモータにより可動
し、シヤツタ１１′が開いた状態では各ブレード
１３がシヤツタ機構１１の外側に開き、上記シヤ
ツタ機構１１の下面を開放する。またシヤツタ１
１′が閉じた状態では、各ブレード１３の一部が
互いに重なり合つて、第３図ａに示すようにシヤ
ツタ機構１１の下面を閉じるから、上記基板５は
シヤツタ機構１１の側壁１２および上記各ブレー
ド１３からなるシヤツタ１１′により、プラズマ
を含む雰囲気から包み込むように遮断され、プリ
スパツタリングの過程で上記基板５の表面に酸化
膜または窒化膜が形成れるのを防止する。
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a sputtering device according to the present invention, FIG. 2 is a diagram showing a shutter mechanism in the sputtering device, in which a is a bottom view, b is a front view, and FIG. 3 is a diagram showing opening and closing of the shutter. In the diagrams showing the states, a is a closed state, b is an open state, and FIG. 4 is a diagram comparing the state of formation of a surface oxide film on the surface of a Si substrate during the pre-sputtering process between a conventional device and a device according to the present invention. , Fig. 5 is a diagram comparing the current-voltage characteristics of a MIS type capacitor formed under the same conditions on a Si substrate using a Ta 2 O 5 insulating thin film as a conventional device and a device according to the present invention, and Fig. 6 is a comparison of the current-voltage characteristics of a conventional device and a device according to the present invention. FIG. 7 is a diagram showing frequency dispersion of capacitance of each MIS type capacitor, and FIG. 7 is a configuration diagram showing another embodiment of the present invention. In Fig. 1, a target 3 is provided on a target electrode 2 in a vacuum chamber 1 having an exhaust pipe.
A substrate electrode 6 is provided opposite to the substrate electrode 6, and the shutter mechanism 11 is directly attached to the substrate electrode 6 so as to wrap around the substrate 5 placed on the substrate electrode 6. As shown in FIGS. 2a and 2b, the shutter mechanism 11 has a side wall 12 attached to the substrate electrode 6 and surrounding the substrate 5, and the lower open surface facing the target 3 is the lower surface of FIG. 2a. As shown in the figure, a shutter 11' includes a plurality of blades 13 that can be freely opened and closed. FIG. 3 shows the opened and closed states of the shutter 11', and a indicates the shutter 1.
1' shows a closed state, and b shows a state where the shutter 11' is open. Each blade 13 constituting the shutter 11' is moved by a magnet motor built into the side wall 12 of the shutter mechanism 11, and when the shutter 11' is open, each blade 13 opens to the outside of the shutter mechanism 11. The lower surface of the shutter mechanism 11 is opened. Also, shutter 1
1' is closed, a portion of each blade 13 overlaps each other and closes the lower surface of the shutter mechanism 11 as shown in FIG. A shutter 11' consisting of a blade 13 shields the substrate 5 from an atmosphere containing plasma, thereby preventing the formation of an oxide film or a nitride film on the surface of the substrate 5 during the pre-sputtering process.
第４図は従来のスパツタリング装置と本実施例
とにおいて、プリスパツタリング過程でSi基板表
面に形成される表面酸化膜の膜厚を、時間の経過
にしたがい比較して示した図である。従来装置に
よる場合は曲線１４に示すように30分のプリスパ
ツタリングによつて、表面酸化膜が７Åから28Å
へと成長しているのに対し、本実施例によるとき
は曲線１５に示すように30分経過後も７Åと変化
なく、基板を真空槽１の基板電極６に装填した時
点で基板５の表面に存在した自然酸化膜以上の表
面酸化膜の成長は認められなかつた。 FIG. 4 is a diagram comparing the thickness of the surface oxide film formed on the surface of the Si substrate in the pre-sputtering process over time between the conventional sputtering apparatus and the present embodiment. When using conventional equipment, the surface oxide film increases from 7 Å to 28 Å after 30 minutes of pre-sputtering, as shown in curve 14.
On the other hand, in the case of this embodiment, as shown in curve 15, the surface of the substrate 5 does not change even after 30 minutes, and the surface of the substrate 5 grows to 7 Å when the substrate is loaded onto the substrate electrode 6 of the vacuum chamber 1. No growth of surface oxide film beyond the natural oxide film present on the surface was observed.
上記結果から、従来のスパツタリング装置では
不可能であつたプリスパツタリング過程における
基板表面の酸化膜成長の防止が、上記シヤツタ機
構１１を備えた本実施例によつて可能になつた。
なお上記第４図は表面酸化膜に対する効果を示す
が、表面窒化膜の成長抑制についても同様の効果
を有することはいうまでもない。 From the above results, it is possible to prevent the growth of an oxide film on the substrate surface during the pre-sputtering process, which was impossible with the conventional sputtering apparatus, by using the present embodiment equipped with the shutter mechanism 11.
Although FIG. 4 above shows the effect on the surface oxide film, it goes without saying that the same effect can be obtained on suppressing the growth of the surface nitride film.
第５図は、同一の形成条件でSi基板上に形成し
たTa2O5を絶縁層とするMIS型キヤパシタの電流
―電圧特性を、従来のスパツタリング装置と本実
施例の装置とで実施した場合について比較したも
のである。本実施例によりプリスパツタリング過
程の表面酸化膜の成長を抑制した結果、曲線１６
に示すように漏れ電流は８桁減少し、絶縁破壊耐
圧は10倍以上に増大した。上記シヤツタ機構１１
を用いた本実施例により形成した薄膜の漏れ電流
の大きさは、半導体素子への適用基準を十分満足
するものである。 Figure 5 shows the current-voltage characteristics of an MIS type capacitor formed on a Si substrate under the same formation conditions and using Ta 2 O 5 as an insulating layer, using a conventional sputtering device and the device of this example. This is a comparison of the following. As a result of suppressing the growth of the surface oxide film during the pre-sputtering process in this example, curve 16
As shown in Figure 2, leakage current decreased by eight orders of magnitude, and dielectric breakdown voltage increased by more than 10 times. The above shutter mechanism 11
The magnitude of the leakage current of the thin film formed according to this example using the method sufficiently satisfies the standards for application to semiconductor devices.
第６図は作製したそれぞれのMIS型キヤパシタ
の静電容量を1MHzにおけるC1MHzで規格化した
規格化容量の周波数分散を比較して示した図であ
る。従来のスパツタリング装置により形成した薄
膜では、曲線１７に示すように静電容量に顕著な
周波数分散が認められ、薄膜中に多数の欠陥が存
在していることを示している。これに対し、本実
施例を用いて形成した薄膜では、曲線１８に示す
ように静電容量に周波数分散が認められず、欠陥
が少ない高品質の絶縁体薄膜が得られている。ま
た、従来のスパツタリング装置により作製した薄
膜の誘電損失は６％であるのに対し、本実施例を
用いて作製した薄膜の誘電損失は0.1％以下と非
常に小さく、この点からも高品質の薄膜が得られ
ることがわかる。 FIG. 6 is a diagram showing a comparison of the frequency dispersion of the normalized capacitance, which is obtained by normalizing the electrostatic capacitance of each manufactured MIS type capacitor by C 1 MHz at 1 MHz. In the thin film formed by the conventional sputtering apparatus, significant frequency dispersion in capacitance is observed as shown by curve 17, indicating that many defects are present in the thin film. In contrast, in the thin film formed using this example, no frequency dispersion was observed in the capacitance, as shown by curve 18, and a high quality insulating thin film with few defects was obtained. Furthermore, while the dielectric loss of the thin film produced using conventional sputtering equipment is 6%, the dielectric loss of the thin film produced using this example is extremely small at 0.1% or less. It can be seen that a thin film can be obtained.
上記の結果から明らかなように、上記のシヤツ
タ機構１１を用いた本発明のスパツタリング装置
により、プリスパツタリング過程におけSi基板表
面の酸化膜の成長を防止した結果、漏れ電流が低
く、絶縁耐圧が高く、誘電損失が小さい高品質の
絶縁体薄膜をSi基板上に形成すことが可能になつ
た。 As is clear from the above results, the sputtering apparatus of the present invention using the above shutter mechanism 11 prevents the growth of an oxide film on the surface of the Si substrate during the pre-sputtering process, resulting in low leakage current and insulation. It has become possible to form high-quality insulating thin films with high breakdown voltage and low dielectric loss on Si substrates.
なお、上記第５図、第６図には、Si基板表面に
形成したTa2O5を絶縁体薄膜とするMISキヤパシ
タの特性によつて、上記シヤツタ機構を有する本
発明のスパツタリング装置の効果を説明したが、
GaAsなどの他の半導体基板表面に形成する場合
や、窒化物の絶縁体薄膜を形成する場合について
も、同様の効果が得られることはいうまでもな
い。 5 and 6 above, the effect of the sputtering apparatus of the present invention having the above-mentioned shutter mechanism is shown in FIG. I explained, but
It goes without saying that similar effects can be obtained when forming on the surface of other semiconductor substrates such as GaAs, or when forming a nitride insulator thin film.
第７図は本発明によるスパツタリング装置の他
の実施例を示す部分断面した構成図である。本実
施例においては、シヤツタ機構１９の側壁２０が
真空槽１の基板電極６の近傍に、基板電極６を取
巻くように取付けられ、上記側壁２０の下部開放
面には、上記実施例と同様に複数のブレードより
なるシヤツタ２１がターゲツト３に対向して設け
られている。したがつてシヤツタ２１を閉じた状
態では、上記シヤツタ機構１９の側壁２０とシヤ
ツタ２１とにより、基板５を設置した基板電極６
全体を包み込むように遮蔽することになり、プリ
スパツタリング過程においてプラズマを発生させ
ても、シヤツタ２１を閉じた状態では基板５の表
面がプラズマを含む雰囲気中にさらされることが
なく、上記実施例と同様に基板表面に酸化膜また
は窒化膜が形成されることがない。 FIG. 7 is a partially sectional configuration diagram showing another embodiment of the sputtering apparatus according to the present invention. In this embodiment, the side wall 20 of the shutter mechanism 19 is attached to the vicinity of the substrate electrode 6 of the vacuum chamber 1 so as to surround the substrate electrode 6, and the lower open surface of the side wall 20 is provided with the same structure as in the above embodiment. A shutter 21 consisting of a plurality of blades is provided facing the target 3. Therefore, when the shutter 21 is closed, the side wall 20 of the shutter mechanism 19 and the shutter 21 allow the substrate electrode 6 on which the substrate 5 is installed to be
Since the entire surface is covered with a shield, even if plasma is generated during the pre-sputtering process, the surface of the substrate 5 will not be exposed to the plasma-containing atmosphere when the shutter 21 is closed. As in the example, no oxide film or nitride film is formed on the substrate surface.
〔発明の効果〕
上記のように本発明によるスパツタリング装置
は、シヤツタ機構を有するスパツタリング装置に
おいて、上記シヤツタ機構を閉じた際に、基板電
極に設置した基板の表面を包み込むように遮蔽で
きるシヤツタ機構のシヤツタを、上記スパツタリ
ング装置のターゲツトに対向して設けたことによ
り、プリスパツタリングの過程で上記シヤツタを
閉じれば、上記基板はプラズマを含む雰囲気から
隔離されるため、SiやGaAsなどの半導体基板表
面に表面酸化膜や表面窒化膜が成長するのを防止
でき、高品質の絶縁体薄膜を上記半導体基板の表
面に形成することが可能である。[Effects of the Invention] As described above, the sputtering apparatus according to the present invention is a sputtering apparatus having a shutter mechanism, and the sputtering apparatus has a shutter mechanism that can wrap around and shield the surface of the substrate placed on the substrate electrode when the shutter mechanism is closed. Since the shutter is provided facing the target of the sputtering device, when the shutter is closed during the pre-sputtering process, the substrate is isolated from the plasma-containing atmosphere. It is possible to prevent a surface oxide film or a surface nitride film from growing on the surface, and it is possible to form a high quality insulating thin film on the surface of the semiconductor substrate.
第１図は本発明によるスパツタリング装置の一
実施例を示す構成図、第２図は上記スパツタリン
グ装置におけるシヤツタ機構を示す図で、ａは下
面図、ｂは正面図、第３図はシヤツタの開閉状態
を示す図で、ａは閉状態、ｂは開状態、第４図は
プリスパツタリングの過程におけるSi基板表面の
表面酸化膜の形成状態を示す図、第５図はSi基板
上に同一条件で形成したTa2O5を絶縁体薄膜とす
るMIS型キヤパシタの電流―電圧特性を示す図、
第６図は作製したそれぞれのMIS型キヤパシタの
静電容量の周波数分散を示す図、第７図は本発明
の他の実施例を示す部分断面した構成図、第８図
は従来のスパツタリング装置の構成図、第９図は
従来装置におけるプリスパツタリング過程の表面
酸化膜形成状態を示す図、第１０図は形成した
Ta2O5薄膜を絶縁体薄膜とするMIS型キヤパシタ
の断面図、第１１図は上記MIS型キヤパシタの電
流電圧特性を示す図である。
３…ターゲツト、５…基板、６…基板電極、１
１，１９…シヤツタ機構、１１′，２１…シヤツ
タ。
FIG. 1 is a block diagram showing an embodiment of a sputtering device according to the present invention, FIG. 2 is a diagram showing a shutter mechanism in the sputtering device, in which a is a bottom view, b is a front view, and FIG. 3 is a diagram showing opening and closing of the shutter. Figure 4 shows the state of formation of a surface oxide film on the Si substrate surface during the pre-sputtering process, and Figure 5 shows the same state on the Si substrate. A diagram showing the current-voltage characteristics of an MIS type capacitor using Ta 2 O 5 as an insulator thin film formed under the following conditions.
FIG. 6 is a diagram showing the frequency dispersion of capacitance of each manufactured MIS type capacitor, FIG. 7 is a partially cross-sectional configuration diagram showing another embodiment of the present invention, and FIG. 8 is a diagram showing a conventional sputtering device. The configuration diagram, Fig. 9 shows the state of surface oxide film formation in the pre-sputtering process in the conventional equipment, and Fig. 10 shows the formed state.
FIG. 11 is a sectional view of an MIS type capacitor using a Ta 2 O 5 thin film as an insulating thin film, and is a diagram showing the current-voltage characteristics of the MIS type capacitor. 3...Target, 5...Substrate, 6...Substrate electrode, 1
1, 19...Shutter mechanism, 11', 21...Shutter.
Claims (1)
おいて、上記シヤツタ機構を閉じた際に、基板電
極に設置した基板の表面を、包み込むように遮蔽
できるシヤツタ機構のシヤツタを、上記スパツタ
リング装置のターゲツトに対向して設け、かつ、
上記シヤツタ機構は、上記基板電極に直接取り付
けられるか、または上記基板電極の近傍に取り付
けられていることを特徴とするスパツタリング装
置。1. In a sputtering device having a shutter mechanism, a shutter of the shutter mechanism is provided opposite to a target of the sputtering device, and is capable of covering the surface of the substrate placed on the substrate electrode when the shutter mechanism is closed. and,
The sputtering apparatus is characterized in that the shutter mechanism is attached directly to the substrate electrode or in the vicinity of the substrate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7674385A JPS61235558A (en) | 1985-04-12 | 1985-04-12 | Sputtering device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7674385A JPS61235558A (en) | 1985-04-12 | 1985-04-12 | Sputtering device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61235558A JPS61235558A (en) | 1986-10-20 |
| JPH021229B2 true JPH021229B2 (en) | 1990-01-10 |
Family
ID=13614082
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7674385A Granted JPS61235558A (en) | 1985-04-12 | 1985-04-12 | Sputtering device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61235558A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7470329B2 (en) * | 2003-08-12 | 2008-12-30 | University Of Maryland | Method and system for nanoscale plasma processing of objects |
| JP2011190530A (en) * | 2010-02-16 | 2011-09-29 | Canon Anelva Corp | Shutter device and vacuum processing apparatus |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5665981A (en) * | 1979-11-02 | 1981-06-04 | Hitachi Ltd | Sputtering device |
-
1985
- 1985-04-12 JP JP7674385A patent/JPS61235558A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5665981A (en) * | 1979-11-02 | 1981-06-04 | Hitachi Ltd | Sputtering device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61235558A (en) | 1986-10-20 |
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