JPH0212109A - Manufacture of optical integrated circuit - Google Patents

Manufacture of optical integrated circuit

Info

Publication number
JPH0212109A
JPH0212109A JP16091488A JP16091488A JPH0212109A JP H0212109 A JPH0212109 A JP H0212109A JP 16091488 A JP16091488 A JP 16091488A JP 16091488 A JP16091488 A JP 16091488A JP H0212109 A JPH0212109 A JP H0212109A
Authority
JP
Japan
Prior art keywords
wafer
scratches
stress
optical integrated
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16091488A
Other languages
Japanese (ja)
Inventor
Shinji Nagaoka
長岡 新二
Norio Nishi
功雄 西
Senta Suzuki
扇太 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP16091488A priority Critical patent/JPH0212109A/en
Publication of JPH0212109A publication Critical patent/JPH0212109A/en
Pending legal-status Critical Current

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  • Element Separation (AREA)
  • Optical Integrated Circuits (AREA)

Abstract

PURPOSE:To enable highly-accurate chip segmenting which is superior in mass- productivity and yield by forming a cleavage flaw at a specific position of a wafer peripheral part by laser beam irradiation, then straining the entire surface of the wafer and advancing the cleavage at a time, and segmenting many circuit chips at the same time. CONSTITUTION:A wafer 41 is installed on a stage 49 with a fine adjusting mechanism and the specific position on the wafer periphery is irradiated with a laser beam 43 to specific length to make a flaw 44. Then the wafer 41 is detached from the stage 49 and sandwiched between two transparent cohesive films 54, whose peripheral parts are fixed hermetically to the opening part 56 of a box 55. Then air is admitted to the box 55 from an air intake 57 to increase the internal air pressure and then the films 54 expand owing to the air pressure difference to cleave along the flaw 53 at a time, thereby dividing chips 52 of individual circuits. Consequently, the highly-accurate chip segmenting which is superior in mass-productivity and yield is enabled.

Description

【発明の詳細な説明】 〈産業上の利用分計〉 本発明は光集積回路の製造において、複数の先導波回路
の形成されるウェハをそれぞれの光導波回路チップに切
り出す方法の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION <Industrial Application> The present invention relates to an improvement in a method for cutting out a wafer on which a plurality of leading wave circuits are formed into respective optical waveguide circuit chips in the production of optical integrated circuits.

〈従来の技術〉 第3図、第4図に光S積回路の従来技術例を示す。第3
図は高見 等(昭和61年度電子通信学会総合全国大会
、No、1050 )による波長多重伝送システム用の
集積化光分波回路であり、シリコン単結晶基板上に形成
された薄膜光導波膜11上にコリメーシヨンならびに集
光用レンズ13、透過形回折格子12が形成され、基板
両端16に入出力ファイバ14、Isが設けられている
。第4図はT、5UHARA at、al(Appl、
Phys、Latt、、VOL。
<Prior Art> FIGS. 3 and 4 show examples of the prior art of optical S product circuits. Third
The figure shows an integrated optical demultiplexing circuit for a wavelength division multiplexing transmission system by Takami et al. (National Conference of the Institute of Electronics and Communication Engineers, 1985, No. 1050), which is mounted on a thin optical waveguide film 11 formed on a silicon single crystal substrate. A collimation and condensing lens 13 and a transmission type diffraction grating 12 are formed on the substrate, and input/output fibers 14 and Is are provided at both ends 16 of the substrate. Figure 4 shows T, 5UHARA at, al (Appl,
Phys, Latt,, VOL.

40、磁2.P、120. (1982) )によるグ
レーティング分波器22とフォトダイオード23をシリ
コン基板21上の薄膜光導波膜24に集積化した例であ
る。尚、第4図中、25は入力ファイバ、26は光導波
膜端面である。これらの回路はシリコン基板上に形成さ
れた光導波回路を基本要素とし、それと受発光素子やフ
ァイバ、さらに電子回路とを組み合わせた所謂ハイブリ
ッド光集積回路と称せられるものであるが、単一のI−
V族化合物半導体基板上に光導波回路、受発光素子、電
子回路を一括形成したモノリシック光集積回路も報告さ
れている。いずれの光集積回路においても、LSI製造
技術と同様にウニへ上の結晶基板上に複数の回路をフォ
トリソグラフィー技術により形成し、しかる後に各回路
についてチップとして切り出されて使用される。チップ
として切り出す際にはLSIでは外周刃による切断のみ
でよいが、光集積回路では導波回路とファイバとの良好
な接続特性を得るために第3図、第4図における導波回
路端面16.26の平滑度を使用波長の数分の1以下に
仕上げる必要がある。このため、従来のとの厘の光集積
回路の製造ではチップを切り出す際に、切断の後に導波
回路端面を光学研磨する方法や結晶基板の方位に沿って
種間する方法が採られている。
40, magnetic 2. P, 120. (1982)) is an example in which a grating demultiplexer 22 and a photodiode 23 are integrated into a thin optical waveguide film 24 on a silicon substrate 21. In FIG. 4, 25 is an input fiber, and 26 is an end face of an optical waveguide film. These circuits are so-called hybrid optical integrated circuits, in which the basic element is an optical waveguide circuit formed on a silicon substrate, which is combined with light-receiving and emitting elements, fibers, and electronic circuits. −
A monolithic optical integrated circuit in which an optical waveguide circuit, a light receiving/emitting element, and an electronic circuit are collectively formed on a group V compound semiconductor substrate has also been reported. In any optical integrated circuit, a plurality of circuits are formed on a crystal substrate by photolithography, similar to LSI manufacturing technology, and then each circuit is cut out as a chip and used. When cutting out a chip, LSI requires only cutting with a peripheral blade, but in optical integrated circuits, in order to obtain good connection characteristics between the waveguide circuit and the fiber, the waveguide circuit end face 16. shown in FIGS. 3 and 4 is used. It is necessary to achieve a smoothness of 26 that is less than a fraction of the wavelength used. For this reason, in the conventional manufacturing of optical integrated circuits, when cutting chips, a method of optically polishing the end face of the waveguide circuit after cutting or a method of seeding along the orientation of the crystal substrate is adopted. .

〈発明が解決しようとする課題〉 しかしながら、切断後に導波路端面を光学研磨する前者
の方法は切断、研磨の工程が煩雑であるとともに作業に
長時間を要しかつ薄膜導波路端面の破損等により良好な
歩留りを得る事が困難であった。これに対して結晶基板
の方位に沿って種間する後者の方法は結晶の種間ととも
に薄膜導波路を同時に切断するため、良好な導波路端面
が簡便に得られる。
<Problems to be Solved by the Invention> However, the former method of optically polishing the end face of the waveguide after cutting requires complicated cutting and polishing steps, takes a long time, and is prone to damage to the end face of the thin film waveguide. It was difficult to obtain a good yield. On the other hand, in the latter method of cutting the seeds along the orientation of the crystal substrate, the thin film waveguide is cut simultaneously with the crystal seeds, so that a good waveguide end face can be easily obtained.

ここで、従来のり開法によるチップ切り出しの工程はそ
の一例を第5図に示すように、まず同図(alのように
傷入れ用のダイアモンド針33でウェハ31上のファセ
ット35に沿って全長または一部(太線部分)に種間用
傷34を入れ、その後種間用鍋34にブレードで同図(
b)に示すように応力Fをかけ短冊状に種間する。次に
、この短冊状の基板に同図(clに示すように傷入れと
応力付与を行い、最終的に同図(d)に示すようにチッ
プ32を得る。ところが、このようなり開法では、傷入
れや応力付与の作業回数が多(かつその作業条件が複雑
で量産性や歩留りを高めることが困難であった。また、
傷入れを所定の位置にミクロンオーダで精確に付与する
ことも困難であった。
Here, an example of the chip cutting process using the conventional gluing method is shown in FIG. 5. First, as shown in FIG. Alternatively, make an interspecies wound 34 in a part (thick line part), and then use a blade on the interspecies pot 34 as shown in the figure (
As shown in b), stress F is applied to separate the seeds into strips. Next, this strip-shaped substrate is scratched and stressed as shown in the same figure (cl), and finally a chip 32 is obtained as shown in the same figure (d). However, in this open method, , the number of times of scratching and applying stress was high (and the working conditions were complex, making it difficult to increase mass productivity and yield.
It was also difficult to accurately make scratches on the order of microns at predetermined positions.

本発明の目的は光集積回路の製造において、ウェハから
光学的に良好な導波回路端面を有するチップを切り出す
ためのつ工へ壱開法に関し、前述の従来技術の欠点を解
決し、高精度で量産性や歩留りに優れもチップ切り出し
法を提供する点にある。
The purpose of the present invention is to solve the above-mentioned drawbacks of the prior art and to achieve high accuracy in the production of optical integrated circuits, with respect to a die-cutting method for cutting out chips having optically good waveguide circuit end faces from a wafer. It also provides a chip cutting method that is superior in mass production and yield.

く課題を解決するための手段〉 本発明は光集積回路形成゛ウェハから光学的に良好な導
波回路端面を有するチップを切り出す際に、ウェハ周辺
部の所定の位置に例えばYAGまたはCO2レーザビー
ムを所定の長さに渡って照射し、その位置にある幅と深
さを持った微細な傷を精度良く入れ、その後ウェハ全面
に応力を付与して前記傷に応力集中させることによりウ
ェハを前記の傷に沿って一括に壱開し、多数のチップを
同時に切り出す方法である。従って、本発明は従来の技
術に比ベレーザピームによる傷入れと全体的な応力付与
という簡単な手段によって高精度で量産性や歩留りに優
れるチップ切り出しが可能となる点で異なる。
Means for Solving the Problems> The present invention aims at forming optical integrated circuits.When cutting out chips having optically good waveguide circuit end faces from a wafer, a YAG or CO2 laser beam, for example, is applied to a predetermined position on the periphery of the wafer. The wafer is irradiated over a predetermined length to accurately create minute scratches with a certain width and depth at that location, and then stress is applied to the entire surface of the wafer to concentrate stress on the scratches. This method involves cutting out multiple chips at once along the wound. Therefore, the present invention differs from the prior art in that it is possible to cut out chips with high precision and excellent mass productivity and yield by simple means of making scratches with a laser beam and applying stress overall.

く実 施 例〉 以下、本発明の一実施例について図面を参照して詳細に
説明する。
Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

第1図及び第2図に本発明の一実施例を示す。第1図は
複数の光集積回路の形成されるウェハへの傷入れ方法を
示し、第2図(a) (b)は傷の入れられたウェハへ
の応力付与方法を示すものである。
An embodiment of the present invention is shown in FIGS. 1 and 2. FIG. FIG. 1 shows a method of making scratches on a wafer on which a plurality of optical integrated circuits are formed, and FIGS. 2(a) and 2(b) show a method of applying stress to the scratched wafer.

まず、第1図に示されるようにシリコン基板又は■−■
族化合物半導体基板であろウェハ41を微動機構付ステ
ージ49上に設置し、ウニ八周辺上の所定位置にレーザ
ビーム43を所定の長さに渡って照射して傷44を入れ
る。レーザビーム43は、レーザ光源48により出射し
、ミラー47により屈折させられレンズ46により収束
してウェハ上へ照射される。傷入れに際しては、基板結
晶の方位を決定するファセット45に対し、傷44が平
行で一定間隔となるようステージ49を移動させ、更に
ファセット45に対し、傷が垂直で一定間隔となるよう
ステージ49を移動させる。傷の深さや幅はレーザ光源
48の出力やアパーチャーによって任意に調整可能であ
る。ステージ49及びレーザ光源48をコンピュータ制
御すれば傷入れ作業の迅速化と劣力化が可能である。以
上の工程によりウェハ周辺部に傷入れが完了したら、ス
テージ49から取り外して第2図(al (b)に示す
ようにウェハ51を2枚の透明粘着フィルム54の間に
挾み込む。そして、これらのフィルム54の周辺部をボ
ックス55の開口部56に気密に固定する。この後ボッ
クス55に空気導入口57より空気を導入して内部気圧
を増大させる。気圧差によりフィルム54が膨張すると
同時にこれらに挾まれたウェハ51に応力が全体的に作
用する。ここでウェハ51に作用する応力は均一に作用
するのでなく、傷53に集中する。このため、ウェハ5
1は傷53に沿って一括に種間し、個々の回路について
のチップ52に分割される。図中、59は種間面である
。その後、フィルム54をボックス55の開口部から取
り外すが、この状態では各チップ52は粘着性フィルム
54に保持されてウェハの状態と同様に整列しているの
で、その後の取り扱いが容易となる。
First, as shown in Fig. 1, a silicon substrate or
A wafer 41, which may be a group compound semiconductor substrate, is placed on a stage 49 with a fine movement mechanism, and a laser beam 43 is irradiated over a predetermined length at a predetermined position on the periphery of the urchin to create a scratch 44. The laser beam 43 is emitted by a laser light source 48, refracted by a mirror 47, converged by a lens 46, and irradiated onto the wafer. When making scratches, the stage 49 is moved so that the scratches 44 are parallel to the facets 45 that determine the orientation of the substrate crystal and are spaced at regular intervals, and the stage 49 is moved so that the scratches are perpendicular to the facets 45 and at regular intervals. move. The depth and width of the scratch can be arbitrarily adjusted by adjusting the output and aperture of the laser light source 48. If the stage 49 and the laser light source 48 are controlled by a computer, it is possible to speed up the incision work and reduce the power required. Once the wafer periphery has been scratched through the above steps, it is removed from the stage 49 and the wafer 51 is sandwiched between two transparent adhesive films 54 as shown in FIG. 2 (al(b)). The peripheral parts of these films 54 are hermetically fixed to the opening 56 of the box 55. After that, air is introduced into the box 55 from the air inlet 57 to increase the internal pressure. At the same time, the film 54 expands due to the pressure difference. Stress acts on the entire wafer 51 held between these.The stress acting on the wafer 51 here does not act uniformly, but concentrates on the scratches 53.For this reason, the wafer 51
1 is injected all at once along the scratch 53 and divided into chips 52 for individual circuits. In the figure, 59 is an interspecific surface. Thereafter, the film 54 is removed from the opening of the box 55, but in this state each chip 52 is held by the adhesive film 54 and aligned in the same manner as a wafer, making subsequent handling easier.

このように本発明では種間用の傷入れをレーザビームの
照射で精度良く形成し、さらにウェハ全面に応力を付与
して一括種間するので、従来技術に較べて光集積回路チ
ップの切り出し作業性や歩留りが向上すると共にブレー
ドやダイアモンド針の交換も不要となる。
In this way, in the present invention, the interseating scratches are formed with high precision by laser beam irradiation, and stress is applied to the entire surface of the wafer to perform the interseating at once, so the cutting process of optical integrated circuit chips is much easier than with the conventional technology. In addition to improving performance and yield, there is no need to replace blades or diamond needles.

〈発明の効果〉 以上、実施例に基づいて具体的に説明したように本発明
は複数の光集積回路の形成されるつ工へからり開によっ
て回路チップを切り出す際に、ウェハ周辺部の所定の位
置に剪開用鍋をレーザビーム照射で形成し、その後、ウ
ェハ全面に応力を付与して一括に種間を進行させ、同時
に多数の回路チップを切り出す方法であるから、以下の
効果を奏する。
<Effects of the Invention> As described above in detail based on the embodiments, the present invention provides a method for cutting out circuit chips by cutting out circuit chips by cutting out a workpiece in which a plurality of optical integrated circuits are formed. This method involves forming a pruning pot at the position of the wafer by irradiating it with a laser beam, and then applying stress to the entire surface of the wafer to advance the seeds all at once, cutting out a large number of circuit chips at the same time.This method has the following effects: .

■ レーザビームのパワー ビームサイズを任意に制御
できるから、種間する基板の厚みや大きさの変化に対し
て傷入れ条件を容易に設定することが可能となる。
■ Laser beam power Since the beam size can be controlled arbitrarily, it is possible to easily set the incision conditions to accommodate changes in the thickness and size of the interfering substrate.

■ 傷入れ箇所や傷の寸法の高精度化が可能となる。■ It is possible to increase the precision of the scratch location and the dimensions of the scratch.

■ 傷入れを非接触で行うため、ブレードやダイアモン
ド針の消耗がな(、切り出し作業の歩留り向上が得られ
る。
■ Since the incision is made without contact, there is no wear on the blade or diamond needle (and the yield of cutting work can be improved).

■ 種間を一括して行うため、回路チップの量産が可能
となる。
■ Mass production of circuit chips becomes possible because all types are processed at once.

■ ウェハを粘着性フィルムに挾んで応力を加えて種間
を行うと、分割された回路チップが整列状態で保持され
るため、その後の取り扱いが容易となる。
■ By sandwiching the wafer between adhesive films and applying stress, the separated circuit chips are held in an aligned state, making subsequent handling easier.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は本発明の一実施例にかかり、第1図
は、種間用鍋入れを説明するための斜視図、第2図(a
l (blはそれぞれ応力付与方法を示す斜視図、断面
図、第3図、第4図はそれぞれ光集積回路に関する従来
技術の説明図、第5図(a)〜(dlはそれぞれ従来の
光集積回路製造工程における回路チップ切り出し方法を
示す工程図である。 図 面 中、 11は薄膜光導波膜、 12は透過形回折格子、 13はレンズ、 14は入力ファイバ、 15は出力ファイバ、 16は導波膜端面、 21はシリコン基板、 22はグレーティング分波器、 23はフォトダイオード、 24は薄膜光導波膜、 25は入力ファイバ、 26は導波膜端面、 31はウェハ、 32はチップ、 33はダイヤモンド針、 34は襞間用鍋、 35はファセット、 41はウェハ、 42はチップ、 43はレーザビーム 44は傷、 45はファセット、 46はレンズ、 47はミラー 48はレーザ光源、 49はステージ、 51はウェハ、 52はチップ、 53は傷、 54は粘着性フィルム、 55はボックス、 56は開口部、 57は空気導入口、 58は空気排出口、 59は種間面である。
1 and 2 show one embodiment of the present invention, and FIG. 1 is a perspective view for explaining a pot holder for seeds, and FIG. 2 (a
l (bl is a perspective view and a cross-sectional view showing the stress applying method, respectively, FIGS. 3 and 4 are explanatory diagrams of conventional technology related to optical integrated circuits, and FIGS. 5(a) to (dl are respectively illustrations of conventional optical integrated circuits) It is a process diagram showing a circuit chip cutting method in a circuit manufacturing process. In the drawing, 11 is a thin optical waveguide film, 12 is a transmission type diffraction grating, 13 is a lens, 14 is an input fiber, 15 is an output fiber, and 16 is a guide. Wave film end face, 21 is a silicon substrate, 22 is a grating splitter, 23 is a photodiode, 24 is a thin film optical waveguide film, 25 is an input fiber, 26 is a wave guide film end face, 31 is a wafer, 32 is a chip, 33 is a 44 is a diamond needle, 34 is a pan for interfolds, 35 is a facet, 41 is a wafer, 42 is a chip, 43 is a laser beam 44 is a scratch, 45 is a facet, 46 is a lens, 47 is a mirror 48 is a laser light source, 49 is a stage, 51 is a wafer, 52 is a chip, 53 is a scratch, 54 is an adhesive film, 55 is a box, 56 is an opening, 57 is an air inlet, 58 is an air outlet, and 59 is an interspecies surface.

Claims (2)

【特許請求の範囲】[Claims] (1)シリコン基板又はIII−V族化合物半導体基板上
に形成された光導波回路を基本要素とする光集積回路の
製造において、複数の光導波回路の形成される結晶基板
であるウェハを個々の光導波回路についてのチップに切
り出す際、前記ウェハ周辺部の所定位置に複数の傷をレ
ーザ光により形成し、しかる後に前記ウェハに全体的に
応力を付与して該傷に応力を集中させて該傷に沿わせて
前記ウェハを一括して劈開し、複数の前記チップに分割
したことを特徴とする光集積回路製造法。
(1) In manufacturing optical integrated circuits whose basic elements are optical waveguide circuits formed on silicon substrates or III-V group compound semiconductor substrates, the wafer, which is a crystalline substrate on which multiple optical waveguide circuits are formed, is separated into individual wafers. When cutting out chips for optical waveguide circuits, a plurality of scratches are formed at predetermined positions around the wafer using a laser beam, and then stress is applied to the entire wafer to concentrate the stress on the scratches. A method for manufacturing an optical integrated circuit, comprising cleaving the wafer all at once along the scratches and dividing the wafer into a plurality of chips.
(2)特許請求の範囲第1項において、前記傷の形成さ
れた前記ウェハを2枚の粘着性フィルムの間に挾み込む
と共に該粘着性フィルムの周辺部を固定してその中央部
に気圧差を作用させ、前記ウェハの前記傷に応力を集中
させることを特徴とする光集積回路製造法。
(2) In claim 1, the wafer in which the scratches have been formed is sandwiched between two adhesive films, and the periphery of the adhesive film is fixed, and air pressure is applied to the central part of the wafer. A method for manufacturing an optical integrated circuit, characterized in that stress is concentrated on the scratches on the wafer by applying a stress to the scratches on the wafer.
JP16091488A 1988-06-30 1988-06-30 Manufacture of optical integrated circuit Pending JPH0212109A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16091488A JPH0212109A (en) 1988-06-30 1988-06-30 Manufacture of optical integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16091488A JPH0212109A (en) 1988-06-30 1988-06-30 Manufacture of optical integrated circuit

Publications (1)

Publication Number Publication Date
JPH0212109A true JPH0212109A (en) 1990-01-17

Family

ID=15725048

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16091488A Pending JPH0212109A (en) 1988-06-30 1988-06-30 Manufacture of optical integrated circuit

Country Status (1)

Country Link
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