JPH02119701U - - Google Patents
Info
- Publication number
- JPH02119701U JPH02119701U JP2671089U JP2671089U JPH02119701U JP H02119701 U JPH02119701 U JP H02119701U JP 2671089 U JP2671089 U JP 2671089U JP 2671089 U JP2671089 U JP 2671089U JP H02119701 U JPH02119701 U JP H02119701U
- Authority
- JP
- Japan
- Prior art keywords
- set value
- circuit
- input
- input terminal
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Description
第1図はこの考案の一実施例を示す接続図、第
2図はこの考案を高周波整合回路に応用する場合
の接続図、第3図は従来の回路を示す接続図。
IC1はプリセツタカウンタ、Rf1〜Rf4
は帰還抵抗、D1〜D4は設定値入力端子、Q1
〜Q4は設定値出力端子、PRはプリセツト信号
入力端子、UPは設定値変更パルス入力端子(増
加)、DNは設定値変更パルス入力端子(減少)
、S10は手動/自動切り替えスイツチ、S11
は手動データ設定スイツチ、IC2はマイクロプ
ロセツサ、P1〜P4は入出力端子、IC3は設
定信号電流増幅IC、K1〜K4は整合回路コン
デンサ切り替えリレー、C1〜C4は整合用コン
デンサ、L1は整合用インダクタ。なお、各図中
同一符号は同一又は相当部分を示すものとする。
FIG. 1 is a connection diagram showing an embodiment of this invention, FIG. 2 is a connection diagram when this invention is applied to a high frequency matching circuit, and FIG. 3 is a connection diagram showing a conventional circuit. IC1 is a preset counter, Rf1 to Rf4
is a feedback resistor, D1 to D4 are set value input terminals, Q1
~Q4 is the set value output terminal, PR is the preset signal input terminal, UP is the set value change pulse input terminal (increase), DN is the set value change pulse input terminal (decrease)
, S10 is a manual/automatic changeover switch, S11
is a manual data setting switch, IC2 is a microprocessor, P1 to P4 are input/output terminals, IC3 is a setting signal current amplification IC, K1 to K4 are matching circuit capacitor switching relays, C1 to C4 are matching capacitors, and L1 is for matching. inductor. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
御回路の制御の手動/自動切り替えを行う設定回
路において、 上記設定回路から送られてくる設定値を入力す
る設定値入力端子と、この設定値入力端子の信号
をカウンタとして構成された内部メモリに書き込
むタイミングを与えるプリセツト信号を入力する
プリセツト信号入力端子と、上記内部メモリによ
り構成されたカウンタにより計数されるパルスを
入力する設定値変更パルス入力端子と、上記メモ
リに記憶された設定値を出力する設定値出力端子
とを有するプリセツタブルカウンタ、 このプリセツタブルカウンタの上記設定値出力
端子と上記設定値入力端子とを帰還抵抗を介して
接続した帰還回路を備え、 上記被制御回路を自動制御する場合には、上記
設定値入力端子に送られてきた上記制御回路から
の設定値をプリセツト信号毎に上記メモリに記憶
して上記設定値出力端子へ出力し、上記被制御回
路を手動制御する場合にはプリセツト信号の入力
を遮断し、上記メモリに記憶されている設定値を
変更する場合は上記設定値変更パルス入力端子か
らパルスを入力して設定値を変更して上記設定値
出力端子へ出力し、これらの設定値出力端子の出
力を上記帰還回路で上記設定値入力端子へ帰還さ
せ必要な場合に上記制御回路で読み取らせること
を特徴とする設定回路。[Claims for Utility Model Registration] In a setting circuit that is connected between a control circuit and a controlled circuit and performs manual/automatic switching of control of the controlled circuit, a setting value sent from the setting circuit is input. A set value input terminal, a preset signal input terminal for inputting a preset signal that provides timing for writing the signal of this set value input terminal into an internal memory configured as a counter, and pulses counted by a counter configured by the internal memory. a presettable counter having a set value change pulse input terminal for inputting the set value, and a set value output terminal for outputting the set value stored in the memory; the set value output terminal and the set value input of the presettable counter; A feedback circuit connected to a terminal via a feedback resistor is provided, and when the controlled circuit is automatically controlled, the set value from the control circuit sent to the set value input terminal is input to the above for each preset signal. The set value is stored in the memory and output to the above set value output terminal, and when the above controlled circuit is manually controlled, the input of the preset signal is cut off, and when the set value stored in the above memory is changed, the above set value is output. Input a pulse from the change pulse input terminal to change the set value and output it to the above set value output terminal, and the output of these set value output terminals is fed back to the above set value input terminal by the above feedback circuit when necessary. A setting circuit characterized by being read by the control circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989026710U JPH082722Y2 (en) | 1989-03-10 | 1989-03-10 | Setting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989026710U JPH082722Y2 (en) | 1989-03-10 | 1989-03-10 | Setting circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02119701U true JPH02119701U (en) | 1990-09-27 |
JPH082722Y2 JPH082722Y2 (en) | 1996-01-29 |
Family
ID=31248583
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1989026710U Expired - Fee Related JPH082722Y2 (en) | 1989-03-10 | 1989-03-10 | Setting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH082722Y2 (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5977502A (en) * | 1982-10-27 | 1984-05-04 | Hitachi Ltd | Automatic/manual switching circuit |
JPS6086601A (en) * | 1983-10-18 | 1985-05-16 | Mitsubishi Electric Corp | Following circuit |
-
1989
- 1989-03-10 JP JP1989026710U patent/JPH082722Y2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5977502A (en) * | 1982-10-27 | 1984-05-04 | Hitachi Ltd | Automatic/manual switching circuit |
JPS6086601A (en) * | 1983-10-18 | 1985-05-16 | Mitsubishi Electric Corp | Following circuit |
Also Published As
Publication number | Publication date |
---|---|
JPH082722Y2 (en) | 1996-01-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |