JPH02119485A - High efficiency coding device for picture signal - Google Patents

Abstract

PURPOSE:To attain a high compression rate and to make the quantity of generated data nearly constant by using together the compression in the level direction. CONSTITUTION:A dynamic range DR is detected for each block in coding circuits 2-10 and the dynamic range DR is divided by a value corresponding to a quantized bit number (n) to calculate a quantization step. The data after minimum value elimination is quantized in the quantized step. The quantized bit number (n) in response to the dynamic range DR is set to 1-4 bits, for example. That is, as the dynamic range DR is larger, the quantized bit number (n) is increased. Thus, the data compression rate is increased and the increased quantization distortion is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a high-efficiency encoding device for image signals such as television signals, and in particular to a configuration that combines subsampling and encoding adapted to a dynamic range. .

[Summary of the invention]

This invention is a hybrid configuration in which data obtained by variable-length encoding adapted to the dynamic range is thinned out by subsampling, and the data can be efficiently compressed. In response to the,
By determining the subsampling thinning rate, the amount of data generated for each block can be made approximately constant depending on the transmission capacity.

[Conventional technology]

When transmitting a digital video signal, a known method for compressing the amount of transmitted data compared to the original amount of data is to thin out pixels by subsampling and lower the sampling frequency. As one type of subsampling, a method has been proposed in which image data is thinned out to %, and a subsampling point and a 2-bit flag indicating the position of the subsampling point used during interpolation are transmitted. One pixel data of digital video signal is 8
In the case of bits, if 2 bits of flag are added, 1 pixel becomes 5 bits, and the compression ratio becomes (5/8).

In this conventional subsampling, since the subsampling pattern is always the same, there is a problem in that the restored image quality is noticeably degraded in areas such as the outline of an object in the image.

In particular, when the subsampling rate is higher than A,
The drawback was that the image quality deteriorated significantly.

The applicant of the present invention has proposed a high-efficiency encoding device for image signals that can form an arbitrary subsampling pattern adapted to the characteristics of an image and can obtain a good restored image. (Refer to the specification of Japanese Patent Application No. 62-208957).

In addition, it has the same advantages as the invention described in the above application specification, uses real data when calculating interpolation errors, and therefore can perform real-time processing, and is capable of processing image signals that can be applied to moving images. A high-efficiency encoding device has been proposed by the applicant of the present invention (see Japanese Patent Application No. 85210/1983).

[Problem to be solved by the invention]

For the previously proposed variable density subsampling,
Applicable to transmission channels (such as digital VTRs) where the amount of generated data changes greatly depending on the degree of image correlation due to adaptive thinning processing, and the amount of transmitted data requires a nearly constant data rate. There was a problem in doing so. Also,
When the transmission capacity is small, subsampling alone is insufficient to reduce the amount of data.

Therefore, an object of the present invention is to provide a highly efficient encoding device for image signals that can achieve a high compression rate and keep the amount of generated data approximately constant by using level-direction compression. There is a particular thing.

[Means for Solving the Problem] In the present invention, a digital image signal is converted into a block structure formed by a plurality of pixels, the dynamic range DR within the block is detected, and the original quantum 2.3.4.5.6.7. Encoding circuit that allocates a variable number n of quantization bits smaller than the number of quantization bits to pixel data in a block and generates a quantization code DT.
8.9.10, interpolation processing similar to that performed on the receiving side is performed using multiple pixels around each of the pixels 81 to S16 in the block, and the data obtained by interpolation is and the interpolation error detection circuit 17 that detects the error between Regarding the circuit 20 to be determined and the above-mentioned errors within the block, in order of decreasing error,
A circuit 14.19 is provided that selectively outputs a number of quantization codes DT corresponding to the thinning rate.

[Effect]

As an example, a digital video signal is converted into a block structure of (4×4) pixels and fed to a dynamic range adaptive encoding circuit. In this encoding circuit, a dynamic range DR is detected for each block, and a quantization step is calculated by dividing the dynamic range DR by a value corresponding to the number of quantization bits n. In this quantization step, the data after minimum value removal is quantized. The number of quantization bits n is set, for example, from 1 bit to 4 bits depending on the dynamic range DR. That is, the larger the dynamic range DR, the larger the number n of quantization bits, the higher the data compression rate, and the greater the quantization distortion.

The n-bit quantization code of this encoding circuit is supplied to a gate circuit 14 for subsampling.

Selection of transmission and thinning of quantization codes within one block is made according to the above-mentioned number of quantization bits n and the magnitude of interpolation error.For example, when the number of quantization bits n is 1, the decimation rate is 1. In the case of (n=2), the thinning rate is set to B, in the case of (n=3), the thinning rate is set to 1/3, and in the case of (n=4), the thinning rate is set to B. The rate is assumed to be 174.

On the other hand, for each block, the interpolation error detection circuit 17 detects an error predicted when interpolation is performed on the thinned out pixels on the receiving side. Interpolation errors (predicted values) regarding 16 pixels within a block are arranged in order according to size. The pixels with the smallest interpolation error are selected as the plurality of pixels to be transmitted according to the above-mentioned thinning rate.

Since this subsampling method makes a decision regarding thinning out for each pixel, it can be highly adaptable to image characteristics.

Since the thinning rate is determined according to the number n of bits of the encoding circuit, the number of bits generated per block can be kept approximately constant. Furthermore, since ADRC and subsampling are used together, the amount of transmitted data is significantly compressed.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. This description is given in the following order.

a. Overall configuration and ADRC encoder b. Interpolation error detection circuit C0 modification a. Overall configuration and ADRC encoder FIG. 1 shows an embodiment of the present invention. A digital image signal, for example a digital video signal, is supplied. This digital video signal has a sampling frequency of 13.5 (MHz), for example, and one pixel data is 8 bits.

A digital video signal is supplied to a blocking circuit 2. As shown in FIG. 2, the blocking circuit 2 converts the image of one field (or one frame) into many blocks Bll.
, B12. ...Subdivide into BNM. Each block has a (4×4) structure as shown in FIG. 3, and one block includes 16 pixel data. The order of data generated from the blocking circuit 2 is the order of blocks indicated by arrows in FIG. Within the block, 16 pixels are transmitted in order from the leftmost pixel of line L1 in FIG. 3 to lines L2, L3, and L4.

The output data of the blocking circuit 2 is supplied to a maximum value detection circuit 3 and a minimum value detection circuit 4, and is also supplied to a subtraction circuit 6 via a delay circuit 5. The maximum value MAX and minimum value MIN are detected for each block by the maximum value detection circuit 3 and the minimum value detection circuit 4.

The maximum value MAX and the minimum value MIN are supplied to the subtraction circuit 7, and the dynamic range D is expressed as (MAX-MIN).
R is obtained from the subtraction circuit 7. The minimum value MIN is supplied to the subtraction circuit 6, and pixel data after the minimum value is removed is obtained from the subtraction circuit 6.

This pixel data is supplied to the quantization circuit 8. The quantization circuit 8 is supplied with the quantization step from the quantization step generation circuit 10, the data normalized by removing the minimum value is divided by the quantization step, and the division result is rounded down. In this way, a quantization code DT is formed.

The quantization code DT has a variable number of bits, for example 1.2.3
Or 4 bits. This number of bits is determined according to the dynamic range DR. Dynamic range DR
is supplied to the ROM 9, and data of n bits is generated from the ROM 9. This bit number n is supplied to the quantization step generation circuit 10, and the quantization step is set. The quantization step generation circuit 10 and the quantization circuit 8 are not limited to division circuits, but can be constructed from a ROM.

The number of bits n increases as the dynamic range DR increases.
considered to be large. For example, as shown in A in Figure 4,
When the dynamic range DR is small, it is assumed that (n=1), and quantization is performed by a quantization step indicated by Δ1,
As shown in FIG. 4B, when the dynamic range DR is larger, (n=2) is set and quantization is performed by a quantization step indicated by Δ2. Nonlinear quantization (Δ1≠Δ2) is performed. The ROM 9 stores a table that associates the dynamic range DR with the number of bits n. The restoration level is the middle of the width of the quantization step.

Dynamic range DR and minimum value MIN are delay circuit 1
1 and 12, respectively, to a framing circuit 15. The quantization code DT from the quantization circuit 8 is sent to the delay circuit 1.
3 to a gate circuit 14 for subsampling. The delay amount DL3 of the delay circuit 13 is (4LD+4
SD). The gate circuit 14 is supplied with a gate signal formed as described below, and the gate circuit 1
A quantization code DT is selectively generated from 4. The output signal of this gate circuit 14 is supplied to a framing circuit 15. The gate signal is a bitmap indicating transmission and thinning, and this bitmap is also supplied to the framing circuit 15.

Dynamic range DR (8 bits), Ji small value MI
N (8 bits), subsampled quantization code (15 or 16 bits), bitmap (16 bits)
is converted into frame-structured transmission data by the framing circuit 15. The framing circuit 15 performs error correction encoding as necessary. Transmission data is taken out to the output terminal 16 of the framing circuit 15. It is sufficient to transmit any two data of the dynamic range DR1 minimum value MIN and maximum value MAX.

A gate signal that controls the transmission and thinning of the quantization code generated in ADRC is generated depending on the number of quantization bits n and the magnitude of the interpolation error. The same interpolation method used to interpolate thinned pixel data on the receiving side is applied to detect interpolation errors.

The digital video signal converted into the block order from the blocking circuit 2 is supplied to the interpolation error detection circuit 17. The interpolation error detected by the interpolation error detection circuit 17 is supplied to the memory 18, and the memory 1B stores 16 blocks of one block.
pixel and the corresponding interpolation error are stored. In this case, since one basic pixel is always transmitted for each block, interpolation errors regarding other pixels may be detected and stored. The interpolation error read from the memory 18 is supplied to the gate signal generation circuit 19.

Information on the thinning rate generated by the thinning rate determining circuit 20 is supplied to the gate signal generating circuit 19 via a delay circuit 21 . The total delay amount (DLL+DL2
) is selected as (4LD-83D). The thinning rate determining circuit 20 determines the thinning rate according to the number of bits n.

The thinning rate (number of transmitted pixels divided by the number of pixels in one block) in the case of (n=1) is 1, the thinning rate in the case of (n=2) is expressed as %, and the thinning rate in the case of (n=3) is 1. The thinning rate is set to 1/3, and the thinning rate in the case of (n=4) is set to 174. In this example, the number of pixels in the block (1) is 16, so when the thinning rate is 173, the number of transmitted pixels is set to 5. Therefore, the total number of bits of the quantization code generated in one block is approximately constant (15 bits or 16 bits).

The gate signal generation circuit 19 generates a gate signal such that the number of pixel data specified by the above-described thinning rate and selected in order of decreasing interpolation error pass through the gate circuit 14.

Of course, when the thinning rate is 1, all pixel data in the block is transmitted via the gate circuit 14.

b. Interpolation error detection circuit An example of the interpolation error detection circuit 17 is shown in FIG.

Delay circuits 31 and 32 are connected to the input terminal 30 to which the digital video signal from the blocking circuit 2 is supplied.
．． 33.34.35.36.37.38.39.40.
41.42 are connected in series. Delay circuits 31 and 33
is a line delay circuit and has a delay amount for one line indicated by LD. The delay circuit 32 has a delay amount of 2LD.

The delay circuits 34 to 41 have a delay amount of the sampling period indicated by SD.The delay circuit 42 has a delay amount of 4SD.

FIG. 6 shows the arrangement of pixels in one block, where the horizontal pixel interval is a sampling period SD, and the vertical pixel interval is a line period LD. Within the block,
Pixel data is transmitted in the order of Sl, S2, S3, . . . S15, S16. The symbols (Δ, . . . , x, O) attached to each pixel in this (4×4)8 block represent differences in the interpolation processing performed on the receiving side.

As will be explained below, the interpolation error detection circuit 17 performs the same interpolation process as on the receiving side and detects the difference (interpolation error) between the pixel data and the true value.

First, a pixel S1 indicated by O represents a basic pixel located every 4 lines and every 4 pixels. 1 for each of these 16 pixels
A proportion of basic pixels are always transmitted without being thinned out.

Therefore, the interpolation error is naturally zero.

Pixels S5, S7, represented by Δ: are compared with the average value of pixel data located on the upper and lower lines, respectively.

It is compared with the average value of the pixels located on the lines two lines above and below the pixel S9 represented by .

Pixels S3 and S11 represented by the mouth: Compare with the average value of pixels located two pixels apart on the left and right.

Pixels represented by × S2, S6, S i 01S14, S
4, S8.312, S16: Compare with the average value of the pixels adjacent to the left and right.

Selectors 43 and 44, to which predetermined output signals of the delay circuits 31 to 42 are supplied to the first input terminal aO to the seventh input terminal a6, take out two pixel data used to calculate the interpolation value. It is provided for. Selector 43
and 44 are controlled by a selector control signal from the ROM 45. The ROM 45 is supplied with a sampling clock having a sampling period synchronized with the output signal of the blocking circuit 2 and a block clock having a block period from terminals 46 and 47.

FIG. 7 shows an example of the ROM 45, and 53 is the ROM 4
5 address counter. The ROM 45 stores 3-bit selector control signals corresponding to the respective positions of the pixels 31 to S16 of one block. However, the seventh
In the figure, for simplicity, (000) (001) (010)
・・・・・・3 bits of (110) are Oll, 2,
...It is shown as 6. When the selector control signal is 0, the selectors 43 and 44 selectively output the data supplied to the input terminal aO, and similarly, in accordance with the selector control signals 1 to 6, the selectors 43 and 44 output the data supplied to the input terminal aO. The data supplied to S6 from input terminal a1 is selectively output.

As can be seen from the selector control signal from the ROM 45 shown in FIG. 7, when each pixel in the block is the pixel of interest, that is,
When the data of the pixel of interest is generated on the output side of the delay circuit 37, these selectors 43 and 44 selectively output two pixel data for forming an interpolated value.

The two pixel data taken out from the selectors 43 and 44 are supplied to the adder circuit 48, the output signal of the adder circuit 48 is supplied to the A-multiplier circuit 49, and the A-multiplier circuit 49 outputs an interpolated value. This interpolated value is supplied to a subtraction circuit 50.

The data of the pixel of interest taken out from the connection point between the delay circuits 37 and 38 is supplied as the other input signal of the subtraction circuit 50. Therefore, a difference between the true value and the interpolated value is generated as an output signal of the subtraction circuit 50, and this difference is converted to the absolute value conversion circuit 51.
supplied to The interpolation error from the absolute value converting circuit 51 is taken out to an output terminal 52. This interpolation error is supplied to memory 18 as shown in FIG. 1, and the interpolation error for one block is stored in memory 18.

The two pixel data selected by the selectors 43 and 44 when each of the pixels 31 to S16 shown in FIG. 6 is the pixel of interest will be described below.

When the pixel S1 is the pixel of interest, a selector control signal of 0 is generated, and the selectors 43 and 44 selectively output the data of the pixel of interest that is being supplied from the output side of the delay circuit 37 to the input terminal aO. Pixel S1 is a basic pixel that is always transmitted, and the interpolation error is always zero.

When pixel S2 is the pixel of interest, a selector control signal of 1 is generated. The delay circuit 3 is connected to the input terminal a1 of the selector 43.
The data of the pixel S1 one sampling period (ISD) before from 8 is supplied, and the input terminal a1 of the selector 44
In this case, I is applied from the output side of the delay circuit 36 to the pixel S2.
Pixel S3 after SD is supplied. Therefore, the data of these two pixels Sl and S3 are sent to the selectors 43 and 4.
4, respectively.

When pixel S3 is the pixel of interest, selector control signal 2 is generated. The input terminal a2 of the selector 43 is supplied with the data of the pixel SL 2 SD before the pixel S3 from the delay circuit 39, and the input terminal a2 of the selector 44 is supplied with the data of the pixel SL 2 SD before the pixel S3.
On the other hand, the pixel S17 after 14SD is supplied from an intermediate stage of the delay circuit 33. That is, the delay circuit 34.3
5.36.37, a delay amount of 4SD is generated, and a delay amount of 103D is generated on the output side of the delay circuit 33 at an intermediate stage of the delay circuit 33. Therefore, the data of these two pixels S1 and S17 are sent to the selectors 43 and 44.
are selected respectively.

When pixel S4 is the pixel of interest, selector control signal 3 is generated. The delay circuit 3 is connected to the input terminal a3 of the selector 43.
The data of the pixel S3 before ISD from 8 is supplied, and the pixel 317 after 13SD is supplied to the input terminal a3 of the selector 44 from an intermediate stage of the delay circuit 33 with respect to the pixel S4. That is, delay circuits 34, 35, 36
．． 37, a delay amount of 4SD occurs, and the delay circuit 33
At an intermediate stage, 9SD is applied to the output side of the delay circuit 33.
amount of delay occurs. These two pixels S3 and 31
7 data are selected by selectors 43 and 44, respectively.

When pixel S5 is the pixel of interest, selector control signal 4 is generated. The delay circuit 4 is connected to the input terminal a4 of the selector 43.
The data of the pixel S1 4 SD before the pixel S5 is supplied to the input terminal a4 of the selector 44, and the pixel S9 after 4 SD from the pixel S5 is supplied from the output side of the delay circuit 33.

Therefore, the data of these two pixels S1 and S9 are selected by selectors 43 and 44, respectively.

When pixel S6 is the pixel of interest, a selector control signal of 1 is generated. The delay circuit 3 is connected to the input terminal a1 of the selector 43.
The data of the pixel S5 before ISD from 8 is supplied, and the pixel S7 after ISD is supplied to the input terminal a1 of the selector 44 with respect to the pixel S6. Therefore, the data of these two pixels S5 and S7 are selected by selectors 43 and 44, respectively.

When pixel S7 is the pixel of interest, selector control signal 4 is generated. The delay circuit 4 is connected to the input terminal a4 of the selector 43.
The data of the pixel S3 4SD before the pixel S7 is supplied to the input terminal a4 of the selector 44, and the pixel S11 after dSD is supplied from the output side of the delay circuit 33 to the input terminal a4 of the selector 44.

Therefore, the data of these two pixels S3 and Sll are selected by selectors 43 and 44, respectively.

When pixel S8 is the pixel of interest, selector control signal 3 is generated. The delay circuit 3 is connected to the input terminal a3 of the selector 43.
The data of the pixel S7 before ISD from pixel S8 is supplied to the input terminal a3 of the selector 44, and the pixel 321 after 13SD is supplied to the input terminal a3 of the selector 44 from an intermediate stage of the delay circuit 33. Therefore, these two pixels S7
and S21 are selected by selectors 43 and 44, respectively.

When pixel S9 is the pixel of interest, a selector control signal of 5 is generated. As shown in FIG. 5, the input terminal a5 of the selector 43 is supplied with the data of the pixel S1 8 SD before from the delay circuit 42, and the data of the pixel S1 after (4LD-83D) is supplied to the input terminal a5 of the selector 44. Data of pixel Si is supplied. In the block below the block shown in FIG. 6, the position of the pixel after 4LD from pixel S9 is pixel S9.
and a corresponding pixel (not shown). For this pixel, pixel St is pre-BSD. Delay circuit 31.32.
33 causes a delay amount of 4LD, and the delay circuit 3
4.35.36.37 causes a delay amount of 4SD. Therefore, the output signal from the position 123D relative to the input side of the delay circuit 31 is supplied to the input terminal a5 of the selector 44.

Selectors 43 and 44 select data of pixels S1 and Si, respectively.

When pixel S10 is the pixel of interest, a selector control signal of 1 is generated. The input terminal a1 of the selector 43 is supplied with the data of the pixel S9 before LSD from the delay circuit 38, and the input terminal a1 of the selector 440 is supplied with the data of 1. The pixel Sll after SD is supplied.

Therefore, the data of these two pixels S9 and Sll are selected by selectors 43 and 44, respectively.

When pixel Sll is the pixel of interest, selector control signal 2 is generated. The input terminal a2 of the selector 43 has the pixel 31
The data of the pixel S9 2 SD before 1 is supplied from the delay circuit 39, and the data of the pixel 325 after 1 dSD with respect to the pixel Sll is supplied to the input terminal a2 of the selector 44 from the delay circuit 39.
It has been supplied since the middle stage of 3. Therefore, the data of these two pixels S9 and 325 are selected by selectors 43 and 44, respectively.

When pixel S12 is the pixel of interest, selector control signal 3 is generated. The input terminal a3 of the selector 43 is supplied with the data of the pixel 311 before the LSD from the delay circuit 38, and the input terminal a3 of the selector 44 is supplied with the data of the pixel S25 after 13SD with respect to the pixel S12. It has been supplied since the middle of 33. Therefore, the data of these two pixels S11 and S25 are selected by selectors 43 and 44, respectively.

When pixel 313 is the pixel of interest, selector control signal 6 is generated. The input terminal a6 of the selector 43 is supplied with the data of the pixel S9 4SD before from the delay circuit 41, and the input terminal a6 of the selector 44 is supplied with the data of the pixel S9 (4LD-12S).
D) Data of the subsequent pixel Si is supplied. In the block below the block shown in FIG. 6, the position of the pixel after JLD is a pixel (not shown) corresponding to pixel S13.
It is. Pixel Si is 12 SD earlier than this pixel. The delay circuits 31, 32, and 33 generate a delay amount of 4LD, and the delay circuits 34, 35, 36, and 37 generate a delay amount of 4SD.

Therefore, the output signal from the position 163D relative to the input side of the delay circuit 31 is supplied to the input terminal a6 of the selector 44. The data of these pixels S9 and Si are selected by selectors 43 and 44, respectively.

When the pixel S14 is the pixel of interest, a selector control signal of 1 is generated. The input terminal a1 of the selector 43 is supplied with the data of the pixel S13 before LSD from the delay circuit 38, and the input terminal a1 of the selector 44 is supplied with the data of the pixel S15 after LSD for the pixel 314. ing. Therefore, the data of these two pixels S13 and S15 are selected by selectors 43 and 44, respectively.

When pixel S15 is the pixel of interest, selector control signal 6 is generated. The input terminal a6 of the selector 43 is supplied with the data of the pixel Sll 4SD before from the delay circuit 41, and the input terminal a6 of the selector 44 is supplied with the data of the pixel Sll (4LD-12).
3D) Data of the subsequent pixel Sk is supplied to the input side of the delay circuit 31 from a position of -16 SD. The data of these pixels Sll and Sk are selected by selectors 43 and 44, respectively.

When pixel S16 is the pixel of interest, selector control signal 3 is generated. The input terminal a3 of the selector 43 is supplied with the data of the pixel S15 before LSD from the delay circuit 38, and the input terminal a3 of the selector 44 is supplied with the data of the pixel S29 after 13SD with respect to the pixel S16. It has been supplied since the middle of 33. Therefore, the data of these two pixels S15 and S29 are selected by selectors 43 and 44, respectively.

C0 Modification According to the present invention, blocked data may be stored in a buffer memory, and data required for determining the interpolation error may be retrieved from the buffer memory.

Furthermore, the data after the minimum value has been removed from the subtraction circuit 7 or the quantization code DT from the quantization circuit 8 may be used to detect the interpolation error. Furthermore, an ADRC local decoder may be provided to detect interpolation errors from ADRC decoded values.

The interpolation method is not limited to the average value of two pixels, but may also use the average value of data of four surrounding pixels.

〔Effect of the invention〕

According to this invention, since subsampling that closely matches the characteristics of the image and ADRC that performs compression in the level direction are used together, the compression ratio can be increased. This invention changes the degree of thinning of subsampling according to the number of quantization bits of ADRC, so the amount of generated data can be controlled to be approximately constant, and the amount of generated data can be controlled to be approximately constant. It is effective when applied to a transmission path such as a VTR. Further, in the present invention, since the determination of transmission and thinning is made according to the magnitude of the interpolation error, the quality of the restored image can be improved.

[Brief explanation of the drawing]

Figure 1 is a block diagram of an embodiment of this invention, Figures 2 and 3 are route diagrams used to explain an example of blocks in this embodiment, and Figure 4 is a route diagram used to explain variable length quantization. 5 is a block diagram of an example of an interpolation error detection circuit,
FIG. 6 is a route diagram showing the arrangement of pixel data used to explain the interpolation process, and FIG. 7 is a block diagram showing the configuration for generating the selector control signal. Explanation of main symbols in the drawings 1: Input terminal, 2 Niblocking circuit, 3: Maximum value detection circuit, 4: Minimum value detection circuit, 8: Quantization circuit, 9: ROM for determining the number of bits. 14: Gate circuit. 17: Interpolation error detection circuit, 19: Gate signal generation circuit, 20: Thinning rate determination circuit.

Claims (1)

[Claims] A digital image signal is converted into a block structure formed by a plurality of pixels, a dynamic range within the block is detected, and a variable number of bits smaller than the original quantization bit number is determined according to the dynamic range. encoding means for allocating a quantization bit number to pixel data in the block and generating a quantization code; and regarding the plurality of pixels in the block;
interpolation error detection means that performs interpolation processing similar to that performed on the receiving side using a plurality of pixels around each pixel, and detects an error between the data obtained by the interpolation and the true value; means for determining a thinning rate according to the number of quantization bits of the encoding means; and with respect to the error in the block, selectively selecting a number of quantization codes corresponding to the thinning rate in order of decreasing error; 1. A high-efficiency encoding device for an image signal, comprising: means for outputting an image signal.