JPH02118641A - Margin pattern for mask - Google Patents

Abstract

PURPOSE:To prevent a bonding wire and a chip from being electrically short- circuited due to an Al film at the time of an assembly by making the length of the successive Al film to remain along a chip sidewall into a prescribed value or below. CONSTITUTION:When a removed part 5 of a dicing line 7 is machined by a dicing plate, the Al film of an alignment mark 3 forming material to remain along a chip sidewall 6 is also machined, and simultaneously, the Al film is made into a condition to be wound into the dicing plate and peeled. However, at the time of a division into chips, since the lengths of the Al film, etc., made to remain along the chip sidewall 6 is set so as to be 30mum or below, even when a part 54 of a remaining member made of the Al film, etc., is peeled, the bonding wire and chip can be prevented from being short-circuited through the Al film at the time of the assembly. Thus, the electric short-circuit cannot be caused.

Description

[Detailed Description of the Invention] [Summary] Regarding the margin pattern of a mask for preventing double exposure of alignment marks drawn on dicing lines of an exposure mask, the margin pattern remains along the sidewall of a chip during dicing. Even if the metal film that forms the margin pattern is turned over, the margin pattern is drawn on the dicing line of the exposure mask to prevent a short circuit between the bonding wire and the semiconductor chip through the metal film during assembly. In the margin pattern of a mask for preventing double exposure of the alignment mark, the exposure-shielding portion of the mask margin pattern overlaps the alignment mark when the mask is stamped and prevents the exposed portion of the alignment mark from being exposed. Although the margin pattern is sufficiently covered, the continuous length of the exposure shielding portion of the margin pattern that remains along the side wall of the chip when it is diced and divided into chips is 30 μm or less. Contains and composes.

[Industrial application field]

The present invention relates to the shape of a margin pattern of a mask for preventing double exposure of alignment marks drawn on dicing lines of an exposure mask.

In recent years, steppers have been introduced in order to cope with the increase in the diameter of wafers due to higher integration of semiconductor devices and larger chip sizes, and to improve pattern accuracy in the patterning process.

The mask pattern is transferred by this stepper to the wafer for each chip pattern or for each plurality of chip patterns. Generally, the dicing line at one end of the chip pattern on the mask is aligned so as to overlap the dicing line at the other end of the chip pattern transferred by the previous step/exposure. For this reason, the pattern on the scribe line is exposed to light in the previous step and exposure in the subsequent step.

By the way, alignment marks for positioning are usually provided on the dicing line, so even if the alignment marks are transferred in the previous step, they will be exposed again after the next step and will disappear. become.

Therefore, in order to prevent the alignment mark on the scribe line from being double exposed even if the scribe line is double exposed when the mask is stepped, a margin pattern is provided in the device that exposes the alignment mark when the mask is stepped. It is being

Next, a process for pattern exposure on a wafer using a stepper using a mask having alignment marks and margin patterns on the dicing lines at both ends will be briefly described.

FIG. 4 is a diagram showing a state where the chip pattern has already been transferred halfway to the positive photoresist 1 on the wafer 18, and the next chip pattern is about to be transferred. FIG. 3B is a partial perspective sectional view taken along line AA in FIG.

In the figure (a), 2a, 3a, and 4a are the main pattern, alignment mark, and margin pattern of the chip already transferred onto the wafer, respectively, and 7a is a dicing line. Further, 81 is a portion where the next pattern is transferred by the stent of the mask, and 61a is an overlapping portion where the already transferred alignment mark on the wafer and the margin pattern on the mask overlap. Note that 91 is an orientation flat of the wafer 18.

Further, in FIG. 4(b), 1 is a photomask, 2 is a main pattern formed on the photomask 1, 3 is an alignment mark formed in the dicing line 7 at one end of the photomask 1, and 4 is also a photomask 1. This is a margin pattern formed within the dicing line 7 at the other end.

Further, 3a is an alignment mark that has already been transferred to the positive photoresist 71 on the wafer 18 in the previous step, and is in a state where it is overlapped by the margin pattern 4 of the photomask 1.

When exposure is performed in this state, double exposure of the alignment mark 3a can be prevented by the margin pattern 4, so that the alignment mark remains as a pattern.

In this manner, the chip pattern is transferred to the entire wafer 18 by repeating the steps.

[Conventional technology]

Next, a conventional margin pattern will be described with reference to the drawings.

FIG. 5 is an enlarged top view for explaining the margin pattern of the conventional example. This shows a state in which the margin patterns inside overlap.

That is, in the figure, 113a is the exposed portion of the alignment mark formed inside the exposure shielding portion 123a of the alignment mark, and 124a is the exposure shielding portion of the margin pattern on the mask.

Further, 154 is the exposure shielding portion 12 of the margin pattern.
4a and the exposure shielding portion 123a of the alignment mark overlap, so even after double exposure, it remains as a pattern.
It is also a portion that remains along the side wall 106 of the chip when it is divided into chips. For example, when the pattern is formed of an AI film, the A1
A film will remain.

[Problem to be solved by the invention]

FIG. 6 is a partial cross-section showing a state in which a chip formed by such a conventional margin pattern is mounted on a mold resin.

In the figure, 108 is a chip, 109 is an extraction lead, and 110 is a ^U wire that electrically connects the bonding pad 112 on the chip and the extraction lead.

By the way, according to the conventional margin pattern, as shown in FIG. 6, the AI film in the portion 154 that is turned upward by the dicing blade during chip division and remains along the chip sidewall]06 is connected to the Au wire 110. Contact may cause an electrical short-circuit, resulting in failure of circuit elements inside the chip.

This is particularly likely to occur when the base of the ^l film is a silicon oxide film that does not have good adhesion to the AI film.

The present invention was created in view of the above-mentioned problems in the prior art, and has a margin pattern that prevents the bonding wire and the chip from causing electrical shorts due to the remains of the alignment pattern during assembly. It is intended for the purpose of providing.

[Means to solve the problem]

The above problem is that in the margin pattern of the mask to prevent double exposure of the alignment mark drawn on the dicing line of the exposure mask, the exposure shielding part of the margin pattern of the mask is A continuous length of the exposed shielded portion of the margin pattern that overlaps the alignment mark and sufficiently covers the exposed portion of the alignment mark, but that remains along the sidewalls of the chip when it is diced and divided into chips. This is achieved by a margin pattern characterized in that it is formed to have a thickness of 30 μm or less.

[For production]

According to the present invention, the length of the AI film, etc. that is generated due to the overlap between the exposure shielding portion of the margin pattern and the exposure shielding portion of the alignment mark, and that remains along the side wall of the chip when it is divided into chips. 30μ
Since it is set to be less than m, even if the remaining part consisting of one film etc. is turned over, the bonding wire and the chip will not be short-circuited through the AI film during assembly. Can be done.

〔Example〕

Hereinafter, the present invention will be specifically explained with reference to an illustrated embodiment.

FIGS. 1(a), 1(b), and 1(c) are illustrations of margin patterns according to an embodiment of the present invention.

In the same figure (a), 1 is a mask made of glass including a reticle or a working mask rotated from an original plate, 2
3 is an alignment mark for positioning, 4 is a margin pattern for preventing double exposure of the alignment mark, and 7 is a dicing line with a width of 15011 m.

FIG. 3C is a further enlarged view of the alignment mark 3, in which a cross-shaped exposed portion 13 is provided at the center of the exposed shielded portion 23. Here, the length of one side of the periphery of the exposure shielding portion 23 is 100 μm, the length of the exposed portion 13 is 90 μm both vertically and horizontally, and the width is 21 Im.

FIG. 2B is an enlarged view of the cross-shaped margin pattern 4 according to the embodiment of the present invention, and the length of the exposure shielding portion 24 is 100 μm in both the vertical and horizontal directions, and the width is 22 μm.
It is m.

Therefore, the cross-shaped margin pattern 4 according to the embodiment of the present invention shown in FIG. 4B and the alignment mark 3 shown in FIG.
When these are overlapped, the exposed portion 13 of the alignment mark 3 is exactly covered by the exposed shielding portion 23 of the margin pattern 4.

FIG. 2 is a top view showing a state in which the alignment mark and the margin pattern overlap, and the cross-shaped margin pattern 4 having the exposure shielding portion 24 drawn on the mask side is cut into a cross-shaped punching by the steps of the mask. It overlaps the alignment mark 3 having the exposed portion 13.

As a result, in the exposure process of the wafer process,
Since double exposure of the exposed portion 13 of the alignment mark 3 can be prevented, the alignment mark for positioning can be left on the wafer.

The shape of the alignment mark after patterning by chemical etching or the like is a cross-shaped margin pattern on the outside and a cross-shaped alignment mark on the inside. This alignment mark is used as a positioning mark in the next step.

When a predetermined wafer process is completed, the wafer is diced into chips along dicing lines 7 using, for example, a dicing blade. This dicing is performed by cutting the removed portion 5 shown in FIG. 2 with a dicing blade. The width of this removed portion 5 corresponds to the width of the dicing blade, and is approximately 60 μm.
It is m.

As a result, the length of the continuous portion (remaining portion 54) of the alignment mark ^l film remaining along the chip side wall 6 after dicing is approximately 10 μm.

By the way, when the removed portion 5 of the dicing line is cut with the dicing blade, the A1 film of the alignment mark forming material remaining along the chip side wall 6 is also cut, but at the same time, the A1 film is rolled up by the dicing blade and peeled off. be in a state of being Further, one end of the first film is pressed against the exposed St substrate of the chip side wall 6.

However, in the embodiment of the present invention, the length of the continuous portion of the AI film of the alignment mark remaining along the chip side wall 6 is about 10 μm, so the amount that is turned up is also extremely small. Therefore, when the chip is mounted in a package, the conventional problem of electrical short-circuiting between the bonding wire and the chip due to the rolled up AI film can be solved.

It is empirically known that if the continuous length of the AI film of the alignment mark remaining along the chip side wall 6 is 30 μm or less, the bonding wire and the chip will not be electrically short-circuited. The margin pattern satisfies this requirement.

Furthermore, even if there is some misalignment between the margin pattern and the alignment mark, according to the margin pattern of the embodiment of the present invention, the continuous length of the A1 film of the alignment mark remaining along the chip side wall 6 is 30 μm. Therefore, there is no chance of a short circuit caused by the rolled up film.

FIG. 3 is a top view of a margin pattern according to another embodiment of the present invention.

In the figure, 4a is a margin pattern, 24a is an exposure shielding portion of the margin pattern 4a, and 14a is an exposure portion provided within the exposure shielding portion 24a. According to the margin pattern having this shape, double exposure can be prevented by shielding the exposed portion 13 of the alignment mark 3 shown in FIG. 1(C). Note that 6a indicates the side wall of the chip after dicing.

Also, depending on the shape of this margin pattern, the length of the continuous residue 64 of the alignment mark of the AI film remaining along the chip side wall 6a can be reduced, and the length of the alignment mark can be easily reduced to 301! m
Since it is possible to do the following, the rolled up AI film will not cause a short circuit failure in the semiconductor element.

〔Effect of the invention〕

As described above, according to the margin pattern of the present invention, when the chip is divided into chips, the length of the continuous film remaining along the side wall of the chip can be reduced to 30 μm or less, so that during assembly. , it is possible to prevent electrical short-circuiting between the bonding wire and the chip due to this AI film.

Therefore, it is possible to improve the manufacturing yield of semiconductor devices.

Claims (1)

[Claims] In a margin pattern of a mask for preventing double exposure of an alignment mark drawn on a dicing line of an exposure mask, an exposure shielding portion of the margin pattern of the mask is arranged so that when the mask is stepped, A continuous portion of the exposed shielded portion of the margin pattern that overlaps the alignment mark and sufficiently covers the exposed portion of the alignment mark, but that remains along the sidewalls of the chip when it is diced and divided into chips. A margin pattern of a mask, characterized in that it is formed to have a length of 30 μm or less.