JPH02113548A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02113548A JPH02113548A JP26648788A JP26648788A JPH02113548A JP H02113548 A JPH02113548 A JP H02113548A JP 26648788 A JP26648788 A JP 26648788A JP 26648788 A JP26648788 A JP 26648788A JP H02113548 A JPH02113548 A JP H02113548A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- gate
- silicon substrate
- isolation
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000002955 isolation Methods 0.000 abstract description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 20
- 229910052710 silicon Inorganic materials 0.000 abstract description 20
- 239000010703 silicon Substances 0.000 abstract description 20
- 230000005684 electric field Effects 0.000 abstract description 10
- 230000000694 effects Effects 0.000 abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 3
- 229920005591 polysilicon Polymers 0.000 abstract description 3
- 238000000151 deposition Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 4
- 239000007864 aqueous solution Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- KWMLJOLKUYYJFJ-UHFFFAOYSA-N 2,3,4,5,6,7-Hexahydroxyheptanoic acid Chemical compound OCC(O)C(O)C(O)C(O)C(O)C(O)=O KWMLJOLKUYYJFJ-UHFFFAOYSA-N 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- 241000293849 Cordylanthus Species 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Landscapes
- Element Separation (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、牛導体装竹、特に電極配線膜構造に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a conductor mounting structure, particularly an electrode wiring film structure.
半導体装置において、素子間分離を行う場合、その分離
法としては、選択酸化法、いわゆる′Ｌ０００Ｂ（１，
＋ｏｏａｌｏｘＬムｔｉｏｎ Ｏｆ ａｉｌ工００ｎ）
’があり、従来より使われてきた。しかし、半導体装置
、特に半導体記憶装置の高集積化に伴い、′Ｌ０００８
法におけるバーズビークと呼ばれる素子形成領域への酸
化膜の侵食が問題になってきた。When performing isolation between elements in a semiconductor device, a selective oxidation method, so-called 'L000B(1,
+OOALOXL MUTION OF AIR WORK 00n)
' and has been used for a long time. However, with the increasing integration of semiconductor devices, especially semiconductor memory devices, 'L0008
In the process, erosion of the oxide film into the element formation region, called bird's beak, has become a problem.
その解決策の一つとしての素子間分離にトレンチ分離法
がある。このトレンチ分離法により製作した従来の半導
体記憶装置の平面図を第４図に示す。また第４図に示す
Ａ、Ａで切断した断面形状を第５図に示す。図にお−で
、（１）はトレンチ分離部及び分離酸化膜、（２）はゲ
ート電極、（３）はソース電極、（４）はドレイン電極
、（６）はシリコン基板、Ｃ５）はゲート酸化膜である
。この半導体記憶装置の製作は以下の手順で行われる。As one solution to this problem, there is a trench isolation method for isolation between elements. FIG. 4 shows a plan view of a conventional semiconductor memory device manufactured by this trench isolation method. Further, the cross-sectional shape taken along lines A and A shown in FIG. 4 is shown in FIG. In the figure, (1) is the trench isolation part and isolation oxide film, (2) is the gate electrode, (3) is the source electrode, (4) is the drain electrode, (6) is the silicon substrate, and C5) is the gate. It is an oxide film. This semiconductor memory device is manufactured in the following steps.
まず、シリコン基板（６）に素子分離の丸めの溝（トレ
ンチ）を形成する。First, a round groove (trench) for element isolation is formed in the silicon substrate (6).
次にその溝を酸化膜によシ埋め込み、トレンチ分離部及
び分離酸化膜（１）を形成する。次に素子形成領域に堆
積した不必要な酸化膜をドライエツチングや７ツ酸水溶
液などで除去し、新たにゲート酸化膜（５）を堆積させ
る。その上にポリシリコンを堆積させ、パターニングに
よシゲート電極（２）を形成させる。このような製作手
順に従い、理想的な半導体記憶装置ができると第６図の
ような断面構造を持つ。すなわち、情理めしたトレンチ
分離部及び分離酸化膜（１）と素子形成領域部は平坦に
なる。Next, the trench is filled with an oxide film to form a trench isolation portion and an isolation oxide film (1). Next, the unnecessary oxide film deposited in the element formation region is removed by dry etching or a heptonic acid aqueous solution, and a new gate oxide film (5) is deposited. Polysilicon is deposited thereon and patterned to form a gate electrode (2). If an ideal semiconductor memory device is manufactured according to such a manufacturing procedure, it will have a cross-sectional structure as shown in FIG. In other words, the trench isolation portion, the isolation oxide film (1), and the element forming region portion become flat.
しかしながら、実際は、素子分離のための溝を酸化膜で
情理めした後の７ツ酸水溶液などによる不必要な醗化膜
除失過程において過剰に酸化膜が除去され、トレンチ分
離部に急しゅんなシリコン基板（６）の角があられれる
ことになる。その角ができた場合の第４図のＡ−Ａにお
ける断面図は第６図になる。第６図中において、（１）
はトレンチ分離部及び分離酸化膜、（２）はゲート電極
、（５）はゲート酸化膜、（６）はシリコン基板、（７
）はトレンチ分離部にあられれたシリコン基板の急しゅ
んな角をあられす０
〔発明が解決しようとする課題〕
従来の半導体装置は以上のように構成されているので、
シリコン基板の急しゅんな角（７）が表われると、ゲー
ト電極（２）に電圧を印加した場合、シリコン基板の急
しゅんな角（７）に電界の集中が発生し、所望する反転
電圧よシ低いゲート電圧でシリコン基板の急しゅんな角
（７）付近で反転が生じ、半導体記憶装置の制御が困難
になるという問題点があつた。そのためにシリコン基板
の急しゅんな角（７）に発生する電界の集中を抑える必
要がある。However, in reality, after the trenches for element isolation have been covered with an oxide film, an excessive amount of oxide film is removed during the unnecessary process of removing the oxide film using an aqueous solution of chloride, resulting in sudden damage to the trench isolation area. The corners of the silicon substrate (6) will be rounded. When the corner is formed, the cross-sectional view taken along line A-A in FIG. 4 is shown in FIG. 6. In Figure 6, (1)
(2) is the gate electrode, (5) is the gate oxide film, (6) is the silicon substrate, (7) is the trench isolation part and the isolation oxide film, (2) is the gate electrode, (5) is the gate oxide film,
) is a sharp corner of the silicon substrate formed in the trench isolation part.
When a sharp corner (7) of the silicon substrate appears, when a voltage is applied to the gate electrode (2), an electric field will be concentrated at the sharp corner (7) of the silicon substrate, and the desired inversion voltage will be achieved. There is a problem in that a low gate voltage causes inversion near the sharp corner (7) of the silicon substrate, making it difficult to control the semiconductor memory device. For this purpose, it is necessary to suppress the concentration of electric fields generated at the sharp corners (7) of the silicon substrate.
この発明は上記のような問題点を解消するためになされ
たもので、シリコン基板の急しゅんな角（７）に発生す
る電界集中を緩和し安定な半導体記憶装置を得ることを
目的とする。The present invention has been made to solve the above-mentioned problems, and its purpose is to alleviate the electric field concentration generated at the sharp corners (7) of the silicon substrate and to obtain a stable semiconductor memory device.
（１１題を解決するための手段〕
この発明に係る半導体装置は、ゲート電極直下に、半導
体基板の段差を有する場合に、その段差に酸化膜のサイ
ドウオールを形成することにより、ゲート電圧印加時に
段差に発生する高電界の集中による反転電圧異常などを
防止するようにしたものである。(Means for Solving Problem 11) When the semiconductor device according to the present invention has a step in the semiconductor substrate directly below the gate electrode, by forming an oxide film sidewall on the step, the This is designed to prevent reverse voltage abnormalities caused by the concentration of high electric fields generated at the steps.
この発明における半導体基板に生じた段差に形成したサ
イドウオール酸化膜は、ゲート酸化膜が段差の急しゅん
な角に沿って配線されることを防止する効果を持つ。こ
のことによシ、ゲート電圧印加時に生じる半導体基板の
段差と、平たん部の電界分布の不均一性が解消され、信
頼性のある半導体記憶装置が得られる。The sidewall oxide film formed on the step formed in the semiconductor substrate according to the present invention has the effect of preventing the gate oxide film from being wired along the sharp corner of the step. This eliminates the step difference in the semiconductor substrate that occurs when applying the gate voltage and the non-uniformity of the electric field distribution in the flat portion, thereby providing a reliable semiconductor memory device.
以下、この発明の一実施例を図に従って説明する。第１
図は、この発明の一実施例による半導体記憶装置の平面
図、第２図は第１図に示すＢ、Ｂにおける断面図、第３
図（＆） （ｂ）は第２図に示す構造を製造する工程を
示す断面図である。図において（１）〜（７）は第４図
ないし％７図の従来例に示したものと同等であるので説
明を省略する０（８）はサイドウオール酸化膜を表わす
。An embodiment of the present invention will be described below with reference to the drawings. 1st
2 is a plan view of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view at B and B shown in FIG. 1, and FIG.
Figure (&) (b) is a sectional view showing the process of manufacturing the structure shown in Figure 2. In the figures, (1) to (7) are the same as those shown in the conventional examples shown in FIGS. 4 to 7, and the explanation thereof will be omitted. 0 (8) represents a sidewall oxide film.
次に第３図に示した製造フローについて述べる。Next, the manufacturing flow shown in FIG. 3 will be described.
まず第３図（＆）に示すようにシリコン基板（６）に異
方性エツチングによりトレンチ部を設け、トレンチ部を
酸化膜によシ埋め込み、トレンチ分離部及び分離酸化膜
（１）を形成する。次に素子形成領域部にある不必要な
酸化膜をフッ酸水溶液等で除去する。この段階でシリコ
ン基板の急しゅんな角（７）が現われる。そこで、第３
図（ｂ）に示すごとくシリコン基板の急しゅんな角（７
）にサイドウオール酸化ｊｌ（８）の形成を行う。そし
て、ゲート酸化膜（５）をた−積させ、ポリシリコンを
たい積させてゲート電極（２）を形成する。このように
ゲート電極（２）がシリコン基板（６）とトレンチ分離
部及び分離酸化膜（１）に存在する段差を横断する場合
、ゲート電極（２）に電圧が印加されると、この段差に
は、平たん部より大きさ高電界が生ずる。このため反転
電圧がゲート電極（２）の場所により異なり半導体記憶
装置の制御に困難をきたす。そこで、上記段差にサイド
ウオール酸化膜（８）を形成することにより、ゲート電
極（２）に電圧印加時に発生する電界分布を均一にする
ことにより、高信頼性のある半導体記憶装置を得ること
ができる。First, as shown in FIG. 3 (&), a trench portion is provided in the silicon substrate (6) by anisotropic etching, and the trench portion is buried in an oxide film to form a trench isolation portion and an isolation oxide film (1). . Next, unnecessary oxide films in the element formation region are removed using a hydrofluoric acid aqueous solution or the like. At this stage, sharp corners (7) of the silicon substrate appear. Therefore, the third
As shown in Figure (b), the sharp corner (7) of the silicon substrate
), sidewall oxidation jl (8) is formed. Then, a gate oxide film (5) is deposited and polysilicon is deposited to form a gate electrode (2). In this way, when the gate electrode (2) crosses the step between the silicon substrate (6), the trench isolation part, and the isolation oxide film (1), when a voltage is applied to the gate electrode (2), this step crosses the step. , a higher electric field is generated than in the flat part. Therefore, the inversion voltage varies depending on the location of the gate electrode (2), making it difficult to control the semiconductor memory device. Therefore, by forming a sidewall oxide film (8) on the step, the electric field distribution generated when voltage is applied to the gate electrode (2) is made uniform, and a highly reliable semiconductor memory device can be obtained. can.
なお、上記実施例では、シリコン基板（６）ニドレンチ
分離部及び分離酸化膜（１）を設けた場合を示したが、
多結晶シリコン基板にトレンチ分離部及び分離酸化膜（
１）を設けた場合に生じる段差に対してもサイドウオー
ル酸化膜（８）を設けてもよい。In addition, in the above embodiment, a case was shown in which a silicon substrate (6), a trench isolation part and an isolation oxide film (1) were provided.
Trench isolation part and isolation oxide film (
A sidewall oxide film (8) may also be provided for the step that occurs when step 1) is provided.
また、サイドウオール酸化Ｍ（８）の材料として酸化膜
の代りに窒化膜、でａ２０５膜を設けてもよい。Furthermore, the a205 film may be formed of a nitride film instead of the oxide film as the material for the sidewall oxide M(8).
以上のように、この発明によれば、ゲート電極直下に存
在するシリコン基板とトレンチ分離部及び分離酸化膜間
に生じる段差にサイドウオール酸化膜を形成したので、
ゲート電圧印加時に発生する電界を均一にでき、高信頼
性のある半導体記憶装置を得ることができる。As described above, according to the present invention, since the sidewall oxide film is formed on the step between the silicon substrate, the trench isolation portion, and the isolation oxide film that exists directly under the gate electrode,
The electric field generated when the gate voltage is applied can be made uniform, and a highly reliable semiconductor memory device can be obtained.
第１図はこの発明の一実施例による半導体記憶装置の平
面図、第２図は、第１図のＩＩ−Ｂにおける断面図、第
３図（ａ） Ｍ Ｃｂ）は第２図に示す構造を製造する
工程を示す断面図、第４図は、従来の半導体記憶装置の
平面図、第５図は、第４図のＡ、Ａにおける断面図、第
６図は、酸化膜が過剰に除去されたときの第４図のＡ、
Ａにおける断面図である。
図において、（１）はトレンチ分離部及び分離酸化膜、
（２）はゲート電極、（３）はソース電極、（４）はド
レイン電極、（５）はゲート酸化膜、（６）はシリコン
基板、（７）はシリコン基板の急しゅんな角、（８）は
サイドウオール激化膜を示す０
なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a plan view of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a sectional view taken along line II-B in FIG. 1, and FIG. 3 (a) M Cb) shows the structure shown in FIG. 4 is a plan view of a conventional semiconductor memory device, FIG. 5 is a sectional view taken at A and A in FIG. 4, and FIG. A in Figure 4 when
FIG. In the figure, (1) is a trench isolation part and an isolation oxide film,
(2) is the gate electrode, (3) is the source electrode, (4) is the drain electrode, (5) is the gate oxide film, (6) is the silicon substrate, (7) is the steep corner of the silicon substrate, (8 ) indicates a sidewall intensification film 0 In the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
面上において段差の下部領域と上部領域を分ける側壁部
分に絶縁膜のサイドウォールを形成し、その上から段差
部上を覆うゲート電極などの配線膜を形成することを特
徴とする半導体装置。A semiconductor substrate has a step on its surface, and on the surface having the step, an insulating film sidewall is formed on a side wall portion that separates a lower region and an upper region of the step, and a gate electrode or the like covers the step. 1. A semiconductor device comprising a wiring film formed thereon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26648788A JPH02113548A (en) | 1988-10-21 | 1988-10-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26648788A JPH02113548A (en) | 1988-10-21 | 1988-10-21 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02113548A true JPH02113548A (en) | 1990-04-25 |
Family
ID=17431615
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26648788A Pending JPH02113548A (en) | 1988-10-21 | 1988-10-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02113548A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990057300A (en) * | 1997-12-29 | 1999-07-15 | 김영환 | Trench formation method with improved leakage characteristics |
| US6239464B1 (en) | 1998-01-08 | 2001-05-29 | Kabushiki Kaisha Toshiba | Semiconductor gate trench with covered open ends |
| US6452246B1 (en) | 1999-07-16 | 2002-09-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having an improved isolation structure, and method of manufacturing the semiconductor device |
| JP2003513470A (en) * | 1999-11-02 | 2003-04-08 | インフィニオン テクノロジーズ ノース アメリカ コーポレイション | Spacer process to remove isolation trench corner transistor device |
| KR100451756B1 (en) * | 1998-08-24 | 2004-11-16 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60206150A (en) * | 1984-03-30 | 1985-10-17 | Toshiba Corp | Manufacture of semiconductor device |
| JPS63102339A (en) * | 1986-10-20 | 1988-05-07 | Matsushita Electronics Corp | Manufacture of semiconductor device |
-
1988
- 1988-10-21 JP JP26648788A patent/JPH02113548A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60206150A (en) * | 1984-03-30 | 1985-10-17 | Toshiba Corp | Manufacture of semiconductor device |
| JPS63102339A (en) * | 1986-10-20 | 1988-05-07 | Matsushita Electronics Corp | Manufacture of semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990057300A (en) * | 1997-12-29 | 1999-07-15 | 김영환 | Trench formation method with improved leakage characteristics |
| US6239464B1 (en) | 1998-01-08 | 2001-05-29 | Kabushiki Kaisha Toshiba | Semiconductor gate trench with covered open ends |
| KR100451756B1 (en) * | 1998-08-24 | 2004-11-16 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device the same |
| US6452246B1 (en) | 1999-07-16 | 2002-09-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having an improved isolation structure, and method of manufacturing the semiconductor device |
| US6855615B2 (en) | 1999-07-16 | 2005-02-15 | Renesas Technology Corp. | Method of manufacturing semiconductor device having an improved isolation structure |
| JP2003513470A (en) * | 1999-11-02 | 2003-04-08 | インフィニオン テクノロジーズ ノース アメリカ コーポレイション | Spacer process to remove isolation trench corner transistor device |
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