JPH02112384A - Picture signal compressing and encoding device - Google Patents

Abstract

PURPOSE:To reduce the capacity of a memory storing picture data after orthogonal transformation by compressing the orthogonally transformed picture data to picture data, which are composed of the set of data having a prescribed length, and after that, encoding the picture data. CONSTITUTION:A picture signal compressing and encoding device is equipped with an orthogonal transforming means 14 to execute the two-dimensional orthogonal transformation of digital picture data, data compressing means 16 and 18 to compress the picture data which are orthogonally transformed, a storing means 20, a reading control means 26 and an encoding means 22 to encode the picture data which are read from the storing means. A transformation coefficient, which is orthogonally transformed, is compressed, after that, stored to the storing means 20, read and encoded. Thus, the capacity of the storing means 20 can be reduced and the control of an address is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image signal compression encoding device, and in particular to an image signal compression encoding device that reduces the capacity of a memory for temporarily storing data after orthogonal transformation, particularly in two-dimensional orthogonal transformation encoding. related to conversion equipment.

11. When storing digital image data such as image data taken by an electronic still camera in memory, in order to reduce the amount of data and the storage capacity of the memory,
Various compression encoding methods are used. In particular, two-dimensional orthogonal transform encoding is widely used because it can perform encoding at a high compression rate and can also suppress image distortion caused by encoding.

The image data that has been subjected to such two-dimensional orthogonal transformation, that is, the transformation coefficients, is compared with a predetermined threshold value, and the portion below the threshold value is truncated (coefficient truncation). Quantization is performed according to the step width, and then encoding is performed. By the way, in transform coefficients that have been subjected to two-dimensional orthogonal transformation, that is, image data, low-order transform coefficients carry low frequency components of the image data before transformation, and this portion becomes important data in image reproduction. That is, when data in the low-order portion of the transform coefficients deteriorates, the quality of the reproduced image signal deteriorates.

Therefore, for example, in an image signal processing system where data transmission or storage is stopped at a single data amount, image data that has undergone two-dimensional orthogonal transformation is encoded sequentially from low-order transform coefficients to high-order transform coefficients. A method is used in which the data is transmitted or stored, and the encoding and transmission or storage are terminated when a predetermined amount of data is reached.

Such encoding reduces O as the transform coefficients become higher order.
Since this is often the case, the length of the O value data is 0.
This is done by finding the run length, non-zero data value, and non-zero amplitude, and then Huffman encoding them.

Conventionally, in order to encode image data that has been subjected to two-dimensional orthogonal transformation for each block, a buffer memory is used to temporarily store one screen's worth of image data that has been subjected to two-dimensional orthogonal transformation. That is, one screen's worth of image data that has been subjected to two-dimensional orthogonal transformation for each block is stored in a buffer memory, and this data is read out in order from the low-frequency data of each block to find the run length of 0 and the amplitude of non-zero. , this was Huffman encoded and then transmitted or stored. Since a buffer memory is required to store one screen worth of image data that has been divided into blocks and converted in this way, there is a drawback that the circuit size increases. Furthermore, address control when reading from the buffer memory is troublesome because the amount of address data increases.1-Plastic The present invention eliminates the drawbacks of the prior art and provides a memory for storing image data after orthogonal transformation. An object of the present invention is to provide an image signal compression encoding device that can reduce the capacity of the image signal.

According to the present invention, an image signal compression encoding device that divides digital image data constituting one screen into a plurality of blocks and performs two-dimensional orthogonal transform encoding on the image data of each block is configured to orthogonal transformation means for two-dimensional orthogonal transformation of digital image data divided into blocks; and data compression for compressing the image data orthogonally transformed by the orthogonal transformation means into image data constituted by a set of data of a predetermined length. storage means for storing the image data compressed by the data compression means; readout control means for controlling the image data stored in the storage means to be read out in order from lower order data; and reading control means for reading out the image data from the storage means. and an encoding means for encoding the image data compressed by the data compression means and read using a relative address corresponding to the number of image data for each block stored in the storage means. It controls addresses.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of an image signal compression encoding apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows an embodiment of an image signal compression encoding device according to the present invention.

The device has a frame buffer 12. Still image data for one frame captured by an electronic still camera is input to the frame buffer 12 through an input terminal IO and is stored therein. The image data stored in the frame buffer 12 is divided into a plurality of blocks, read out block by block, and sent to the two-dimensional orthogonal transformation section 14. The two-dimensional orthogonal transform unit 14 performs two-dimensional orthogonal transform on the image data for each block. As the two-dimensional orthogonal transformation, well-known orthogonal transformations such as discrete cosine transformation and Hadamard transformation are used.

The image data for each block that has been subjected to two-dimensional orthogonal transformation in the two-dimensional orthogonal transformation unit 14 is arranged vertically and horizontally as shown in FIG. The following data will be obtained. The output of the two-dimensional orthogonal transform section 14 is sent to the quantization section 1B.

The quantization unit 16 performs coefficient truncation and quantization on the image data subjected to the two-dimensional orthogonal transformation in the two-dimensional orthogonal transformation unit 14, that is, the number of transformed io1s. Coefficient truncation is performed by comparing orthogonally transformed image data with a predetermined threshold,
The part below the threshold value is discarded. Quantization is performed by dividing the image data whose coefficients have been truncated by a predetermined quantization step value, and performing quantization based on the step width.

The output of the quantization section 16 is sent to the run length amplitude encoding section 18.
sent to. The run length amplitude encoding section 18 encodes the O run length and non-zero amplitude of the quantized image data sent from the quantization section 1B. That is,
The quantized image data is processed in a zigzag manner from low-order parts to high-order parts as shown in Figure 4, and the run length of 0 and non-zero amplitude are set as shown in Figure 5. The quantized image data that is encoded takes a value other than O in the low-order part, but the high-order part takes a
When read out in a zigzag pattern as shown in the figure, O's often follow. Therefore, each quantized image de-
Since it is inefficient to perform Huffman encoding of all data as it is, which will be described later, we calculate the length of O, that is, the run length of O, and calculate the value of non-O data that appears after that, that is, the non-zero amplitude. The data is encoded as one set as shown in FIG. As shown in the figure, for example, the run length of O is 6 bits, the non-zero amplitude is 3 bits, and the level within each non-zero amplitude range is 7 bits, for a total of I
It is represented by B bits and is one set of data.

The data encoded as shown in FIG. 5 by the run-length amplitude encoder 18 is sent to the frame buffer 20. The frame buffer 20 is a buffer that stores one frame of image data input from the run-length amplitude encoder 18. An example of data stored in the frame buffer 20 is shown in FIG. 6. In the example shown in FIG.
5, the data of block 2 is stored from address 1B to address 27, and the data of block 3 is stored from address 28 to address 38, respectively. this is,
Run-length amplitude encoder! This is because when processed in 8, there were 16 non-zero data in block l, 12 in block 2, and 11 in block 3, and these non-zero data each have a run length of O. It is stored in one address as one set of data (16 bits).

Therefore, the value of data stored in the frame buffer 20 changes depending on the number of non-zero data in each block. In other words, if a lot of O data appears in each block and the run length of 0 is long, this part will be compressed and combined with non-zero data to form one set of data as shown in Figure 5. The amount of data stored in frame buffer 20 is reduced.

A read/write controller 26 is connected to the frame buffer 20, and an address generator 30 is connected to the read/write controller 26. As shown in FIG. 2, the address generation section 30 includes a pointer memory 32. It has an adder 34 and an incrementer 36. The pointer memory 32 is constituted by a ring counter, and as shown in FIG. 7, data corresponding to the number of data for each block stored in the frame buffer 20 is stored. That is, since the data stored in the frame buffer 20 as shown in FIG. Data 1612.11 is stored. Such address data stored in the pointer memory 32 is, for example, 6 bits.

The output of pointer memory 32 is input to one input of adder 34. Further, the output of the pointer memory 32 is input to the incrementer 3B. The incrementer 36 adds 1 to the value of the data stored in the pointer memory 32 and stores the value in the pointer memory 32 again.

Address data indicating the real address of the frame buffer 20 is outputted from the output of the adder 34 as will be described later, and is sent to the frame buffer 20 through the read/write control section 26.
At the same time, this address data is sent to the adder 34.
is input as the other input.

When a set of O run lengths and non-zero data constituting each block is input to the frame buffer 20, data corresponding to the number of these data in each block, that is, the number of non-zero data, is read/written. For example, as shown in FIG. 7, tl! is input to the pointer memory 32 through the control unit 26 and written in the frame buffer 20. Data according to the number of data per block, 18.12.11...
. is stored in the pointer memory 32.

When reading data from the frame buffer 20, the read/write control unit 26 first specifies address 0 and reads the first data of the first block stored at address 0 of the frame buffer 20. The above data [6] is read out from the pointer memory 32 and sent to the adder 34. The above address O is input to the other input of the adder 34, and added to the data 16 in the adder 34, and the added value 18 is sent to the frame buffer 20 through the read/write controller 26 as the next address.
is output to.

As a result, the first data of the second block written at address 16 of the frame buffer 20 is read out. Furthermore, the next data 12 is read from the pointer memory 32 and sent to the adder 34. Adder 34
The address 16 mentioned above is input to the other input of the adder 34, and is added to the data 12, and the added value 28 is output as the next address to the frame buffer 20 through the 1 read/write controller 28. Ru. As a result, the first data of the third block stored at address 28 of frame buffer 20 is read.

Similarly, data 11 is read from the pointer memory 32, and the first data of the fourth block stored at address 38 of the frame buffer 20 is read.

On the other hand, each time the first data of each block stored in the frame buffer 20 is read, the incrementer 36
adds 1 to the value of the data stored in the pointer memory 32, and stores this value in the pointer memory 32 again. After all the first data of each block stored in the frame buffer 20 is read out, the read/write control unit 2
6 indicates the value of each block stored in the frame buffer 20 based on the value of the data stored in the pointer memory 32.
Read the th data, i.e. pointer memory 3
Data 1 is obtained by adding 1 to the data stored in 2.
17, 29, 40, . . . are read out. First, 1 is read, and the second data of the 111i-th block is read. 0, then 17 is read, and the second data of the second block is read. Furthermore, 29 is read out, and the second data of the third block is read out. The second data of each block is read out in the same manner.

When the second data of each block is read, the 37th If and subsequent data of each block are read in the same way.

In this way, the data constituting each block is read out in order from the lowest order data.

The data read out from the frame buffer 20 in this manner is sent to the Huffman encoding section 22 and subjected to Huffman encoding. The output from the Huffman encoder 22 is output from the output terminal 2.
4 and stored in a storage medium such as a memory. The output from the Huffman encoding section 22 is also sent to the transmission bit number accumulating section 2B. The output of the sending bit number accumulating section 2 is connected to the read/write control section 2B. The transmission bit number accumulation unit 28 accumulates the number of bits of data output from the Huffman encoding unit 22, and when a predetermined number of bits is reached, outputs an output to that effect to the read/write control unit 26.

Accordingly, the read/write control unit 2B stops advancing address 20 to the frame buffer, and
Reading data from 0 is stopped. therefore,
Since the data read from the frame buffer 20 is stopped at a predetermined number of bits, the data output to the output terminal 24 can be stopped at a predetermined amount.

According to this embodiment, as described above, the image data is subjected to two-dimensional orthogonal transformation, and after storing the zero run length and non-zero data of the transformed transformation coefficients in the frame buffer 2G, the read address is controlled. The stored data of each block is read out. Conventionally, the converted transform coefficients are stored in a frame buffer as they are without being converted into run lengths of 0 and non-zero data, and then read out and converted into run lengths of 0 and non-zero data. On the other hand, in this embodiment, the converted conversion coefficients are stored in the frame buffer 2o as run lengths of 0 and non-zero data, so the capacity of the frame buffer 20 can be reduced.

Furthermore, since the address for reading data from the frame buffer 20 uses the data stored in the pointer memory 32 as a relative address, address data can be easily generated and address processing can be performed easily.

Furthermore, even if the number of data constituting each block stored in the frame buffer 20 is different, reading is stopped when a predetermined number is reached from the lower order data, so the same number of data from each block is read out from the lower order data. It is possible to sequentially read and encode the data.

Effects According to the present invention, after the orthogonally transformed transform coefficients are compressed, they are stored in the storage means, and are read and encoded. Therefore, the capacity of the storage means can be reduced compared to the case where the orthogonally transformed transformation coefficients are stored as they are in the storage means.

In addition, since the readout address is controlled using a relative address according to the number of image data for each block compressed and stored in the storage means, it is possible to reduce the amount of data used to generate the address, and control the address. is easy.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an image signal compression encoding device according to the present invention. FIG. 2 is a block diagram showing the address generation section of FIG. 1. Figure 3 shows an example of image data for each block that has been subjected to two-dimensional orthogonal transformation. Figure 4 shows the order in which run lengths and non-zero amplitudes are encoded. Figure 7 shows an example of data stored in the frame buffer of Figure 1. Figure 7 shows an example of data encoded with non-zero amplitude. FIG. 3 is a diagram showing an example of data stored in a memory. Explanation of some issues 14... Two-dimensional orthogonal transform unit 1B, Quantization unit 18, Run-length amplitude encoding unit 20, Frame buffer 22, Huffman encoding unit 2B, Read/Write control unit 30, Address Generation part tail 3 Figure '#-, 4 Figure book 5 Figure tail 6 Wahozu

Claims (1)

[Claims] 1. An image signal compression encoding device that divides digital image data constituting one screen into a plurality of blocks and performs two-dimensional orthogonal transform encoding on the image data of each block, the device comprising: , orthogonal transformation means for two-dimensional orthogonal transformation of the digital image data divided into the plurality of blocks, and image data constituted by a set of data of a predetermined length from the image data orthogonally transformed by the orthogonal transformation means. a data compression means for compressing the image data into a data compression means; a storage means for storing the image data compressed by the data compression means; and a readout control means for controlling the image data stored in the storage means to be read out in order from lower order data. and encoding means for encoding the image data read from the storage means, the readout control means compressing the image data for each block compressed by the data compression means and stored in the storage means. An image signal compression encoding device characterized in that a read address is controlled using a relative address according to the number of data. 2. The apparatus according to claim 1, wherein the read control means includes a relative address storage means for storing the relative address, and an increment means for incrementing the relative address stored in the relative address storage means, Each time the image data for each block stored in the storage means is read out one by one from the blocks using the relative address read from the relative address storage means, the relative address stored in the relative address storage means is An image signal compression encoding device characterized in that the image data is read out in order from the lower-order image data of the block by incrementing the image data by the incrementing means.