JPH02111826U - - Google Patents
Info
- Publication number
- JPH02111826U JPH02111826U JP2079989U JP2079989U JPH02111826U JP H02111826 U JPH02111826 U JP H02111826U JP 2079989 U JP2079989 U JP 2079989U JP 2079989 U JP2079989 U JP 2079989U JP H02111826 U JPH02111826 U JP H02111826U
- Authority
- JP
- Japan
- Prior art keywords
- clock signal
- frequency
- oscillation circuit
- circuit
- microprocessor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Description
第１図は本考案の一実施例の要部ブロツク図お
よび、第２図は従来のマイクロプロセツサの要部
ブロツク図である。
図において、１，１′…マイクロプロセツサ、
１ｃ…基準周波数のクロツク信号が導かれる出力
端子、２…水晶振動子、３…発振回路、４…バツ
フアアンプ、５…分周回路、６…内部クロツク信
号、７…クロツク信号、８，９…発振安定用のコ
ンデンサ、１０…分周出力。
FIG. 1 is a block diagram of the main part of an embodiment of the present invention, and FIG. 2 is a block diagram of the main part of a conventional microprocessor. In the figure, 1, 1'...microprocessor,
1c... Output terminal to which a reference frequency clock signal is guided, 2... Crystal resonator, 3... Oscillation circuit, 4... Buffer amplifier, 5... Frequency dividing circuit, 6... Internal clock signal, 7... Clock signal, 8, 9... Oscillation. Stabilizing capacitor, 10...divided output.
Claims (1)
クロツク信号を発生する発振回路と、該発振回路
で発生されたクロツク信号を分周して内部クロツ
ク信号を生成する分周回路とを内蔵するマイクロ
プロセツサにおいて、 前記発振回路と前記分周回路との間に設けられ
たバツフアアンプと、 該バツフアアンプから取り出された前記基準周
波数のクロツク信号が導かれる出力端子とを具備
したことを特徴とするマイクロプロセツサ。[Claims for Utility Model Registration] An oscillation circuit that generates a reference frequency clock signal according to an externally attached crystal resonator, and an internal clock signal that is generated by dividing the frequency of the clock signal generated by the oscillation circuit. A microprocessor with a built-in frequency dividing circuit, comprising a buffer amplifier provided between the oscillation circuit and the frequency dividing circuit, and an output terminal to which a clock signal of the reference frequency extracted from the buffer amplifier is guided. A microprocessor characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2079989U JPH02111826U (en) | 1989-02-23 | 1989-02-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2079989U JPH02111826U (en) | 1989-02-23 | 1989-02-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02111826U true JPH02111826U (en) | 1990-09-06 |
Family
ID=31237470
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2079989U Pending JPH02111826U (en) | 1989-02-23 | 1989-02-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02111826U (en) |
-
1989
- 1989-02-23 JP JP2079989U patent/JPH02111826U/ja active Pending
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