JPH02110751A - Information processing system - Google Patents

Abstract

PURPOSE:To facilitate the control of cache hit information and to maintain the high speed of the access to a cache memory by extending the duty ration of a system clock given to a processor at the time of writing from the processor to the cache memory. CONSTITUTION:The title system is composed of a CPU 1, a cache hit information preparing part 2, a clock control part 3, a cache hit information control part 4, and a cache control part 5. The CPU 1 extends the timing to sample the cache hit information at the time of writing a memory by correcting the duty ration of a sampling clock. Thus, the allowance occurs at the timing to control forcibly the cache hit information to the cache error condition, the control is easily executed and the high speed of the access to the memory is not damaged.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing system, and more particularly to a control method for performing retry processing of the access upon receiving cache hit information when a processor accesses a cache memory. It is.

A high-speed cache memory that stores a partial copy of data in the main storage device is provided, and when a processor performs a memory read, it is determined whether or not a target data copy exists in the cache memory. If the data exists (if it is cached), the target data copy is read from this high-speed cache memory, thereby speeding up memory access.

At this time, if the desired data copy does not exist in the cache memory (if it is a cache miss), the processor is made to perform a retry operation, and for this purpose the processor is sent cache hit information (cache (Information about mistakes) must be notified. In this case, when writing from the processor to the cache memory, the processor only needs to perform processing to write write data to the write buffer, so there is no need for the processor to perform retry processing.

Therefore, if a cache miss occurs when writing from the processor to the cache memory, it is necessary to make it appear as if a cache hit has occurred to the processor, and to accurately notify the cache memory control unit of the cache hit information (this (If there is a cache miss, it is necessary to notify the cache memory control unit that there is a cache miss.) Therefore, by controlling the cache hit information, when writing from the processor to the cache memory, the cache memory control unit is notified that there is a cache miss. must accurately report the catch information and make it appear to the processor that the catch has been made. Therefore, in the prior art, there are methods such as inserting a logic circuit between the processor and the cache hit information generating section, or forcing the cache hit information to be in the hit state at the time when the processor determines whether or not to retry. .

The disadvantage of the method of inserting a logic circuit between the processor and the cache information generator is that the notification of cache information to the processor is delayed by the operating time of this logic circuit, which slows down the processor's ability to access the cache memory. There is.

Furthermore, in the method of controlling the cache hit information to a forced hit state at the time when the processor determines whether or not to retry, it becomes difficult to control the output of the cache hit information as the processor becomes faster.

Therefore, the present invention was made to solve the drawbacks of the conventional ones, and its purpose is to facilitate the control of cache information and to improve access to cache memory. An object of the present invention is to provide an information processing system that maintains high speed.

According to the present invention, a cache memory that stores a copy of a portion of data in the main storage device, and a cache memory that determines whether or not a copy of the target data exists in the cache memory, and performs the cache memory. A cash hit information generation means for generating information; and a processor that samples the cash hit information at every predetermined level transition timing of a system clock and retries the previous cycle operation again when this information indicates a cache miss. An information processing system comprising: a clock duty ratio correction means for extending a duty ratio of a system clock applied to the processor when writing from the processor to the cache memory; It will be done.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a system block diagram showing an embodiment of the present invention. A processor (hereinafter referred to as CPU) 1 includes an instruction pipe 11 that decodes instructions, a microsequencer and controller 2 that executes microprograms, generates control signals, etc. according to the instructions, and an execution unit that executes arithmetic processing. 13, a bus controller 14 for controlling data buses, address buses, and bus control signals, and a DFF (D type flip-flop) 15 for sampling cash hit information 107.

The cache information generating section 2 includes an address array (address array) 21 for storing addresses indicating the location of data copies in a main memory (not shown), and an address bus 1.
A comparator 22 detects whether or not the access address of No. 10 matches the address in the address array 21, and the output of this comparator is used as cash hit information 107.
The OR gate 23 is derived as follows.

The clock control unit 3 includes a clock generation unit 31 that generates a basic clock 101 of the system that determines the operation of the CPUI, and a DFF 32.3 circuit that is provided to generate a correction signal 102 that corrects the duty ratio of this basic clock 101. ANDGATE, 2-person ORGATE 33. The output 105 of this clock control section 3 serves as the clock input of the DFF 15 for sampling the cash hit information 107.

The cache hit information control unit 4 stores this information 1 at the time when the CPU 1 samples the cash hit information 107.
It generates a cash hit information control signal 106 that controls the driver 07 to be in a forced hit state, and is made up of three-person catch gates 41 and 42 and a two-person catch gate 43.

The cache control section 5 has a function of controlling a cache memory (not shown), the cash hit information generation section 2, and the cash hit information control section 4, and generates the following control signals. In other words, the write buffer busy signal (WBBS) indicates that the write buffer for temporarily storing data to be written from the CPU to the main memory is in use.
Y) 111, a block busy signal (BLBSY) 112 indicating that a block is being loaded, a reset signal 113 for the address array 21, a data write signal 114 to the address array 21, and a signal indicating cache access. (810) and 115, respectively.

Note that an address strobe signal 116 and a read/write signal 117 are generated from the bus controller 14 of the CPUI.

First, the basic operation of the CPUI will be explained using the operation timing chart of the signals of each part shown in FIG.

When the cpui accesses memory, address bus 1
An address is generated on 10 and is established in state SO. A read/write signal 117 indicating whether this access is a read or a write is generated, and this is determined in state SO. Note that when this signal 117 is at a high level, it indicates a read cycle, and when it is at a low level, it indicates a write cycle.

Also, an address strobe signal 116 is generated indicating that a valid address is present on the address bus 110 and is asserted during state S1 and is asserted during state S3.
is negated. Note that the acknowledge signal is sent from the outside by C.
This is a signal given to the PU, and is a so-called handshake signal indicating completion of data transfer. When the address strobe signal 116 becomes low level and a predetermined cycle (read or write cycle) begins, the CPUI samples the acknowledge signal at the rising timing of the clock 101, and if it is low level, the cycle is ended, and when it goes high If so, insert a wait (SW) and continue waiting until the acknowledge signal is returned (becomes low level).

Next, the retry cycle of the CPU 1 will be explained using the time chart shown in FIG. When the address strobe signal 116 becomes low level and a read cycle begins, the CPU samples the cash hit information 107 using the DFF 15 at the falling timing of the clock, and if this hit information is determined to be low level (miss hit), After the current read cycle is completed, the same read cycle is repeated again.

Here, as described above, in the case of a write cycle, even if a cache miss occurs, the CPUI does not need to retry. In CPtJl, the cash hit information 107 is sampled at the falling timing of state S2 in the retry cycle shown in FIG. 3, but in the present invention, as shown in FIG. Downhill (point A),
The time is delayed by two states and extended to point B, and the hit information 107 is controlled to be forced into the hit state during the extended time.

In order to extend the sampling timing for the CPU to identify this cash hit information 107, the duty ratio of the clock 105 of the sampling DFF 15 is controlled by the clock control unit 3. FIG. 6 is a truth table showing the operation of the clock control section 3, and FIGS. 7 and 8 show the operation time charts. In FIG. 6, X indicates indeterminacy, and an upward arrow indicates the rising timing of the clock 101.

In this way, CPtJl receives information 10
7 is extended by controlling the duty ratio of the sampling clock 105, and during this extended time, the cash hit information control section 4 controls the cash hit information 107 to be a forced hit.

A truth table showing the operation of this cash hit information control section 4 is shown in FIG. 9, and a block busy signal (BLBS'/
) 112, clocks 101, 105 . Address strobe signal 116. The relationship with the read/write signal 117 is shown in the time chart of FIG.

The relationship between the hit information control signal 106 obtained by this circuit 4 and the duty ratio corrected clock 105 obtained by the clock control section 3 is shown in the time chart of FIG.

As shown in FIG. 4, the catch information 107 is as follows:
Tp61 hours after address confirmation, that is, after the cash hit information control signal becomes low level, Tpd
It will be confirmed after 2. Here, in the cache control unit 5, since the cash hit information is sampled at the point A, this hit information is controlled so that the determination of the cash hit information for the point A satisfies the set-up time Tsu1. In addition, in the CPUI, since this human information is sampled at point B, it is necessary to
It controls the hit information so that it is at a high level, and prevents the CPU from entering a retry during a write cycle.

FIG. 5 is an operation time chart in the conventional technology,
Since the sampling timing of the catch hit information in the CPUI is not extended to the same extent, the control timing for forcibly controlling the catch hit information to a high level needs to be earlier than in the present invention, making control difficult. .

As shown in Fig. 1 and Fig. 1, according to the present invention, the timing at which the CPU samples cash hit information at the time of memory write is extended by correcting the duty ratio of the sampling clock. This has the effect that there is a margin in the timing for forcibly controlling the cache miss state, making the control easier, and that the high speed of access to the memory is not impaired in any way.

[Brief explanation of drawings]

Fig. 1 is a system block diagram of an embodiment of the present invention, Fig. 2 is a time chart showing the basic operation of the CPU, and Fig. 3 is a C
A time chart showing the retry operation of the PU, Figure 4 is the first
Fig. 5 is a time chart showing the operation of the conventional technology, Fig. 6 is a truth table showing the operation of the clock control section, and Figs. 7 and 8 are the operation of the clock control section. FIG. 9 is a time chart showing the clock duty correction operation, FIG. 9 is a truth table showing the operation of the hit information control section, and FIG. 10 is a time chart 1 showing the relationship of signals used in the hit information control section. Explanation of symbols of main parts 1...CPU 2...Cache information generation unit 3...
... Clock control section 4 ... Clock information control section 5 ...
・Cache control section

Claims (1)

[Claims] (1) A cache memory that stores a partial copy of data in the main storage device, and cache hit information that determines whether a copy of the target data exists in this cache memory and generates cache hit information. An information processing system comprising: a generating means; and a processor that samples the cache hit information at every predetermined level transition timing of a system clock and retries the previous cycle operation again when this information indicates a cache miss. An information processing system further comprising clock duty ratio correction means for extending the duty ratio of a system clock applied to the processor when writing from the processor to the cache memory.