JPH02110735A - List data processor - Google Patents

Abstract

PURPOSE:To improve the list processing efficiency by processing list data with the construction displayed by a connecting cell arranged two-dimensionally and an atomic cell arranged one-dimensionally. CONSTITUTION:The internal expression of the list data handled by an arithmetic unit 10 is realized by the data construction composed of connecting cells C11 to Cnm to store the connection information of a list and atomic cells A1 to An to store the information of the leaf of the list, namely, the referring information to a data substance called 'atom'. The connecting cells C11 to Cnm are two-dimensionally arranged to the depth direction (X direction) of a list and the number direction (Y direction) of a list element and this is made into a cell matrix memory 17. The atomic cells A1 to An are one-dimensionally arranged in the number direction of the list element and this is made into an atomic memory 18. Thus, the list data can be efficiently processed and the high speed operation can be executed.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a list data processing device that processes list-structured data used in the fields of knowledge information processing systems and artificial intelligence (AI).

The purpose is to provide a device that efficiently processes list data and enables high-speed calculation, and a memory that stores list data includes a connection cell that stores list connection information;
It consists of an atom cell that stores the information of the leaves of the list.
The connection cells are arranged two-dimensionally in the depth direction of the list and the number of list elements, and the atom cells are arranged two-dimensionally in the depth direction of the list and the number direction of list elements.

It is configured to be arranged one-dimensionally in the direction of the number of list elements.

[Industrial application field]

The present invention is a knowledge information processing system and an artificial intelligence (AI) system.
The present invention relates to a list data processing device that efficiently processes list-structured data often used in the field of

For example, list data processing is actively performed in fields such as machine translation systems, natural language analysis software, knowledge base systems, knowledge information processing systems such as graphic editors, and AI. This is because the data structure of list data is flexible, it is possible to express data in complex forms, and it is easy to add and delete data. It is expected that the scope of use of list data will continue to expand in the future, and a means that enables efficient handling of list data is desired.

[Conventional technology]

FIGS. 10 and 11 show examples of list data storage structures according to the conventional method.

In the conventional method, when an element of a list is expressed in a computer system, it is expressed using a pair of address ADI and address AD2, as shown in FIG. It was designed to point to data entities called elements or atoms. Note that F in Figure 3 is a flag indicating the type of data, etc.

For example, when storing list data r(A (X Y) B) J as shown in Figure 10 (B) in the memory of a computer, it is stored in the structure shown in Figure 10 (C). do.

Here, the address used as the pointer is 2. In a normal computer, about 4 bytes are used. Therefore, each element of the list requires about 8 to 9 bytes, including flag information. As the scale of the problem to be solved by a computer becomes larger, a larger memory for storing list data is also required.

As VLSI memory technology advances, the cost of increasing memory capacity tends to be relatively small. However, when handling list data, the large number of bits of list elements and the fact that related list elements are scattered throughout the memory device can cause a relative slowdown in computer processing speed. It has become.

Also, when the current list processing runs out of available list memory.

A process called garbage collection, ie.

It is necessary to collect list elements that are no longer needed for processing so that they can be used again. This processing also relatively reduces the processing speed of the computer.

For example, some LISP machines currently used as list processing calculators employ a technique called CDR coding to save memory, reducing the amount of memory required for list elements by about half. There is something that aims to do that. In a device adopting this, for example, the 11th
When storing list data in memory as shown in figure (a).

Rather than storing it as shown in FIG. 11(b).

By storing the data as shown in FIG. 11(c) and arranging the first half of each element in a continuous area, the address area of the second half can be reduced.

However, this method also has the drawback that it loses its effectiveness if list-type data is frequently added or deleted.

[Problem to be solved by the invention]

As described above, the conventional method has problems such as a large amount of memory being required and a large overhead due to garbage collection and the like. You can also create list data, add/delete sublists, and replace lists or sublists.

There was a problem in that matching processing of multiple lists, unification processing, etc. could not be efficiently executed.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide an apparatus that can efficiently process list data and perform high-speed calculations.

[Means to solve the problem]

FIG. F shows an example of the configuration of the present invention.

In FIG. 1, 10 is an arithmetic unit that performs operations related to list processing; 11 is an arithmetic unit that performs operations related to list processing;
A logic operation unit that performs matching, unification, etc.
12 is a control memory in which firmware is stored; 13a;
, 13b is a list data register in which list data to be calculated is set, 14 is a list data storage memory in which list data is stored, 15 is an X address register indicating the address in the depth direction of the list, and 16 is a list element register. Y address register indicating address in number direction, 17 is cell matrix memory, 18 is atom memory, C1l to Cn
m represents a connection cell, and Al to An represent an atom cell.

In the present invention, the internal representation of the list data handled by the five arithmetic units 10 is expressed as
nm, and atom cell A1 to store leaf information of the list, that is, reference information to a data entity called an atom.
This is realized by a data structure consisting of An.

The connected cells CIl to Cnm are two-dimensionally arranged in the depth direction of the list (X direction) and the number direction of list elements (Y direction), and this is defined as the cell matrix memory 17. Atom cells A1 to An are.

The list elements are arranged one-dimensionally in the direction of the number of list elements, and this is referred to as the atom memory 18.

The list data storage memory 14 is a memory composed of one or more cell matrix memories 17 and an atom memory 18. The list data storage memory 14 consists of a plurality of planes, and one list data is stored in one plane.

The list data registers 13a and 13b have a structure in which the contents of the cell matrix memory 17 and the atom memory 18 in the list data storage memory 14 are stored in a similar format. The logic operation unit 11 processes data set in the list data registers 13a, 13b, etc. by executing microinstructions stored in the control memory 12.

It has functions for simultaneous shifting in the X-axis direction, simultaneous shifting in the Y-axis direction, comparison, matching, and other operations related to list processing.

[Effect]

The present invention uses cells (list elements) that are used to express a list structure according to the conventional method.

Focusing on the fact that it represents the connection relationship between cells or between cells and atoms, only the part showing the connection relationship is extracted, and the information showing the connection relationship is arranged two-dimensionally in the connected cells C1l~ By expressing it in Cnm, it is possible to reduce the size of the entire list data and to perform high-speed data manipulation. Since list elements are no longer scattered all over the place, processing of garbage collectors and the like is also simplified.

〔Example〕

FIG. 2 shows an example of the configuration of a connection cell according to an embodiment of the present invention;
The figure shows an example of internal representation of list data according to an embodiment of the present invention.
FIG. 4 is a configuration example of a list data register according to an embodiment of the present invention, and FIG. 5 is an explanatory diagram of sub-list addition/extraction processing according to an embodiment of the present invention.

6 is an explanatory diagram of unification processing according to an embodiment of the present invention, FIG. 7 is a block diagram related to unification processing according to an embodiment of the present invention, and FIG. 8 is an explanatory diagram of the rmcp logic shown in FIG. FIG. 9 shows an example of the configuration of a system to which the present invention is applied.

In the list data storage memory 14 shown in FIG.
For example, it is configured as shown in FIG. It is designed to hold connection information 20 indicating the connection relationship of , and an atom flag 21 indicating whether the connected cell corresponds to a leaf of the list.

This connection information 20. The atom flag 21 indicates the connection cell selected by the X selection signal and the Y selection signal.
It can be set or referenced according to the control signal.

By the way, the external representation of a list is called a 3 expression in the LISP language, and in this S2, it is a left parenthesis.

Right parentheses and atoms are used to allow arbitrary list structures to be represented.

For example, an external representation of a list such as quadratic.

((A B) (CD) (E (F G (H)))) is 1 The internal representation according to the present invention is as shown in FIG.

In the cell matrix memory 17 shown in FIG. 3, a point where nine dotted lines intersect corresponds to one connected cell. Here, the black circle represents a node (cell with list information) whose atom flag is OFF, that is, it is not a leaf of the list, and the white circle ○ represents
The atom flag is ON, indicating that it corresponds to a leaf of the list.

A line connecting these indicates connection information.

The atom memory 18 stores address information and the like to the atom table 30 in which atom character strings are stored, corresponding to each leaf of the list.

The conversion from external representation to internal representation of such a list is 1
This can be achieved using the following logic.

■ Initialize registers, tables, etc. i.e. 9
Clears work registers, atom table 30, etc.

■ Set initial values for work variables.

i←1 (i-row counter) j←1 (j-column counter) k←0 (k-atom table index) ■ Repeat the following operations ■ and ■ until the external expression data is exhausted.

■ Perform list data input operations. left parenthesis right parenthesis 3
Atom is the unit of one read.

■ Processing for each type of read unit.

(a) "(→ Skooking - Turn on the "horizontal connection" flag of the current cell position.

・Turn off the atom flag at the current cell position.

・j←j+1 (horizontally to the right).

) → Unskating ・j=j-1 (horizontally to the left).

(C) In other cases → - Depending on whether the current cell position is the head of the sublist, etc., turn on the "vertical connection" flag of the current cell position or the left cell position.

- Check whether the atom is already registered.

If it has been registered, its index is set to m. If it is not registered, register it in the atom table.

+1 to k4-. Let it be m4-k.

・Turn ON the 7 Tom flag at the current cell position (b) do.

・Atom cell (i) 6m.

・14-i+l (vertically downward).

The format of the internal representation converted through the above processing is called the topology standard form.

As shown in Figure 4, such a topology standard form is
This is also realized on the list data registers 13a and 13b.

A plurality of such registers are used to perform various operations on list data. For example, 2 shown in Figure 4 (a)
By matching the two registers REG1 and REC;2, unification processing and the like can be performed.

In this embodiment, each register REGI REC2 has 1
A maximum of 32 words of 55-bit data can be set. Its internal configuration is as shown in FIG. 4(b), and includes a cell matrix memory 17 having 13×32 connected cells.

It is composed of an atom memory 18 having 32 atom cells.

One O of the cell matrix memory 17 shown in FIG. 4(b) is
Corresponding to one connection cell, each connection cell has 3 bits.

■ This first focus is the "vertical connection" flag, which is 9
It has the following meaning.

When the first bit is O, there is no vertical connection.When it is 1, there is vertical connection.

■ The second bit is the "horizontal connection" flag.

It has the following meaning.

When the second bit is O, there is no horizontal connection.When it is 1, there is horizontal connection.

■ The third bit is an atom flag and has a secondary meaning.

When the third bit is 0, it is not the first leaf, or when it is 1 without list information, it is the first leaf.

The atom flag of this third bit is 0.

and when both the first bit and the second bit are 0,
means "no list information", and if the atom flag is 0 and the first or second bit is 1, then [
"List information outside of collection".

The atom cell consists of a 1-bit variable flag ■ and 15-bit atom table reference information REF. This variable flag ■ has the following meaning.

When the variable flag ■ is 0, it is 2. When the normal atom is 1, it is a variable.

Add and extract sublists as follows for the list data in the topology standard form as described above.

It is now possible to perform processing such as copying, matching, and unification.

[Sublist addition process] When adding a sublist, the position to be added (XO2yO)
and the number (i) of the sublist register where the sublist to be added is located, 2 For example, the data shown in Figure 5 (a) is changed to the data shown in Figure 5 (b). Performs processing to convert to .

The processing logic is as follows.

(2) The y row where (y<yO-1) is left unchanged.

(2) For y rows where (y≧yO), sublists are added one by one while shifting downward by the height of the sublist.

(a) Processing for the row (y-yO).

For (x<xO), the connected cell with list information (
(hereinafter referred to as a continuation cell), it is considered a continuation cell.

For (x=xO), insert the contents of the sub-register and set vertical connection information to it.

For (X>XO), enter the contents of the sublist.

(b) For the row (y>yO), yO→yO+1. Shift downward so that yO+1→yo+2...

(C) When fetching one line from the sublist register, if there is a downward connection, set the vertical connection flag to “1”.
”, and if not, set the flag to “0゛′.

(d) If the logical sum of the vertical connection flags set in (C) above is "1 pass", there are remaining rows on the sublist register side, so repeat (a) to (C) above. Otherwise, the process ends.

sublist extraction process] In the sublist extraction process, the location (xo, yO) of the sublist to be extracted and the number (i) of the sublist register where the extracted sublist should be placed are specified. At this point, contrary to the addition process, the data shown in FIG. 5(B) is converted into the data shown in FIG. 5(B).

The processing logic is as follows.

(2) The y row where (y<yO-1) is left unchanged.

(2) For the y row where (y≧yO), data is extracted for the height of the sublist and the contents are placed in the sublist register.

(a) Processing for the row (y=yo).

For (x=xO), send its contents to the sublist register. It is not necessary to set the vertical connection information.

For (x>xO), send to the sublist register.

(b) The row (y>yO) is shifted upward so that it becomes yO+1→yO, yO+2→yO+1, and so on.

(C) When extracting one line from the sublist, if there is a downward connection, set the vertical connection flag to 1°",
If not, the flag is set to "0".

(d) If the logical sum of the vertical connection flags set in (C) above is "l", there are remaining rows in the sublist, so repeat (a) to (C) above. Otherwise, the process ends.

[Sublist Copy Processing] In sublist copying, specifying the location (xO, yO) of the sublist to be copied and the number (i) of the sublist register where the copy is to be placed, Perform copy processing. This is the same as the extraction process described above, except that there is no change in the original data to be copied.

[Sublist Deletion Processing] When deleting a co-sublist, a process is performed to delete the sublist based on the specification of the position (xo, yO) of the sublist to be deleted. This is the same as the extraction process described above, except that it does not affect sublist registers, etc.

[(Sub)list matching processing command In list or sublist matching operations.

Check whether two lists or sublists match. Specify the location of each target to be checked for a match. If they match, set the match flag to “°1”.
” and if they don't match.

The flag indicating a match is set to "0"' and the result is notified.

[List Unification Processing] Unification processing is an extension of matching processing for two tree-structured data in the form of a list. When a variable is located at a leaf position in a tree, if the corresponding position in the other tree is a variable or some sublist, it is considered a match. This relationship.

It is applied symmetrically to two tree-structured data. If they match, Unify is successful; if they do not match, Unify has failed.

This unification processing occupies an important part in the processing system of a logical language such as the PROLOG language, and will be explained in more detail.

For example, the list data shown in FIG. 6(a).

Suppose that the list data shown in FIG. 6(b) is to be unified.

First, these data are loaded into list data registers REGI and REG2, respectively. Then, the following processing is performed.

■ i←1 (initializes the index i for the list data register to 1).

■ To the internal registers R1 and R2 of the logic operation unit 11.

Read one word from the list data register.

R1←List data register REGI (i) R2←List data register REG2 (i)■ Processing is performed in the following cases.

(a) When both R1 and R2 are empty.

Return true (unification success).

(b) When either R1 or R2 is empty and the other is not.

Return false (unification failure).

(C) When both R1 and R2 are not empty.

Execute the following process ■.

Here, when R1 and R2 are "empty", it means that the values in one row are all 0 for data obtained by horizontally combining the cell matrix memory and the atom memory.

(2) When R1=R2, one part of the unification has been successful up to this point, so proceed to process (2) and check the remaining part.

When R1≠R2, the following processes (1) and (2) are performed.

(1) If either R1 or R2 is a variable specification (
2), otherwise Return false
Set as e (unification failure).

(2) Check whether 9 is equal to the position (rmcp-1) from the left.

rmcp is the right-most cel
It is an abbreviation for "lposition" and refers to the horizontal position of the cell corresponding to the leaf of the list corresponding to the variable.

(a) If not equal, Return false
Set as e (UNIFI failure).

(b) If they are equal.

- Find the height h of the sublist corresponding to the variable.

・Regarding the register on the variable side, the lines below the first line are h
Just do a downward shift.

In this downward shift, if the register overflows downward.

Unify is a failure and Return false
shall be.

■ When i=n (n is the last line number).

Return true (unification success).

When i'4-n.

+4-i +1, and control is returned to process (2).

A block diagram of the arithmetic device 10 that performs the above processing is shown below.
It is shown in FIG.

By the device shown in FIG. 7, the list data register REG
Based on the list data in the topology standard form stored in I, REG2, unification processing is performed as described below.

9 from a normal memory or list data storage memory 14 shown in FIG.

Stores list data of unification targets in topology standard form. This storage method.

This is done by data transfer via a normal memory bus, etc.

The device is controlled by firmware, and upon receiving an activation signal, microinstructions stored in the control memory MMEM start operating from a predetermined address.

When the device completes its operation, the device sets ENDFLAG to 1. In addition, the operation results of the device can be
Display with E-FLAG. TRUE-FLAG becomes "1" when unification is successful, and becomes "0" when unification is not successful.

The part that controls the firmware is the control memory MMEM
, an address register MMAR for accessing this memory, and a microinstruction register MIR for storing accessed microinstructions. The instruction in the microinstruction register MIR is decoded by a decoder DEC, and a control signal corresponding to the instruction is output.

List data registers REGI and REG2.

For example, as shown in Figure 4, a maximum of 32 bits per word is 55 bits.
It is designed to hold word data. Corresponding to these registers, there are address registers RARI and RAR2 for access, respectively.

The READ-R1 instruction is prepared as a microinstruction.
The word with the number indicated in register RAR1.

Read into register R1. Similarly, the READ-R2 instruction reads the word numbered by register RAR2 into register R2.

The data stored in register R1 and register R2 is stored in register content check/comparison logic section (COMP) 7G.
Then, checks and comparisons are made.

The result is set in CASE-FLAG.

The set conditions are as follows.

CASE-FLAG "000" - (R1=null) & (R2=n
ull)"010"-(R1≠null), &(
R2=null)"001"-(R1=null)&
(R2≠null)"111" ・(R1≠nu
ll) &(R2≠null) &(R1=R2)”
011 ” ・= (R1≠null) &(R2≠
null) &(R1≠R2) Here, null means that the register (55 bits) is O, and & means AND logic.

Among the data in registers R1 and R2, the 39th bit from the left (the leftmost bit is the 0th bit) is.

This bit indicates that it is a variable when it is “1°” and that it is not a variable when it is “0”.

VAR-FLAG is the 39th bit of R1.

It has a value that is a combination of the 39th bit of R2.

For unified processing including variables, use rmcp
It is necessary to check for a match up to (the horizontal position of the cell corresponding to the leaf of the list corresponding to the variable). The process is rmc
This is done by p logic 71. The result of the processing is MATCH
-TO-RMCP-FLAG.

The r m c p logic 71 is configured as shown in FIG. 8, for example. In FIG. 8, 80 is a selection section that selects R1 and R2, and 81 is an AND logic.

82 is an OR logic, 83 is a mutual comparison section of each cell, and 84 is an r
In the mcp setting section, 85 is OR logic, and 86 is AND logic.

The mutual comparison section 83 of each cell compares θ to θ of registers R1 and R2.
Compare up to the 38th bit in 3-bit cell units, and r
Find out whether the positions one position to the left of mcp are equal. The output of the rmcp setting unit 84 is 1 corresponding to the cell position.
All 3 bits to the right from the rmcp position are “1”.
′ is.

Others are "0". As a result, when the contents of each cell match up to the rmcp position, MATCH-TO-RMCP-FL is sent via the OR logic 85 and the AND logic 86.
AG is set.

V[RTICAL-FLAG is a flag indicating whether the sublist unified to the variable continues downward. For each of registers R1 and R2, take out the first bit representing vertical connection from 13 cells, and select the side that is not a register that is a variable by the 3 selection unit 80 using the 39th bit of R1 and R2. Then, it is logically ANDed with the output of the rmcp setting unit 84 to check whether it continues downward.

When VBRT I CAL-FLAG is 1”.

There is a downward connection, and when it is 0, it is assumed that there is no downward connection.

The contents of the firmware regarding the above logic are as follows.

Kansaku plate pheasant: END-FLAG knee “'0°゛TRU
E-FLAG: -”0” Death 10=: (R1:=) READ-R1(R2:=
)READ-R2 CASE-FLAG branch 000"°, branch to Tama Sane L Fukai Bean "010", branch to Wang Sansu L Fufubai "001''', Wang Sansu L If it is "111", it will be branched to Ashibu Tanbo. If it is "011", it will be branched to Hisao Katsuhada.
”, branch to the King and 21 Fugoku; ``01'', branch to double processing of ``10'', 21 sticks (branch to brother 2nd processing; ``11'', 1 plate) Branch to classification λM dan ni λ processing: If branch by MATCH-To-FLAG is ``0'', branch to Wang Sane L failure L!i: VERTI CA
If the branch by L-FLAG is "0°", count up the branch RARI to 9 plates (R1: -) READ-R1 Branch to processing I and set the basic date to 2: MATCH-To-FLAG In the case of branch “0” by
Branch processing and establishment to Odo EL failure: Branching by VERTI CAL-FLAG"
If 0゛, branch to the bottom ship 9 times, count up RAR2 (R2 knee) READ-R2 Branch to the processing master, count up RAR1, count up RAR2, branch to the top of the place 1, 33 times Unsuccessful success: TRUE-FLAC; : = “1
'”ENI)-FLAG: = “1” Branch to Okatamaaki use 3 = 77 (:TRUE-FLAG knee”0”END-F
LAC, Knee "1" Branch to wait 1 autumn plate One side co-base: If there is a start signal, branch to gai lie plate cry Wait 1 branch to state ri We have explained the firmware of the unification processing logic in detail above, but as mentioned above. It is clear that firmware for adding and deleting sublists can be easily configured by analogy with two or more logics.

FIG. 9 shows an example of the overall configuration of a system using the list data processing device according to the present invention.

In FIG. 9, 90 is a general-purpose computer equipped with a CPU;
1 represents a main storage device, and 92 represents a list data processing device according to the present invention.

In this example, list data processing device 92 is used as a back-end processor of general-purpose computer 90. The list data processing device 92 includes an arithmetic device 10. as shown in FIG. A list data storage memory 14 is provided, and list data can be exchanged between the list data processing device 92 and the main memory bag W91. The general-purpose computer 90 controls the calculation unit W10 by issuing a startup command to the list data processing device 92 and the like.

Note that the list data storage memory 14 can be omitted by providing a device or the like that converts the list data stored in the main memory bag M91 into a topology standard form and sets it in the list data register of the arithmetic unit 10. It is possible to do so.

Additionally, a device equivalent to the general-purpose computer 90 is provided inside the list data processing device 92, and the list data processing device 92
can also be made to operate independently.

〔Effect of the invention〕

As explained above, according to one aspect of the present invention, list data is connected to connected cells arranged two-dimensionally.

Since processing is performed using a structure represented by dimensionally arranged atom cells, it becomes possible to realize a device with good space efficiency and processing efficiency regarding list processing.

[Brief explanation of drawings]

FIG. 1 shows a configuration example of the present invention. FIG. 2 shows an example of the configuration of a connected cell according to an embodiment of the present invention. FIG. 3 is an example of internal representation of list data according to an embodiment of the present invention. FIG. 4 shows an example of the configuration of a list data register according to an embodiment of the present invention. FIG. 5 is an explanatory diagram of sub-list addition/extraction processing according to the embodiment of the present invention. FIG. 6 is an explanatory diagram of unification processing according to an embodiment of the present invention. FIG. 7 is a unification-related block diagram according to an embodiment of the present invention. FIG. 8 is an explanatory diagram of the r m c p logic shown in FIG. 7. FIG. 9 shows an example of the configuration of a system to which the present invention is applied. FIGS. 10 and 11 show examples of list data storage structures according to the conventional method. In the figure, 10 is an arithmetic unit, 11 is a logic operation unit, 12 is a control memory, 13a and 13b are list data registers, and 14
is a list data storage memory, 15 is an X address register, 16 is a Y address register, 17 is a cell matrix memory,
18 is an atom memory, C1l to Cnm are connection cells,
A1 to An represent atom cells.

Claims (1)

[Scope of Claims] [1] In a list data processing device that processes list-structured data, a memory (14) that stores list data includes connection cells (C11 to Cnm) that store connection information of the list, and connection cells (C11 to Cnm) that store list connection information, and It consists of atom cells (A1 to An) that store leaf information, the connection cells are arranged two-dimensionally in the depth direction of the list and the direction of the number of list elements, and the atom cells are A list data processing device characterized in that the list data processing device is arranged one-dimensionally in the direction of the number of list elements. [2] A list data processing device that processes list-structured data consists of a connection cell that stores list connection information and an atom cell that stores list leaf information. List data registers (13a, 13b) are arranged two-dimensionally in the vertical direction and in the direction of the number of list elements, and the atom cells are set with list data arranged one-dimensionally in the direction of the number of list elements. A list data processing device comprising: and a logic operation unit (11) that performs operations related to list processing using microinstructions on data set in these list data registers.