JPH02109435A - Jitter absorbing device - Google Patents

Abstract

PURPOSE:To reduce data jitter and clock jitter remarkably by outputting a prescribed frequency signal based on an output of an averaging frequency calculation circuit and a master clock by a digital synthesizer. CONSTITUTION:A frequency counter 10 measures the clock frequency extracted by a synchronizing detection circuit 7. A mean frequency calculation circuit 11 obtains an average measured value obtained from a counter 10. A reference oscillator 12 generates a master clock. A digital synthesizer 13 connecting to the oscillator 12 and the circuit 11 receives an output of the circuit 11 as a setting frequency and outputs a corresponding frequency signal. The 2nd PLL circuit 14 connecting to the synthesizer 13 is used to stabilize the output of the synthesizer 13, gives a clock for data readout to a jitter absorbing memory 4 and gives a clock to a digital filter 5 and a D/A converter 6. The clock is independently of jitter.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Fields] The present invention is applicable to CD (compact disc) devices, DAT (
The present invention relates to a jitter absorbing device configured to absorb jitter using memory in a data transmission path in a digital audio tape recorder or the like.

[Prior Art] A clock required by a digital signal processing circuit is created based on clock information included in a digital signal. However, if the clock has jitter (fluctuation on the time axis), distortion and jitter occur when a digital signal is converted into an analog signal.

In order to absorb this type of jitter, it has been proposed to use a jitter absorbing memory as shown in FIG.

In FIG. 2, 1 is a digital signal input terminal, and 2 is a digital signal input circuit. A digital signal including a clock is input to the input terminal 1 during the synchronization period, and a signal corresponding to this is obtained from the input circuit 2. A decoder 3 connected to the input circuit 2 demodulates the digital signal and outputs data. In the jitter absorbing memory 4 connected to the decoder 3, data is written based on the write clock, and data is read based on the read clock, which has less jitter than the write clock. As a result, data with less jitter is obtained at the output stage of the jitter absorption memory 4. The output of the jitter absorption memory 4 passes through a digital filter 5 and is input to a digital/analog (D/A) converter 6, where it is converted into an analog signal.

Synchronization detection circuit 7 connected to digital signal input circuit 2
is a circuit that extracts the clock of the synchronization period within the frame. The first PLL (
The phase-locked loop) circuit 8 consists of a phase comparator, a low-pass filter, a VCO, and a frequency divider. Since the time constant of the low-pass filter of the first PLL circuit 8 is set to be relatively small, the first PLL circuit 8 is a high-speed PLL with a fast response speed. First PLL circuit 8
The clock obtained from the above is given to the decoder 3 and also given to the jitter absorption memory 4 as a write clock. If the time constant of the low-pass filter in the first PLL circuit 1748 is increased, a clock with less jitter can be formed, but the response speed of the PLL circuit 8 will be slow, and if data with a lot of jitter is input, the PLL circuit will
will soon become unable to lock, causing some of the received data to be lost. Further, when the PLL becomes unlocked due to external noise, it takes a long time to relock the PLL, resulting in interruptions in the sound.

Therefore, in the first PLL circuit 8, priority is given to high-speed response over jitter.

On the other hand, the second PLL circuit 9 connected to the synchronization detection port #I7 includes a low-pass filter with a large time constant. Therefore, the second PLL circuit 9 generates a clock with less jitter, provides this to the jitter absorption memory 4 as a reading clock, and also outputs the clock to the digital filter 5 and the D/A.
The converter 6 is also provided with a clock. Since the decoder 3 is driven by a clock with a lot of jitter, it outputs data with a lot of jitter, which is written into the jitter absorption memory 4. However, since the read clock of the jitter absorbing memory 4 has little jitter, the jitter of the data is absorbed by the memory 4.

[Problem M to be solved by the invention] By the way, jitter can be reduced to some extent by providing the second low-speed PLL circuit 9, but in any case, it depends largely on the clock extracted by the synchronization detection circuit 7. Since the readout clock signal is formed using It becomes difficult to ensure responsiveness.

SUMMARY OF THE INVENTION An object of the present invention is to provide a jitter absorbing device that can satisfactorily absorb data jitter by supplying a clock with very little jitter to a jitter absorbing memory.

[Means for Solving the Problems] The present invention for achieving the above object connects a jitter absorption memory to a digital signal transmission path, writes data to the memory based on a data writing clock, and writes data to the memory based on a data writing clock. A jitter absorption device configured to absorb jitter by reading the data using a data read clock having less jitter than a clock for data reading, the jitter absorber comprising: a clock extraction circuit for extracting a clock from a digital signal including clock information; a PLL circuit that inputs the clock obtained from the clock extraction circuit and forms the data writing clock; a frequency measurement circuit that measures the frequency of the clock obtained from the clock extraction circuit; a reference oscillator; The data reading clock corresponding to the frequency signal or a digital synthesizer forming the base frequency signal is set based on the master clock obtained from the frequency measurement circuit and the frequency signal obtained from the frequency measurement circuit. This relates to a jitter absorption device.

[Operation] The PLL circuit forming the data write clock of the present invention operates in the same manner as the conventional one. A digital synthesizer outputs a predetermined frequency signal based on a master clock (reference frequency) obtained from a reference oscillator. Therefore, this output is completely unaffected by jitter of the clock detected by the clock detection circuit, and this frequency signal becomes a clock for reading data via a PLL circuit provided as necessary. Data jitter is absorbed by a jitter absorption memory.

[Embodiment] Next, a data processing device including a jitter absorption device according to an embodiment of the present invention will be described with reference to FIG. However, the first
Components indicated by reference numerals 1 to 8 in the figure are substantially the same as those indicated by the same reference numerals in FIG. 2, so their explanation will be omitted.

Frequency counter 1 connected to synchronization detection circuit 7 in FIG.
0 is a circuit that samples the clock extracted by the synchronization detection port #I7 and fixes the frequency of the clock to 1.

Average frequency calculation circuit 1 connected to frequency counter 10
1 calculates the average of the measured values obtained from the frequency counter 1o, and is comprised of a microcomputer.

A reference oscillator 12 generates a master clock. A digital synthesizer 13 connected to the reference oscillator 12 and the average frequency calculation circuit 11 receives the output of the average frequency calculation circuit 11 as a set frequency, and outputs a frequency signal corresponding to this. Digital synthesizer 1
3 uses what is generally called a quartz digital synthesizer.

A second PLL connected to the digital synthesizer 13
The circuit 14 stabilizes the output of the digital synthesizer 13, and provides a clock for reading data to the jitter absorption memory, as well as a clock to the digital filter 5 and the D/A converter 6.

In the jitter absorption device of this embodiment, the synchronization detection port fM
The data read clock and the clocks for the digital filter 5 and the D/A converter 6 are generated regardless of the jitter of the clock extracted in step 7.

Therefore, a clock with extremely low jitter can be obtained. Furthermore, since the digital synthesizer 13 is used, clocks of various frequencies can be generated as required.

[Modifications] The present invention is not limited to the above-mentioned embodiments, and may be modified. For example, the digital synthesizer 13 and the PLL circuit 14 may be integrated into a circuit configuration. The frequency counter 10 and the average frequency calculation circuit 11 may be integrated to form a frequency measurement circuit.

[Effects of the Invention] As is clear from the above, according to the present invention, data jitter and clock jitter can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a data processing device including a jitter absorption device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a data processing device including a conventional jitter absorption device. 3... Decoder, 4... Jitter absorption memory, 5...
...Digital filter, 6...D/A converter, 7.
...Synchronization detection circuit, 8...First PLL circuit, 10.
... Frequency counter, 11... Average frequency calculation circuit,
12... base oscillator, 13... digital synthesizer, 4... second PLL circuit.

Claims (1)

[Scope of Claims] [1] A jitter absorbing memory is connected to a digital signal transmission path, data is written to the memory based on a data writing clock, and a data reading clock has less jitter than the data writing clock. A jitter absorption device configured to read the data and absorb jitter by using a clock extraction circuit that extracts a clock from a digital signal containing clock information; a PLL circuit that forms a clock for the clock; a frequency measurement circuit that measures the frequency of the clock obtained from the clock extraction circuit; a reference oscillator; a master clock obtained from the reference oscillator and a frequency signal obtained from the frequency measurement circuit; 1. A jitter absorption device comprising: a digital synthesizer that forms the data reading clock corresponding to the frequency signal based on the frequency signal or a frequency signal that is the basis of the data reading clock.