JPH0210477A - Three-dimensional hidden plane processing and drawing device - Google Patents

Abstract

PURPOSE:To eliminate the need to consider a transfer cycle for display as to a three-dimensional frame buffer by transferring the contents of the three- dimensional frame buffer to a two-dimensional dedicated frame buffer and mixing images. CONSTITUTION:Original image data after hidden plane processing by hidden plane processing algorithm using a depth buffer 8 are written in the three- dimensional frame buffer 7. Picture element data are read out of this frame buffer 7 in order and converted into data consisting of three bits for each picture element by a data converting and transfer circuit and the data are transferred to one plane of the two-dimensional dedicated frame memory of dual plane constitution. The contents of the two-dimensional dedicated frame memory 3 are converted, bit by bit, by D/A converters 6R, 6G, and 6B into digital data, which are transferred to a CRT display device 5, so that a graphic form after the hidden plane processing is displayed visually.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a three-dimensional hidden surface processing drawing device, and more specifically, a device for visually displaying figures based on the contents of a two-dimensional dedicated frame memory. The present invention relates to a drawing device for visually displaying a figure after three-dimensional hidden surface processing has been performed on the drawing device.

<Prior Art and Problems to be Solved by the Invention> A three-dimensional graphic display device should be equipped with a bitblt function and a three-dimensional hidden surface processing function that bit map type graphic display devices usually have. Generally, a three-dimensional graphic display device is realized by adding a three-dimensional hidden surface processing function to a two-dimensional graphic workstation.

However, the frame memory built into 2D graphics workstations is generally not designed to efficiently perform 3D hidden surface processing, and in particular, the frame memory built into 2D graphics workstations is not designed to efficiently perform 3D hidden surface processing. Currently, the three-dimensional hidden surface processing efficiency of the device is low.

Therefore, when providing a three-dimensional hidden surface processing function, a two-dimensional dedicated frame memory (
21), frame memory dedicated to 3D hidden surface processing (
22) and a depth buffer (23), the pixel data read from both frame memories (21) and (22) is supplied to a combining circuit (24), and the data output from the combining circuit (24) is sent to a CRT display device. (25), a configuration is adopted in which a two-dimensional mode screen and a three-dimensional mode screen are mixedly displayed. The synthesis circuit (24) may be a digital synthesis circuit or an analog synthesis circuit, but synthesis is generally performed at a clock rate exceeding 100 MH2.

In the three-dimensional hidden surface processing drawing device with the above configuration, display circuits are required for the frame memories (21) and (22), and both frame memories are generally designed to speed up the display. In order to achieve this, a dual-port memory and a dual-brain configuration are required, which results in a significantly larger overall size and a more complex configuration, resulting in a large number of problems.

<Object of the invention> This invention was made in view of the above problems,
It is an object of the present invention to provide a three-dimensional hidden surface processing drawing device that can have a three-dimensional hidden surface processing function while greatly suppressing the complexity and size of the configuration.

Means for Solving the Problems> To achieve the above object, the three-dimensional hidden surface processing rendering device of the present invention has a three-dimensional frame buffer and a depth buffer that do not have a display function. It also has data conversion and transfer means for converting data read from the frame buffer to make it compatible with the two-dimensional frame memory and supplying the converted data to the two-dimensional frame memory.

However, it is preferable that the frame buffer and the depth buffer have a single plane configuration, and that screen erasing is performed in synchronization with data reading for transfer.

Further, it is preferable that the data conversion and transfer means is capable of reading data also from the depth buffer.

Further, it is preferable that the data conversion and transfer means is capable of performing /%-ftone conversion.

Furthermore, it is preferable that the data conversion and transfer means takes into consideration the values of pixels surrounding the pixel of interest and compresses the bit width of the read data so as to reduce cumulative errors.

With the 3D hidden surface processing drawing device configured as described above, when a figure is visually displayed based on the contents of the frame memory dedicated to 2D, sorting processing in the depth direction using the depth buffer is performed. The pixel data is read out from a three-dimensional frame buffer that does not have a display function, in which pixel data is stored in a state in which the pixel data is stored, and the read pixel data is adapted to the two-dimensional dedicated frame memory using a data conversion and transfer means. Since the data is converted as necessary and supplied to the two-dimensional frame memory, it is possible to visually display an image that has been subjected to three-dimensional hidden surface processing based on the contents of the two-dimensional frame memory.

To explain in more detail, in a 3D frame buffer, it is only necessary to read out pixel data in a specified area, perform data conversion processing, and transfer it to a 2D dedicated buffer memory, so the transfer cycle for display is It is no longer necessary to take this into account, and drawing efficiency can be improved, so that the drawing speed can be maintained at a high level even when three-dimensional hidden surface processing has been performed as a whole. Furthermore, by transferring pixel data only from a predetermined area of the three-dimensional frame buffer to the two-dimensional dedicated buffer memory, overlay display of the two-dimensional screen and the three-dimensional hidden surface processing screen can be easily achieved.

Furthermore, it is possible to easily handle bit map type two-dimensional frame memories, graphic display type two-dimensional frame memories, and the like.

If the frame buffer and depth buffer have a single-plane configuration and the screen is erased in synchronization with data reading for transfer, it is possible to simplify the configuration of the frame buffer and depth buffer. can. Furthermore, since the contents of the frame buffer are transferred to the -H two-dimensional dedicated buffer memory before being visually displayed, when pixel data is read from a single-plane frame buffer and transferred to the two-dimensional dedicated buffer memory, Since pixel data in the frame buffer is erased at the same time, it is possible to greatly suppress a decrease in display speed compared to the case where visual display is performed directly based on the contents of the frame buffer.

In addition, if the data conversion and transfer means can also read data from the depth buffer, it can perform perspective conversion, brightness modulation, etc. by reading the depth data from the depth buffer, and create a display with good three-dimensional space. can be achieved.

Furthermore, if the data conversion and transfer means is capable of halftone conversion, even if the 2D-dedicated buffer memory is a bit map display system and cannot display multiple colors simultaneously, 3D By displaying the hidden surface processing screen in halftone, high-quality visual display can be performed.

Furthermore, when the data conversion and transfer means takes into consideration the values of pixels surrounding the pixel of interest and compresses the bit width of the read data so as to reduce the cumulative error,
When converting pixel data read from a three-dimensional frame buffer, which has a large number of bits per pixel, to a two-dimensional dedicated buffer memory, which has a small number of bits per pixel, it is necessary to convert pixel data between each pixel. Since it is possible to greatly suppress the unnaturalness in the image data, and also to minimize the errors associated with data compression, it is possible to display a three-dimensional hidden surface processing screen with high quality.

<Example> Hereinafter, embodiments will be described in detail with reference to the accompanying drawings showing examples.

FIG. 1 is a block diagram showing an embodiment of the three-dimensional hidden surface processing drawing device of the present invention, and shows a central processing unit (hereinafter referred to as C
(abbreviated as PU) (1), system bus ■ and two-dimensional dedicated frame memory with dual brain configuration (3), D/A comparator for red, green, and blue (6R) (6G) (
8 (8), etc., and a CRT display device (5), as well as a 3D frame buffer (7) and a 3D frame buffer for performing 3D hidden surface processing. It has a depth buffer (8) and a data conversion and transfer circuit (9) that performs predetermined conversion processing on pixel data read from the frame buffer (7) and sends it to the system bus (2).

That is, frame buffer (7), depth buffer (
8) and a data conversion and transfer circuit (9) are added to the two-dimensional workstation (4).

To explain in more detail, the two-dimensional dedicated frame memory (3) has one pixel made up of 3-bit data, and the three-dimensional frame buffer (7) has one pixel made up of 24-bit data. It is something that will be done. and,
The frame buffer (7) allows data reading for transfer and writing for erasing the screen to be performed in the same memory access cycle.

Further, the data conversion and transfer circuit (9) has three parallel circuits for dividing 24-bit data into 8-bit units and binarizing each 8-bit data. For example, as shown in Figure 2, there is a ranked line buffer (91) that stores original image data with levels distributed within the range of 0 to 255 as is, and a line buffer (91) that stores data that has already been subjected to reallocation calculations. A distribution line buffer (92) and a correction value calculation circuit (based on the original image data, binary output, etc.)
Calculating a correction value based on a rank correction line buffer (93) that stores the correction value calculated in step 94) and a plurality of correction values stored in the rank correction line buffer (93); The ranking is performed by correcting the read data from the line buffer (9I) to obtain the corrected ranking value.A ranking value calculation circuit (95);
The ranking is done by a distribution rank determining circuit (96) that determines the distribution rank based on the usage value, and a redistribution calculation circuit (96) that redistributes the sum of pixel levels in units of 255 based on the determined distribution rank.
7), a binarization circuit (98) that binarizes the redistribution result, and a repeating error calculated by calculating the difference between the binarized data and the redistribution result, and adding it to the sum of pixel levels. A repetitive error correction circuit (
99).

Therefore, the data to be processed by the ranking line buffer (91), the redistribution line buffer (92), and the ranking correction line buffer (93) are, for example, as shown in FIG.
In the case of the values shown in B and C, the ranking is done by the value calculation circuit (9
In 5), (70+100+120-50)/2
0 (where 20 is a weighting coefficient), a correction value of 12 is obtained, and the ranking is done using the line buffer (
91) to the upper left original image data, the corrected ranking value (see the third diagram) can be obtained.

Then, based on the obtained ranking, the distribution ranking determination circuit (96) sets the distribution ranking based on the usage value (see Fig. 3E).
.

In addition, the repetitive error correction circuit (99) calculates the sum of the data in the redistribution line buffer (92) that has already been subjected to the redistribution operation, and further calculates the difference between the binarized data and the redistribution result. The total pixel level is calculated by calculating the repetition error and adding it to the above sum (2
55 + 135 + 75 + 2O - 485), so this total is distributed in 255 units in descending order of distribution rank.
(See Figure F) By performing binarization using a threshold value of 128 in the binarization circuit (98), the level of the original image data at the upper left can be corrected to 255 (black level).

The operation of the three-dimensional hidden surface processing drawing device having the above configuration is as follows.

Original image data (each pixel data is 24 bits) that has been subjected to hidden surface processing using a conventionally known hidden surface processing algorithm using a depth buffer (8) is written to the three-dimensional frame buffer (7). It is rare.

When this original image data is to be visually displayed on a CRT display device (5), the pixel data is sequentially read out from the frame buffer (7), and the data conversion and transfer circuit (9) converts each pixel into 3-bit data (R data). , G data and B data) and then connects it to a two-dimensional dedicated frame memory with a dual-brane configuration (
3) to one of the branes.

Then, the contents of the two-dimensional dedicated frame memory (3) are processed bit by bit by a D/A converter (OR) (8G) (6(
8), it is converted into digital data and transferred to the CRT display device (5), so that the hidden surface processed figure can be visually displayed.

Of course, for areas that are not processed by the data conversion and transfer circuit (9), the CPU (1) writes data to the two-dimensional dedicated frame memory (3), so the two-dimensional screen and the three-dimensional Overlay display with the hidden surface processing screen can be easily achieved, and when displaying characters, it is sufficient to use a pre-built one for 2D, so 2D work The configuration to be added to the station (4) can be simplified as much as possible.

That is, the data conversion and transfer circuit (9) performs the necessary data conversion so that the pixel data stored in the three-dimensional frame buffer (7) matches the data required in the two-dimensional frame memory (3). Therefore, whether the two-dimensional dedicated frame memory (3) is a bit map type or a graphic display type, a three-dimensional hidden surface processing screen can be easily displayed. be able to.

Furthermore, in the 3D frame buffer allo, data read for data transfer to the 2D dedicated frame memory (3) with a dual-brane configuration and write for screen erasing can be performed in the same memory cycle. In this case, since there is no direct display based on the contents of the frame buffer σ), the frame buffer (7) is stored in a normal memory, such as DRAM. In addition, a single buffer configuration can be adopted, and even if this configuration is adopted, the display speed can be made comparable to that of a two-dimensional screen display. Moreover, the video shifter
Since it is not necessary to provide an ECLRAM, a D/A converter, etc. in correspondence with the frame buffer (7), the 3D hidden surface processing rendering device can be simplified as a whole, and a 3D hidden surface processing function can be added. The associated cost increase can be greatly suppressed. Furthermore, since there is no need to consider the display transfer cycle in the frame buffer (7), the drawing efficiency can be improved and the data transfer control circuit can be simplified. Of course, the frame buffer (7) can also have a dual-brane configuration.

Furthermore, if it is necessary to perform the depth cue function, data is sequentially read out not only from the frame buffer (7) but also from the depth buffer [F]), and after data conversion is performed on the read data, perspective conversion is performed. , brightness modulation, etc. can be applied.

Note that the present invention is not limited to the above-described embodiments; for example, it is possible to omit data processing based on cumulative error values, and it is also possible to omit data processing based on cumulative error values, and also to omit data processing based on the frame buffer (7), depth buffer S) The circuit (9) is made into a unit, and the data conversion function of the data conversion and transfer circuit (9) is combined with a connectable two-dimensional dedicated frame memory (3).
), and can be configured to correspond to the type of image scanner, facsimile, etc., and can be configured with or without a halftone conversion function commonly used in image scanners, facsimiles, etc. The frame memory can have a single plane configuration, and various other design changes can be made without departing from the gist of the invention.

<Effects of the Invention> As described above, the first invention performs image mixing by transferring the contents of the 3D frame buffer to the 2D dedicated frame memory, so that the content of the display in the 3D frame buffer is mixed. There is no need to consider the transfer cycle for 3D hidden surface processing, and it is not only possible to maintain a high drawing speed when 3D hidden surface processing is applied, but also to easily draw data without being affected by the type of 2D dedicated frame memory. Moreover, it has the unique effect of easily achieving overlay display of a two-dimensional screen and a three-dimensional hidden surface processing screen.

The second invention can simplify the configuration of the frame buffer and depth buffer, and can also significantly reduce the display speed compared to the case where visual display is performed directly based on the contents of the frame buffer. It has the unique effect of being able to suppress it.

The third aspect of the invention has the unique effect of being able to perform perspective conversion, brightness modulation, etc. by reading depth data from the depth buffer, and achieve a display with good stereoscopic spacing.

The fourth invention is to display high-quality visual images by halftone displaying the 3D hidden surface processing screen even when the 2D dedicated buffer memory is a bit map display system and cannot display multiple colors simultaneously. This has the unique effect of making it possible to display a target image.

The fifth invention is to convert pixel data read from a three-dimensional frame buffer, which has a large number of bits per pixel, into a two-dimensional dedicated buffer memory, which has a small number of bits per pixel. It is possible to greatly suppress unnaturalness between each pixel, and it is also possible to suppress errors caused by data compression to a minimum, making it possible to display 3D hidden surface processing screens with high quality. It has the unique effect of being able to

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the three-dimensional hidden surface processing drawing device of the present invention, Fig. 2 is a schematic block diagram showing an example of a data conversion and transfer circuit, and Fig. 3 shows the operation of the data conversion and transfer circuit. FIG. 4A is a timing chart schematically showing the relationship between the brain of the frame memory in which the three-dimensional hidden surface processing figure is visually displayed and data transfer; FIG. 5 is a timing chart illustrating a data transfer operation in detail, and FIG. 5 is a block diagram illustrating a conventional example of a three-dimensional hidden surface processing drawing device. (3)...Two-dimensional dedicated frame memory, (5)...
CRT display device, (7)...three-dimensional frame buffer, (8)...depth buffer, (9)...data conversion and transfer circuit

Claims (1)

[Claims] In a drawing device that visually displays a figure based on the contents of a frame memory (3) dedicated to one or two dimensions, a three-dimensional frame buffer (3) that does not have a display function is provided.
7) and a depth buffer (8), the data read from the frame buffer (7) is converted into a two-dimensional frame memory (3) by performing conversion processing to make it compatible with the two-dimensional frame memory (3). 3 characterized in that it has a data conversion and transfer means (9) for supplying data to the
Dimensional hidden surface processing drawing device. 2. Frame buffer (7) and depth buffer (8)
2. The three-dimensional hidden surface processing drawing device according to claim 1, wherein the device has a single-plane configuration, and the screen is erased in synchronization with data reading for transfer. 3. The data conversion and transfer means (9) is connected to the depth buffer (8).
2. The three-dimensional hidden surface processing drawing device according to claim 1, wherein data can also be read from a computer. 4. The three-dimensional hidden surface processing drawing device according to claim 1, wherein the data conversion and transfer means (9) is capable of performing halftone conversion. 5. The data conversion and transfer means (9) takes into consideration the values of peripheral pixels of the pixel of interest and compresses the bit width of the read data so as to reduce cumulative errors. 3D hidden surface processing drawing device.