JPH0210457A - Data transfer device - Google Patents

Abstract

PURPOSE:To perform more complicated operation between a central processing unit CPU and a peripheral device by transmitting a identification code, which designates each device, to a data line connecting the CPU and each device together with data. CONSTITUTION:The output from the CPU is set to the high level on a device select line 10. Then, devices A-C can accept data. A first pulse as the identification code of the device A which is synchronized with a clock CLK is sent to a data line 2. The device A is set to the operating state and processes following data, and devices B and C do not cause malfunction identification codes peculiar to devices B and C are given to these devices respectively. Thus, the processing is performed with only four control signal lines independently of the number of devices, and the operation of each device is controlled by the identification code.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] As electronic devices become more sophisticated these days, a large number of devices are arranged around a central processing unit to control them. For example, control between a large computer and each terminal, control of peripheral LSI in a VTR system, CPU and peripheral LSI in a microcomputer system, etc.
This is control such as I.

[Conventional technology] A block diagram of an example of a conventional device is shown in FIG.

FIG. 5 is a timing chart thereof. The central processing unit CPU and each device A, B, C each have a clock line 1. Data line 2. They are connected in parallel by a 3° strobe line, and each line has a clock CLK,
Data data and strobe signal STB are sent. Further, device A is connected to the central processing unit CPU by a device C select line 4, device B is connected to a device C select line 5, and device C is connected to a central processing unit CPU by a device C select line 6. is now being sent. Since it is connected like this, the central processing unit CP
When transmitting data from U to device A, the select signal C3A makes only the device select line 4 active and the others passive. Hereinafter, the active state will be referred to as H, and the passive state will be referred to as L. Since the device select line 4 becomes H, the device A becomes ready to accept data as shown in FIG. Next, data synchronized with the clock CLK is sent, and after sending out one byte of data, the strobe signal STB is changed from L to H, and then to L. This indicates that one byte of data has been transmitted. When data transmission to device A is completed, the select signal C3A of device A becomes L. During data transfer to device A, device B and device C
The respective select signals C5B and C8C remain at L.

[Problems to be Solved by the Invention] Conventionally, with the above configuration, the same number of device select lines as the number of devices connected to the central processing unit were required. Therefore, as the number of peripheral devices to be controlled by the central processing unit increases, the number of outputs from the central processing unit also increases, and the number of wiring also increases, leading to an increase in cost. Furthermore, as the central processing unit becomes smaller, the absolute number of its output terminals is limited, which may limit the number of peripheral devices.

[Means for Solving the Problems] In order to solve the above problems, the present invention has a structure in which an identification code for specifying each device is transmitted together with data on a data line connecting the central processing unit and each device. I made it.

[Operation] Each device starts its respective operation based on the identification code sent through the data line.

Devices that are not specified by the identification code do not start operating, so devices can be selected using only the data lines.

[Example] FIG. 1 is a block diagram of one embodiment of the present invention.

A clock line 1 for transmitting a clock CLK, a data line 2 for transmitting data, a strobe line 3 for transmitting a strobe signal STB, and a device select line 10 are led out from the central processing unit CPU, and in parallel with these, devices A, Device B and device C are connected in parallel. A timing chart for this is shown in FIG. The output from the central processing unit CPU is set to H on the device select line 10. This allows device A-
At the same time, C becomes ready to accept data. Next, a first pulse synchronized with the clock CLK is sent to the data line 2. Assuming that this first pulse is the identification code of device A, device A becomes operational and processes the data sent thereafter. Device B and device C do not start operating with the first pulse. After sending a series of data to device A, the strobe signal STB is set to H, then set to L again. This indicates that a series of data transmission to device A has ended. Then, the output of the device select line 10 is returned to L. As a result, both devices A1B and A1C become in a state where they cannot accept data, and malfunctions due to noise or the like can be prevented. Devices B and C are each assigned a unique identification code.

FIG. 3 is an example of a flowchart in the above example. Operation begins at step 100, step 10
At step 1, device A determines whether data transmission has occurred. In step 102, the data da t
If aO is 1, since this is the identification code of device A, device A starts operating and processes data 4 to 6 sent thereafter as data in step 103. Once the processing is completed, the work ends in step 104. d at the bottom of Fig. 2
a t aO to 7 indicate the relationship between the clock CLK and the data timing.

[Effects of the Invention] According to the present invention, regardless of the number of peripheral devices controlled by the central processing unit, processing is performed using only four control signal lines, making it possible to save ports and reduce wiring costs. Furthermore, it is easy to send out the identification code of each device from the central processing unit, and it is also easy to put each device into an operable state using the identification code. More complex operations are possible between the central processing unit and peripheral devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a timing chart thereof, and FIG. 3 is a flow chart thereof. FIG. 4 is a block diagram of a conventional example, and FIG. 5 is a timing chart thereof. CPU... Central processing unit, A, B, C... Device, Figure 3

Claims (1)

[Claims] It consists of a central processing unit, a plurality of devices, a clock line, a data line, a strobe line, and a device select line that connect these devices, and the data line has a means for supplying an identification code along with data to the central processing unit. Data transfer device installed.