JPH02104048A - Parallel interface circuit - Google Patents

Abstract

PURPOSE:To prevent the reception of erroneous reception data by latching a reception data in time division and comparing and discriminating the result. CONSTITUTION:A control section 5 outputs a 2nd data latch signal 7 when no data confirming signal 8 is outputted and allows a 2nd data latch cirucit 3 to latch the output of a 1st data latch circuit 2. Then a 1st data latch signal 6 is outputted and a received data 10 is latched to the 1st data latch cirucit 2. Thus, the control section 5 repeats the operation till the data confirming signal 8 is outputted from a comparator 4 and does not output a data requesting signal 9 to a host parallel interface till the control section 5 discriminates the received data 10 to be a correct received data.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to parallel interface circuits.

[Conventional technology]

Conventionally, this type of parallel interface circuit receives data by outputting a data request signal without checking the received data.

[Problem to be solved by the invention]

The above-described conventional parallel interface circuit has the disadvantage that it outputs a data request signal without confirming the received data, and receives erroneous data when receiving data.

[Means to solve the problem]

The parallel interface circuit of the present invention includes a first data latch circuit that latches data using a data latch signal from a host or a data latch signal from a control unit, and a first data latch circuit to determine whether received data is correct or incorrect. a second data latch circuit that latches the output of the circuit using a data latch signal from the control section; a comparison circuit that compares the outputs of the first data latch circuit and the second data latch circuit; It has a control section that determines whether the data is correct or incorrect and outputs a data request signal to a higher-level device.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

Received data 10 from the upper parallel interface 1 is latched into the first data latch circuit 2 by the first data latch signal 6 output from the upper parallel interface 1. This first data latch signal 6 is input to the control section 5 as a transmission signal 11. When the control unit 5 confirms the transmission signal 11, it outputs the second data latch signal 7.

The second data latch circuit 3 latches the output of the first data latch circuit 2 using the second data latch signal 7.

The control unit 5 outputs the first data latch signal 6 and causes the first data latch circuit 2 to latch the received data 10 again. The comparison circuit 4 compares the output of the first data latch circuit 2 and the output of the second data latch circuit 3, and outputs a data confirmation signal 8 to the control unit 5 if the data are the same. The control unit 5 determines that the received data 10 is correct data based on the data confirmation signal 8, outputs a data request signal 9 to the upper parallel interface 1, and performs the next reception. Further, the comparison circuit 4 does not output the data confirmation signal 8 when the output of the first data latch circuit 2 and the output of the second data latch circuit 3 are not the same.

When the data confirmation signal 8 is not output, the control unit 5 outputs the second data latch signal 7 and causes the output of the first data latch circuit 2 to be transferred to the second data latch circuit 3. Next, the first data latch signal 6 is outputted to cause the first data latch circuit 2 to latch the received data 10. In this way, the control unit 5 repeats the operation until the data confirmation signal 8 is output from the comparison circuit 4, and does not output the data request signal 9 to the upper parallel interface until it determines that the received data 10 is correct received data.

By performing the above operations, instantaneous changes in received data between the upper parallel interface 1 and the first data latch circuit 2 or between the first data latch circuit 2 and the second data latch circuit 3 are prevented. Even if incorrect received data is latched, only correct received data can be received.

〔Effect of the invention〕

As described above, the present invention has the effect of preventing erroneous reception data from being received by latching and comparing received data in a time-division manner.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1... Upper parallel interface, 2...
...First data latch circuit, 3...Second data latch circuit, 4...Comparison circuit, 5...
・Control unit, 6...First data latch signal, 7.
...Second data latch signal, 8...Data confirmation signal, 9...Data request signal, 10...
... Received data, 11... Transmitted signal. Agent Patent Attorney Oto Uchihara

Claims (1)

[Claims] A first data latch circuit that latches received data using a data latch signal from a host device or a data latch signal from a control unit, and a data latch signal from the control unit that latches the received data latched by the first data latch circuit. a second data latch circuit that latches the data; a comparison circuit that compares the outputs of the first and second data latch circuits; and a comparison circuit that determines whether the received data is correct or incorrect based on the output from the comparison circuit and requests data from the host device. 1. A parallel interface circuit comprising: a control section that outputs a signal.