JPH02103800A - Sampling and holding circuit - Google Patents

Abstract

PURPOSE:To suppress the reduction of the holding voltage due to leak of a capacitor for long-time holding to zero by using a counter instead of the charging capacitor. CONSTITUTION:When a sampling and holding signal is in the high level, the output of an oscillating circuit 6 is outputted through an AND gate 7. Meanwhile, when the voltage of an output signal 11 is higher than that of an input signal 15, the output of a comparator goes to the low level and the output of an inverter 16 goes to the high level, and the output pulse of the oscillating circuit is inputted to a down-count terminal, and therefore, a counter 2 is counted down. Consequently, the voltage of the output signal of a D/A converter 1 is reduced to follow up the voltage of the input signal 15. When the voltage of the output signal 11 is lower than that of the input signal 15, the output pulse of the oscillating circuit is inputted to the up-count terminal, and the counter 2 is counted up, and the voltage of the output signal 11 of the D/A converter 1 is raised to follow up the input signal. Thus, the holding voltage is always kept constant.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to sample/hold circuits.

[Conventional technology]

Traditionally, this type of sample/hold circuit.

It consisted of a charging capacitor and an analog switch.

(Problem to be Solved by the Invention) Therefore, when the hold time becomes long, there is a drawback that an error occurs in the hold voltage due to discharge from the capacitor.

An object of the present invention is to provide a sample/hold circuit that can always keep a hold voltage constant regardless of the length of the hold time.

(Means for Solving the Problems) In order to achieve the above object, the sample/hold circuit according to the present invention includes a comparator that compares the voltages of an input analog signal and an output signal, and a sample/hold switching signal that is in a hold state. When is the oscillation circuit output sent? 72: a gate circuit for transmitting the comparator output I and therefore the output of the oscillation circuit to a first output terminal or a second output terminal I when the sample/hold switching signal is in the sample state; Is the first output terminal of the gate circuit count up terminal 1? It consists of an up-down counter whose output terminals c, 7g and 2 are respectively connected to a countdown terminal l, and a D/A converter which converts the output sound of the up-down counter into D/A and outputs the output signal.

(Example) Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 is a block diagram illustrating one embodiment of a sample/hold circuit according to the present invention.

In the figure, 3 is a comparator, which inputs the input signal 15 and D/
Voltage of output signal 11 of A converter 1? compare. 4 is a sample hold signal. When this signal is high level (logic ``1''), it is low level (logic ``'').
0''), a hold operation occurs.

5 is a gate circuit. This consists of three AND gates7.
8 and 9, one inverter 15, and one oscillation circuit 6I.

13i, AN when sample hold signal 4 is low level
The D gate 7 is turned off and the output pulse of the oscillation circuit 6 for counting operation is not output to the subsequent circuit.

When the sample hold signal 4 is at a high level, the AND gate 7 is turned on, so the signal from the oscillation circuit 6 is
D game) 8. SH is sent, and depending on the output state of comparator 3, either AND gate 8 or 9 is turned on.

In this embodiment, when the output signal 11 has a higher voltage than the input signal 15, the comparator output goes to low level and the output of the inverter 16 goes to the low level, so the AND gate 9 turns on and the output from the AND gate 9 is turned on. The pulse of circuit 6 is output.

Contrary to the above, if the output signal 11 has a lower voltage than the input signal 15, the output of the comparator 3 will be at a high level, so A
When the ND gate 8 is turned on, the pulse from the oscillation circuit 6 is output from the AND gate 8.

2 is an up/down counter, the up count terminal is connected to the output of AND gate 8, and the down count terminal is connected to AN
They are respectively connected to the outputs of the D gates 9. Therefore, when the output pulse of the oscillation circuit is input to the up-count terminal, the counter 2 counts up, and when it is input to the down-count terminal, it counts down.

1 is a D/A converter, and the digital data output from the up/down counter 2 is converted into an analog voltage.

FIG. 2 is a waveform diagram for explaining the operation of the circuit of FIG. 1.

When the sample hold signal is high level, the oscillation circuit 6
Is the output of AND gate 7? On the other hand, when the voltage of the output signal 11 is higher than the input signal 15, the comparator output becomes low level, the inverter 16 output becomes high level, and the output pulse of the oscillation circuit is input to the down count terminal. Therefore, counter 2 counts down. As a result, the voltage of the output signal of the D/A converter 1 decreases and follows the voltage of the input signal 15.

When the voltage of the input signal 15 and output signal 11 is low, the output pulse of the oscillation circuit is input to the up-count terminal, the counter 2 counts up, and the voltage of the output signal 1 of the D/A converter 1 increases. 9° will still follow the input signal.

When the sample and hold signal is at a low level, that is, during a hold operation, the AND gate 7 is gated off, so that the pulse of the up/down counter 2ζ moss oscillation circuit 6 is outputted to 0. Therefore, the output signal is held at the same voltage.

(Effects of the Invention) As explained above, the present invention uses a counter instead of a charging capacitor to reduce voltage.

This has the effect of suppressing the drop in hold voltage due to capacitor leakage to zero when holding for a long time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the sample/hold circuit according to the present invention, and FIG. 2 is a waveform diagram illustrating the operation of the circuit of FIG. 1. 1... D/A converter 2... Up/down counter 3... Comparator 6... Oscillation circuit patent applicant NEC Corporation

Claims (1)

[Claims] A ratio softener that compares the voltages of the input analog signal and the output signal, stops sending the oscillation circuit output when the sample/hold switching signal is in the hold state, and compares the voltage of the sample/hold switching signal when the sample/hold switching signal is in the sample state. a gate circuit that sends the oscillation circuit output to a first output terminal or a second output terminal according to the output of the oscillation circuit; the first output terminal of the gate circuit is a count-up terminal, and the second output terminal is a count-down terminal; 1. A sample/hold circuit comprising up/down counters connected to respective up/down counters, and a D/A converter for D/A converting the outputs of the up/down counters and outputting the output signals.