JPH02101793A - Manufacture of multilayer printed interconnection board - Google Patents
Manufacture of multilayer printed interconnection boardInfo
- Publication number
- JPH02101793A JPH02101793A JP25532388A JP25532388A JPH02101793A JP H02101793 A JPH02101793 A JP H02101793A JP 25532388 A JP25532388 A JP 25532388A JP 25532388 A JP25532388 A JP 25532388A JP H02101793 A JPH02101793 A JP H02101793A
- Authority
- JP
- Japan
- Prior art keywords
- printed wiring
- wiring board
- polyimide resin
- printed
- connection land
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229920001721 polyimide Polymers 0.000 claims abstract description 20
- 239000009719 polyimide resin Substances 0.000 claims abstract description 16
- 238000007639 printing Methods 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 5
- 239000002184 metal Substances 0.000 abstract description 2
- 229910052751 metal Inorganic materials 0.000 abstract description 2
- 238000007650 screen-printing Methods 0.000 abstract description 2
- 238000010030 laminating Methods 0.000 abstract 1
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 10
- 230000001070 adhesive effect Effects 0.000 description 9
- 239000000853 adhesive Substances 0.000 description 7
- 239000004020 conductor Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 238000004080 punching Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229920006332 epoxy adhesive Polymers 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
二の発明は、多層プリント配線基板を製造する際の積層
方法の改良に関する。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The second invention relates to an improvement in a lamination method when manufacturing a multilayer printed wiring board.
く従来の技術〉
７レキシプルプリント配線基板（以下、ＦＰＣと謂う）
を２Ｍ以上積層した多層プリント配線基板、あるいは銅
張８！層板製のプリント配線基板（以下、ＰＷＢと謂う
）とＦＰＣを積層した複合多層プリン）配線基板は、熱
硬化性接着シートを介して各プリント配線基板を熱圧着
し、その後ドリルでスルホールを形成してこの部分を銅
めっきすることにより、各プリント配線基板間を電気的
に接続することが一般に行われている。また、熱硬化性
接着シートにあらかじめ金型パンチング等によって抜き
穴を形成しておき、その盛所を通して半田ペーストを印
刷し、これを硬化させて電気的に接続することも行われ
ている。Conventional technology> 7 Lexiple printed circuit board (hereinafter referred to as FPC)
Multilayer printed wiring board with 2M or more laminated, or copper-clad 8! The printed wiring board (hereinafter referred to as PWB) made of a composite multilayer printed wiring board (hereinafter referred to as PWB) and FPC laminated is made by thermo-compression bonding of each printed wiring board via a thermosetting adhesive sheet, and then through-holes are formed with a drill. It is common practice to electrically connect each printed wiring board by plating this portion with copper. In addition, holes are formed in advance in a thermosetting adhesive sheet by die punching or the like, and solder paste is printed through the holes, and the solder paste is cured to make an electrical connection.
〈発明が解決しようとする課屈〉
上記の接着シートは接着を目的としたものであるため、
各プリント配線基板間の絶縁性を向上するためにポリイ
ミドフィルムを介在させたり、プリント配ＭＸ基板の接
着面にフィルムカバーレイ等をあらかじめ貼り合わせて
おく必要があった。また半田ペーストの印刷、硬化によ
り電気的接続を得る場合、半田ペーストが溶融時に容易
に抜き穴の部分に流れ込むように、あらかじめ接着シー
トをパンチング加工して接着シートの接続ランド部に対
応する部分を除去しでおく必要があり、固定資産となる
金型の製作保管が必要になるとともに、加工工程が一つ
増えるという量定があった。<Issues to be solved by the invention> Since the above-mentioned adhesive sheet is intended for adhesion,
In order to improve the insulation between each printed wiring board, it was necessary to interpose a polyimide film or to attach a film coverlay or the like to the adhesive surface of the printed MX board in advance. In addition, when obtaining electrical connections by printing and curing solder paste, punch the adhesive sheet in advance to punch the parts of the adhesive sheet that correspond to the connection lands so that the solder paste can easily flow into the punched holes when melted. It was necessary to remove the metal mold, which required production and storage of the mold, which is a fixed asset, and also added one more processing process.
この発明はこの点に着目し、絶縁用フィルムや金型を用
いずに多層プリント配＃ｌ基板を製造することを目的と
してなされたものである。The present invention has focused on this point and has been made for the purpose of manufacturing a multilayer printed wiring board without using an insulating film or a mold.
く課ｚを解決するための手段〉
上述の目的を達成するために、この発明では、積層され
る各プリント配線基板にあらかじめ所定の回路パターン
を形成するとともに、各プリント配線基板を相互に接続
するための接続ランド部に導通孔をそれぞれ形威し、一
方のプリント配ａ基板に上記接続ランド部を避けてイン
ク状ポリイミド樹脂を印刷した後、他方のプリント配線
基板を重ね合わせてインク状ボリミイド樹脂を硬化させ
るようにしでいる。Means for Solving Problem Z> In order to achieve the above-mentioned object, the present invention forms a predetermined circuit pattern on each printed wiring board to be laminated in advance, and connects each printed wiring board to each other. After forming conductive holes in each of the connection lands for the purpose of printing, and printing ink-like polyimide resin on one printed wiring board avoiding the above-mentioned connection lands, the other printed wiring board is superimposed and ink-like polyimide resin is printed on the other printed wiring board. It is made to harden.
く作用〉
ポリイミドθを脂は電気絶縁性と接着性に優れており、
絶縁と接着に高い信頼性が得られる。またポリイミド樹
脂の層は印刷によって形成されるため、パンチング用の
金型よりも製作が容易でコス（の安い印刷版を用いるこ
とによって、導通孔が設けられている接続ランド部にポ
リイミド樹脂が付着しないようにすることができる。尚
、導通孔には部品実装時に半田ペーストが印刷され、こ
れを溶融させることによって各プリント配ｍ基板の相互
接続が打われる。Effect〉 Polyimide θ has excellent electrical insulation and adhesive properties,
High reliability can be obtained for insulation and adhesion. In addition, since the polyimide resin layer is formed by printing, it is easier to manufacture than a punching mold, and by using a cheaper printing plate, the polyimide resin adheres to the connecting land where the conductive holes are provided. Note that solder paste is printed on the conductive holes when components are mounted, and by melting the solder paste, interconnections between the printed circuit boards are established.
〈実施例〉
次に図示の一実施例について説明する。Ｐｔ５１図は製
造工程を説明する断面図、第２図は相互接続が行われた
状態の断面図である。<Example> Next, an example shown in the drawings will be described. Pt51 is a cross-sectional view for explaining the manufacturing process, and FIG. 2 is a cross-sectional view of the interconnected state.
Ｐｔ４１図において、１はＦＰＣまたはＰＷＢ等の第１
のプリント配線基板、２はプリント配線基板１に積層さ
れる第２のプリント配線基板であり、まず、プリント配
線基板１及び２にあらがじめ所定の回路パターン形成と
導通孔形成が実施される。In Pt41 diagram, 1 is the first of FPC or PWB etc.
The printed wiring board 2 is a second printed wiring board laminated on the printed wiring board 1, and first, predetermined circuit pattern formation and conductive hole formation are performed on the printed wiring boards 1 and 2 in advance. .
即ち、図において、１１はプリント配線基板１の基板、
１２は基板１１上に形成されている導体回路部、１２ａ
は導体回路部１２の所定箇所に設けられた接続ランド部
、１３は接続ランド部１２ａに形成された導通孔である
。また２１はプリント配線基板２の基板、２２は基板２
１上に形成されている導体回路部、２２ａは導体回路部
２２の所定箇所に設けられた接続ランド部、２３は接続
ランド部２２ｇに形成された導通孔である。この導通孔
２３は導通孔１３よりも大きめに形成される。That is, in the figure, 11 is the substrate of the printed wiring board 1;
12 is a conductor circuit section formed on the substrate 11; 12a;
1 is a connection land provided at a predetermined location of the conductor circuit portion 12, and 13 is a conduction hole formed in the connection land 12a. Further, 21 is the board of the printed wiring board 2, and 22 is the board 2.
1, 22a is a connection land portion provided at a predetermined location of the conductor circuit portion 22, and 23 is a conduction hole formed in the connection land portion 22g. The conduction hole 23 is formed to be larger than the conduction hole 13.
次いで、第１図（ａ）に示すプリント配線基板１にｆ５
１図（ｂ）に示すようにインク状ポリイミド樹脂を印刷
する。３はこのインク状ポリイミド樹脂であり、印刷は
例えばスクリーン印刷が利用され、接続ランド部１２ａ
の部分に印刷されないように製板されたスクリーン版が
用いられる１次いで、第１図（、）に示すようにプリン
ト配線基板１にプリント配線基板２を重ね合わせて熱圧
着し、更に恒温炉でインク状ポリイミドＩ（脂３を硬化
させることにより、接続ランド部を貫通した導通孔５を
有する多層プリント配線基板４を得るのである。Next, f5 is attached to the printed wiring board 1 shown in FIG. 1(a).
1. Print an ink-like polyimide resin as shown in FIG. 1(b). 3 is this ink-like polyimide resin, for example, screen printing is used for printing, and the connecting land portion 12a is printed.
A screen plate made so as not to print on the parts is used.Next, as shown in Fig. 1(,), printed wiring board 2 is superimposed on printed wiring board 1 and bonded by thermocompression, and then heated in a constant temperature oven. By curing the ink-like polyimide I (oil 3), a multilayer printed wiring board 4 having conductive holes 5 passing through the connection land portions is obtained.
各プリント配線基板１，２間の相互接続は、例えば部品
実装時に導通孔５に半田ペーストを印刷し、これを溶融
させてｆｊＳ２図に示すように半田６を導通孔５に充填
させることにより行われる。この時、導通孔５の周辺に
は硬化ポリイミド樹脂３が存在しないため、半田６の溶
融と充填は支障なく行われ、両虎板間を確実に接続する
ことができる。The interconnection between the printed wiring boards 1 and 2 is achieved, for example, by printing solder paste in the conductive holes 5 during component mounting, melting it, and filling the conductive holes 5 with solder 6 as shown in Figure fjS2. be exposed. At this time, since the cured polyimide resin 3 is not present around the conductive hole 5, the melting and filling of the solder 6 can be performed without any problem, and the two tabs can be reliably connected.
尚、上記の実施例は２枚のプリント配線基板を積層する
場合の例であるが、３枚以上を積層した多層プリント配
線基板も実施例に準じて製造することができる。Although the above embodiment is an example in which two printed wiring boards are stacked, a multilayer printed wiring board in which three or more boards are stacked can also be manufactured according to the embodiment.
〈発明の効果〉
上述の実施例から明らかなように、この発明は、所定の
パターンを形成済みの各プリント配線基板の接続ランド
部に導通孔をそれぞれ形成し、接続ランド部を避けて印
刷したインク状ポリイミド樹脂によって各プリント配線
基板をｆｆｆ／ｊｉｆｆするようにしたものである。<Effects of the Invention> As is clear from the above-described embodiments, the present invention provides a method in which conductive holes are formed in the connection land portions of each printed wiring board on which a predetermined pattern has been formed, and printing is performed while avoiding the connection land portions. Each printed wiring board is fff/jiffed using ink-like polyimide resin.
即ち、電気絶縁性と接着性に優れたポリイミド樹脂を用
いているので、ポリイミドフィルムやフィルムカバーレ
イ等の絶縁用フィルムを用いないでも絶縁が確実となり
、また、硬化後はエポキシ系の接着剤よりも優れた接着
力と耐熱性が得られる。In other words, since polyimide resin with excellent electrical insulation and adhesive properties is used, insulation can be ensured without the use of insulating films such as polyimide films or film coverlays, and after curing, it is easier to use than epoxy adhesives. Also provides excellent adhesive strength and heat resistance.
更に、半田ペーストが溶融時に容易に導通孔に流れ込む
ようにするために導通孔周辺からポリイミド樹脂をなく
すことは、印刷版の設計によって容易に実施できて、製
作費や管理費の高い金型やパンチング加工工程は不要と
なり、これらの総合効果により多層プリント配線基板を
安価に製造することが可能となるのである。Furthermore, eliminating the polyimide resin from around the through holes so that the solder paste can easily flow into the through holes when melted can be easily implemented by designing the printing plate, which eliminates the need for molds and molds, which have high manufacturing and management costs. The punching process becomes unnecessary, and the overall effect of these makes it possible to manufacture multilayer printed wiring boards at low cost.
第１図（ａ）、第１図（■〕）及びＰｔ５１図（ｃ）は
、それぞれこの発明の実施例による製造工程の断面図、
ｔｔＳ２図は、相互接続が行われた状態の断面図である
。
１．２・・・プリント配線基板 、
３・・・インク状ポリイミド樹脂 、
４・・・多層プリント配線基板 、
５．１３．２３・・・導通孔 、１１．２１・・・基板
１２．２２・・・導体回路部 、 １２ａ、２２ａ・・
・接続ランド部１［１
＠（Ｏ）
膏１ ツ（ｂ）
端１ ＷＡ（Ｃ）
π２％！１FIG. 1(a), FIG. 1(■)) and Pt51(c) are sectional views of the manufacturing process according to the embodiment of the present invention, respectively.
Figure ttS2 is a cross-sectional view of the interconnected state. 1.2...Printed wiring board, 3...Ink-like polyimide resin, 4...Multilayer printed wiring board, 5.13.23...Conducting hole, 11.21...Substrate 12.22.・・Conductor circuit part, 12a, 22a・・
・Connection land part 1 [1 @ (O) Glue 1 TS (b) End 1 WA (C) π2%! 1
Claims (1)
回路パターンを形成するとともに、各プリント配線基板
を相互に接続するための接続ランド部に導通孔をそれぞ
れ形成し、一方のプリント配線基板に上記接続ランド部
を避けてインク状ポリイミド樹脂を印刷した後、他方の
プリント配線基板を重ね合わせてインク状ポリイミド樹
脂を硬化させることを特徴とする多層プリント配線基板
の製造方法。1. A predetermined circuit pattern is formed in advance on each printed wiring board to be laminated, and conductive holes are formed in the connecting land portions for connecting the printed wiring boards to each other, and the connecting land portions are formed on one printed wiring board. 1. A method for manufacturing a multilayer printed wiring board, which comprises printing an ink-like polyimide resin while avoiding the above-mentioned conditions, and then superimposing another printed wiring board and curing the ink-like polyimide resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25532388A JPH02101793A (en) | 1988-10-11 | 1988-10-11 | Manufacture of multilayer printed interconnection board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25532388A JPH02101793A (en) | 1988-10-11 | 1988-10-11 | Manufacture of multilayer printed interconnection board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02101793A true JPH02101793A (en) | 1990-04-13 |
Family
ID=17277185
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25532388A Pending JPH02101793A (en) | 1988-10-11 | 1988-10-11 | Manufacture of multilayer printed interconnection board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02101793A (en) |
-
1988
- 1988-10-11 JP JP25532388A patent/JPH02101793A/en active Pending
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