JPH02100544A - Data transmission equipment - Google Patents

Abstract

PURPOSE:To connect a terminal equipment to a transmission line without recognizing the polarity of a signal by switching the polarity of the signal transmitted on the transmission line and making the polarity of the transmission signal equal to the polarity of a signal on the transmission line. CONSTITUTION:When a terminal equipment 2A is connected to the transmission line 1, power is supplied to a power module 13 from the transmission line 1, a signal polarity storage circuit 17 is initialized, and the polarity input terminals 3e and 3f of CPU 3A come to an 'H' level. When a frame is transmitted in such a way that a start bit comes to the +line 1a-side of the transmission line 1 in such a state, a decoding circuit 9 decodes the signal on the transmission line 1, and a decoding result is inputted to the input terminals 17a and 17b of the signal polarity storage circuit 17. Then, the polarity input terminal 3e of CPU 3A comes to an 'L' level, the polarity input terminal 3f comes to the 'H' level, and the start bit appears on the +line 1a-side of the transmission line 1. The state is held until the terminal equipment 2A is detached from the transmission line 1 and feed from the transmission line 1 stops.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data transmission device in which a large number of terminals connected to a pair of information transmission paths transmit and receive information via the transmission path using AMI codes. .

[Conventional technology]

Figure 7 shows, for example, the conventional data transmission shown in the ``Report of the Research Group on Computerization in the Home (Final Report) - Technology Standardization Edition'' published by the Research Group on Computerization in the Home in March 1986. It is a circuit diagram showing the device, and in the figure, ■ is a transmission path for signal transmission, and is composed of a tenth line 1a and a single line lb. 2 and 11 are terminals,
3 is a transmission control device connected to the transmission path 1 and configured as explained below, for transmitting and receiving information according to a predetermined protocol, and has the packet structure shown in FIGS. 8(a) and 8(b). , the transmission data for transmitting the signal with the AMI code in the character configuration is output to the 1-output terminal 3a and the -output terminal 3b, and each time the code "0" is transmitted, 1
Outputs are output alternately to -output terminal 3a and -output terminal 3b. 4.5 is a transistor, and output terminals 3a, -
An output terminal 3b is connected to each base terminal, forming a common emitter type amplifier driven by a signal output. 6 is a coupling transformer, the collector terminal of the transistor 45 is grounded on the primary side, and the power supply voltage is supplied to the intermediate tap 6a on the primary side, and it is turned on and off according to the on/off of the transistors 4 and 5. Current flows and coupling transformer 6
An AMI-encoded signal (hereinafter abbreviated as AMI signal) appears on the secondary side. A capacitor 78 injects the AMI signal appearing on the secondary side of the transformer 6 into the transmission line 1. 9 is an AMI decoding circuit, which is connected to the primary side of the transformer 6. The AMI signal on the transmission line 1-h is applied to the secondary side of the 1-lance 6 via the capacitor 7.8, and therefore the AMI signal on the 1-h
The AMI signal appears on the next side as well, and is input manually to the AMI decoding circuit 9, and the decoding result is sent to the receiver of the transmission side 11 device 3 (input terminal 3).
It is manually operated by c. IO is 'gttX which supplies the necessary power to terminal [2.

Next, the operation will be explained. When the terminal device 2 is connected to the transmission path 1 and, for example, a transmission request is issued to the terminal device 11, the transmission control device 3 uses a signal from the AMI decoding circuit 9 to determine whether the transmission path 1 is in an idle state (GM L?). 2, change the start focus code "0" of each character to (-line 1a) according to the Pakent configuration shown in FIG. 8(a).
Transmit with positive polarity. That is, when the output terminal 3a is set to a high level during the start focus period, the base current is supplied to the transistor 4 and the transistor 4 is turned on. As the current flows, a voltage is generated at the polarity of the arrow. This voltage is also generated on the secondary side of the transformer 6 with the polarity indicated by the arrow, and is transmitted via the capacitor 7.8 to the transmission line 1 in a waveform as shown in FIG. 8(b).

Also, when transmitting the start bit code "0", the voltage generated in the transformer 6 is input to the AMI decoding circuit 9, the decoding result is read at the reception input terminal 3c, and the transmitted code is correctly transmitted in the transmission control device 3. Make sure that it is. Next, when transmitting the code "1", the transistor 45 is turned off by outputting a low level from both the + output terminal 3a and the - output terminal 3b. That is, since nothing is output to the transmission line 1, the voltage becomes 0. Furthermore, the start bit code “0” is followed by the code “0”.
'', the output terminal 3b is set to a high level to turn on the transistor 5, generate a voltage with a polarity opposite to that of the start bit, and output a signal to the transmission line 1. This allows serial transmission of baseband signals of AMI codes. In addition, for reception, for example, only the signal transmitted by the terminal all is received by the transformer 6 via the capacitor 7.8, decoded by the AMI decoding circuit 9 as in the case of transmission, input to the reception input terminal 3c, and transmitted control Device 3 receives.

Next, a case where terminals 2 and 11 start transmitting at the same time will be described. 9th [D(a), (bl is terminal 2゜1
1 indicates the signal to be transmitted, and C indicates the signal actually applied to the transmission path 1. Since the start focus code "0" initially transmitted is transmitted with the same polarity in both terminals 2 and 11, it is accurately transmitted as a code "0" to the transmission path l. The code rl of the next bit is similarly applied to both terminals 2.
11 does not output a signal to the transmission line l. Also, when transmitting the code "0" next time, both terminals 2 and 11 output signals with the opposite polarity to the start focus, so both terminals i2 and 11 output signals with the opposite polarity to the start focus.
．． 11 transmits the same code, the transmitted signal and the received signal match and are transmitted accurately. When terminal 2 transmits the code "0" and terminal all transmits the code "1", the third bit becomes the state where the code "0" is transmitted on the transmission path 1, and the terminal 11 receives the transmitted signal. A mismatch in received signals is detected and transmission is stopped. On the other hand, since the transmitted signal and the received signal in terminal device 2 match, transmission continues. In this way, when a collision occurs between terminals 2.11, a transmission control system called "rC3MA/CD win-now system" is realized in which one terminal survives. In order to ensure that this rcsMA/CD win-now system is carried out, each terminal 2.11 needs to transmit the start bit code r□J to the transmission path 1 with the same polarity. If there is a terminal connected with opposite polarity, the signal level on transmission path 1 will be uncertain when the start bit is transmitted, and the terminal that caused the collision will not be able to match the transmitted and received signals, resulting in a winner. It becomes impossible to realize it.

[Problem to be solved by the invention]

Since the conventional data transmission device is configured as described above, there is a polarity in the transmission line 1, and when connecting the terminal 2.11 to the transmission line 1, it is necessary to confirm the polarity. There were problems such as mistakes made during construction that could cause problems with the transmission system.

This invention was made in order to solve the above-mentioned problems, and aims to provide a data transmission device that can normally transmit information without checking the polarity when connecting a terminal to a transmission line. purpose.

[Means to solve the problem]

The data transmission device according to the present invention is provided with a signal switching means for switching the polarity of a start focus transmitted by a terminal, and a signal polarity detection means for determining the polarity of a signal on a transmission line, and a transmission control device controls the transmission of the signal. so that the polarity of the signal sent to the transmission path is the same as the signal polarity on the transmission path.
The polarity is determined by receiving valid data.

[For production]

The data transmission device of the present invention switches the polarity of the start bit transmitted by the terminal based on the determination result of the signal polarity with the transmission line, and changes the polarity of the star I/bin 1- transmitted by the terminal to the transmission line. This acts to match all terminals connected to the .

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, ■ indicates a transmission path, and through this transmission path 1, the terminals 2A as each data transmission device exchange data among these plurality of devices. Reference numeral 3A denotes a transmission control device, which is composed of, for example, a one-chip microcomputer, and will be abbreviated as CPU hereinafter. The CPU 3A has two operating modes, a master mode and a slave mode, and switching between them is performed by a switch 18 connected to the switching input terminal 3h.When the switch is on, it is the master machine mode, and when it is off, it is the slave machine mode. mode. Output terminal 3a, - of CPU3A
The output terminal 3b is connected to input terminals 12b and 12a of a selector 12 as signal switching means, respectively. C.P.
Selector 1 connected to polarity control output terminal 3d of U3A
According to the signal of the selector control input terminal 12e of the selector 12, the output terminals 3a, 3 are output to the output terminals 12c, 12d of the selector 12.
The signals obtained in b appear alternately. For example, when the polarity control output terminal 3d is at "H" level, the selector output terminal 12c
The signal from the selector output terminal 3a is output from the selector output terminal 12d.
A signal from one output terminal 3b is outputted to each of the terminals 3b and 3b. Further, when the polarity control output terminal 3d is at the "°L'° level, the one output terminal 3b signal is outputted to the selector output terminal 12C, and the signal of the tenth output terminal 3a is outputted to the selector output terminal 12d.

Output terminals 12c and 12d of the selector 12 are each connected to the base terminal of the transistor 5.4, and output to selector output terminals 12c and 12d, respectively. - The transformer 6 is driven by the signals at the output terminal 3b and the output terminal 3a, and is connected to the collector terminal of the transistor 4.5.

The secondary side of the transformer 6 is connected to the transmission line 1 via a capacitor 7.8, and the above-mentioned signals are output onto the transmission line 1.

On the other hand, the signal on the transmission line 1 is received by a decoding circuit 9 connected to the primary side of the transformer 6 via a capacitor 7.8. The signal appearing on the primary side of the transformer 6 is connected to the coupling resistor 9a of the decoding circuit 9.

It is supplied to comparators 9c and 9d via 9b. 9
e is a signal level comparison voltage dq, and the signal level applied from this is set as a threshold voltage to the comparator 9.
c and 9d waveform-shape the signal appearing on the primary side and output it. 9f is an AND gate that performs the logical product of the outputs of the comparators 9c and 9d, and its output is input to the received signal input terminal 3c of the CPU 3A. Further, 17 is a signal polarity storage circuit as a signal polarity detection means, and a comparator 9c
.

9d are received at input terminals I7a and 17b, respectively. The signal polarity memory circuit 17 stores a signal when either one of the signals applied to the input terminals 17a, 17b goes to "L" level.
The state is outputted to the output terminals 17C and 17d, and the state is held until a reset signal is applied to the reset input terminal 17e. Output terminals 17c and 17d are C
It is connected to polarity input terminals 3e and 3f of PU3A.

A power supply module 13 is connected to the transmission line 1 and steps down the power supply voltage supplied from the transmission line 1 to supply power to the decoding circuit 9 and the signal polarity storage circuit 17.

Reference numeral 14 denotes a signal generating circuit 7) which generates a pulse when the terminal a2A serving as a data transmission device is connected to the transmission line 1 and power supply to the power source module 13 is started. The pulse generated by the reset signal generation circuit 14 is logically ANDed with the reset signal output from the CPU 3A or sent from the cent signal terminal 3g by the AND gate 15, and is applied to the reset input terminal 17e of the signal polarity storage circuit 17. .

16 is a power supply for supplying power to the CP tJ 3 A, the selector 12, and the transistor 4.5; 20 is a transmission line power supply device for supplying power to the transmission line 1;

Next, the operation will be explained. FIG. 2 is a timing diagram showing the operation of each part of the terminal t12A including the signal polarity storage circuit 17. In the figure, terminal device 2 as a data transmission device
When A is connected to the transmission line 1, power is supplied to the power supply module 13 from the transmission line 1, so the reset signal generation circuit 14 generates a pulse as shown in FIG. 2(a).

When the reset pulse is input, the signal polarity storage circuit 17
is initialized, and the polarity input terminals 3e and 3f of the CPU 3A go to the "H" level during the periods TA shown in FIGS. 2(d) and (e). In this state, when the frames shown in FIGS. 8(a) and 8(b) are transmitted so that the start bit is placed on the child line la side of the transmission path 1, the decoding circuit 9 is activated as shown in FIG. A signal as shown in FIG. 3(a) on the transmission line 1 is decoded, and decoding result signals as shown in FIG. 3(d) and (e) are output. This decoding result is also input to the input terminals 17a and 17b of the signal polarity storage circuit 17, and is shown in FIGS.
As shown in the figure, the polarity input terminal 3e of the CPU 3A is “L”.
The level and polarity input terminal 3f becomes the °H°" level, and a start bit appears on the child line la side of the transmission line l. This state is at the reset input terminal 1.7 of the signal polarity storage circuit 17.
It is held until a reset pulse is manually applied to e, or the terminal 2A is disconnected from the transmission line 1 and the power supply from the transmission line 1 is stopped. The above is the basic operation of the signal polarity storage circuit 17.

Next, the operation of the two terminals until the determination of the scratching behavior is performed in two modes (
I will explain about ゛. Firstly, when the mode switching switch 18 is on, that is, in the main unit mode, the fourth
This will be explained based on the flowchart shown in the figure. Now, terminal 2
With A connected to transmission line 1, CP tJ 3
When power is applied to A (step 5TI), CP[
J3A reads the polarity input terminals 3e and 3f (step ST2.5T3), and further reads these polarity input terminals 3e and 3f.
The exclusive OR of 3f is taken and it is determined whether or not it is "'true degree" (step 5T4). If the result is true, it further confirms that the polarity input terminal 3e is “L”, confirms that the polarity has already been determined, and outputs “H” to the polarity control output terminal 3d. ′ is output and the process returns to normal processing. If the polarity is not set, output "H°" to the polarity control output terminal 3d (step 5T5) and operate the selector 12 so that the start bit is output to the child line la side of the transmission line 1. and transmits the determined frame (step 5T6). The transmitted data frame is input to its own input terminal 3c and received, and it is determined whether or not the ■ field has been received normally (step 5T7).
If it is normal, read the polarity input terminal 3e3f (
Steps ST8, 5T9), followed by polarity input terminal 3e,
Take the exclusive OR of 3f (step 5T10), and if the result is "true", further confirm that the polarity input terminal 3e is low (step 5TII), and then,
The process shifts to normal processing (step 5T12). If one field cannot be received normally, if the exclusive OR result is “false”, or if the polarity input terminal 3e is “H”, the CPU 3A sends a reset pulse to the reset signal terminal 3g. In step 5T13), the signal polarity storage circuit 17 is initialized, the frame is transmitted again, and the same operation as above is repeated until the polarity is set normally.

Next, the slave device mode in which the mode changeover switch 18 is turned off will be explained based on the flowchart of FIG. With terminal a2A connected to transmission path 1, C
When the power is turned on to PU3A (step 5T21),
The CPU 3A reads the polarity input terminals 3e and 3f (step ST22゜5T23), calculates the exclusive OR of the polarity input terminals 3e and 3f, and if the result is determined to be true (step 5T24), the polarity input Check the value of the terminal 3e (step 5T25), and if it is L, output °°H'° to the polarity control output terminal 3d so that the start bit is output to the slave line la side of the transmission line 1.Step 5T26 )
, when the polarity input terminal 3e is H", contrary to the above, outputs "L" to the polarity control output terminal 3d so that the start bit is output to the line 1b side of the transmission line 1 (step 5).
T27), the selector 12 is operated to match the polarity of transmission and reception, and the process shifts to normal processing (step 5T28). If the result of the exclusive OR is "'false", the output of the decoding circuit 9 is input to the input terminal 3C, and it is checked whether the data of one field has been received normally (step 5T29).
), when it is detected that the data of one field has been correctly received, the operations from step ST22 onwards are executed again.

Further, if the data in the I field cannot be received normally or if the result of the exclusive OR is "false", the routine does not proceed to normal processing until the polarity can be set normally.

The polarity setting operation is performed as described above. Therefore, as shown in Fig. 6, in a system in which one terminal 2A in master mode and two terminals in slave mode 1 are connected to transmission line 1, the power is turned on all at once. In this case, the polarity is set by the frame transmitted by the terminal 2A in the master mode, and even if only one terminal 2A in the slave mode is powered on later, the polarity is set on the transmission path 1. Polarity is determined by the frame and data can be exchanged. Furthermore, even if the power is cut off midway, each terminal 2A maintains its polarity due to the power supplied from the transmission path 1, so that data transmission can be performed without any problem when the power is turned on again.

In the above embodiment, the terminal 2A in the machine mode 1 outputs the polarity control output terminal 3d so that the start bit of the transmission data is output to the upper line la side of the transmission line 1 during the polarity setting operation. The frame was transmitted by operating the selector 12 by outputting "'H" to ” and transmit the frame by operating the selector 12, the same effect can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, the polarity of the signal on the transmission path is detected by the signal polarity detection means, the polarity of the signal sent out on the transmission path is switched by the signal switching means,
The polarity of the signal is changed to 1 by the transmission control device so that the polarity of the above sending signal is the same as the polarity of the signal on the transmission path.
Since it is configured to be determined by receiving valid field data, it is possible to connect the terminal to the transmission line without checking the signal polarity, and it is possible to prevent problems in the transmission system due to errors during installation work. It has the effect of getting something.

[Brief explanation of the drawing]

FIG. 1 is a block connection diagram showing a data transmission device according to an embodiment of the invention, FIGS. 2 and 3 are timing diagrams showing signals of each part of the data transmission device according to an embodiment of the invention, and FIG. FIG. 5 is a flowchart showing the initial operation of the slave mode 1 of the data transmission device according to the present invention. FIG. 6 is a flowchart showing the initial operation of the slave mode 1 of the data transmission device according to the invention. Fig. 7 is a block connection diagram of the system used. Fig. 7 is a block connection diagram showing a conventional data transmission device. Fig. 8 is an explanatory diagram showing the structure and character structure for transmitting information. FIG. 2 is an explanatory diagram showing the relationship between a transmitted signal and a signal transmitted by a terminal. 1 is a transmission path, 2A is a data transmission device (terminal a), 3A is a transmission control device (CPU), 9 is a decoding circuit, 12 is a signal switching means (selector), 17 is a signal polarity detection means (signal polarity storage circuit) . In addition, in the figures, the same reference numerals indicate the same or equivalent parts. 2゜Figure cc 5・I code

Claims (1)

[Claims] In a data transmission device in which a plurality of terminals that mutually transmit data are connected to a pair of transmission paths, there is provided a signal polarity detection means for detecting the polarity of a signal on the transmission path, and a polarity of the signal sent onto the transmission path. and a transmission control device that determines the polarity of the signal by receiving valid data so that the polarity of the transmitted signal is the same as the polarity of the signal on the transmission path. Data transmission equipment.