JPH02100424A - Interference compensating circuit - Google Patents

Abstract

PURPOSE:To constitute the title circuit so that an interference signal can be eliminated enough even when a signal which becomes the cause of an interference cannot be obtained directly by receiving signals generated by mixing the interference signal into a main signal with regard to plural propagation paths, respectively, and synthesizing these signals by negative phases to each other and equal amplitude. CONSTITUTION:Relative amplitude and the phase difference of a receiving signal received from an auxiliary antenna 4 and a receiving signal distributed form a main antenna 1 are detected by a control circuit 105. Subsequently, a variable amplitude circuit 37 and a variable phase circuit 38 are controlled by its output so that a main signal included in one input of an adder 39 becomes an equal amplitude negative phase against a main signal contained in the other input, the main signals are offset by the output of the adder 39 and only an interference signal is obtained. In such a manner, the interference signal of high purity can be obtained, it is unnecessary to receive directly a signal which becomes the cause of the interference signal, and even if the directions of a main signal source and an interference signal source are the same, the interference signal mixed in the receiving signal can be eliminated with high accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is used for digital or analog signal transmission. In particular, the present invention relates to an interference compensation circuit that removes interference signals from other transmission systems.

[Conventional technology]

FIG. 27 is a block diagram of a conventional interference compensation circuit. This circuit is equivalent to the circuit shown in, for example, Japanese Patent Laid-Open No. 62-147818.

The main signal (here, a digital signal) received by the main antenna 1 for main signal reception includes interference signals from signals of other transmission systems, for example, other transmission methods. This received signal is supplied to a frequency converter 3 via a bandpass filter 2, and is frequency-converted by the frequency converter 3 to an intermediate frequency band.

On the other hand, signals that cause interference are received by directing the auxiliary antenna 4 toward the interference source.

The received signal of the auxiliary antenna 4 is passed through a bandpass filter 2 to improve the signal-to-noise ratio, and then to a local oscillator 5.
The frequency is converted into an intermediate frequency band by the frequency converter 3 using a local oscillation signal common to the main signal side supplied from the main signal side.

The phase and amplitude of this interference signal are adjusted by a variable phase circuit 6 and a variable amplitude circuit 7 to generate a compensation signal having an opposite phase and equal amplitude to the interference component mixed into the main signal.

By adding this compensation signal by the adder 8, the interference signal component mixed into the main signal can be removed.

To control the variable phase circuit 6 and variable amplitude circuit 7,
An error signal and an interference signal are obtained for each in-phase and quadrature component.

The output of the adder 8 is supplied to a demodulator 100 in order to detect the in-phase and quadrature components of the interference components remaining in the main signal after the compensation signal is added by the adder 8.

The quadrature phase detectors 12 and 13 in the demodulator 100 detect the reference carrier 10 reproduced from the main signal with respect to the output of the adder 8.
is used to detect the wave and decompose it into in-phase and quadrature components.

These component signals are processed by harmonic removal filters 14 and 15.
are supplied to error signal generation circuits 101 and 102 via. Error signal generation circuits 101 and 102 detect residual interference components and generate error signals of in-phase and quadrature components, respectively.

On the other hand, the interference signal that has passed through the variable phase circuit 6 is divided into two by a divider 9, one of which is output to the variable amplitude circuit 7, and the other is input to the quadrature phase detector 20.21. The quadrature phase detectors 20 and 21 decompose the interference signal into in-phase components and quadrature components using the reference carrier wave 10 regenerated by the demodulator 100 on the main signal side. The decomposed interference signal is supplied to an identification circuit 24.25 via a harmonic removal filter 22.23. Identification circuit 24.25
each binarizes the interference signal using the timing signal obtained by the main signal demodulator 100.

Since the case where digital processing is performed is explained here, identification circuits 24 and 25 are required for binarization. These are not necessary in case of analog processing.

Furthermore, an analog-to-digital converter can also be used when outputting the outputs of the error signal generation circuits 101 and 102 as digital signals. In that case, for example, if the main signal is a 16QAM signal, the demodulated signal will be a 4-value signal, so it is sampled with an analog-to-digital converter having an output of 3 bits or more. The digital output at that time is shown in the table.

At this time, the top two bits of the digital output indicate the identification result, and the third bit from the top indicates the direction of the error. Therefore, the third bit from the top is used as an error signal. At this time, the most significant bit of the two most significant bits becomes the polarity signal.

(Hereinafter referred to as the margin of this page) The correlations between the in-phase and quadrature components of the error signal and interference signal thus obtained are determined.

That is, the exclusive OR circuits 26 and 27 calculate the exclusive OR of the orthogonal components and the in-phase components, respectively, and supply the outputs to the integrator 30 via the resistors 28 and 29. The output is used as a control signal for the variable amplitude circuit 7. Also, by exclusive OR circuits 31 and 32,
The exclusive OR of the in-phase component and the quadrature component is determined, and the output thereof is supplied to an integrator 35 via resistors 33 and 34, and the output of this integrator 35 is used as a control signal for the variable phase circuit 6.

[Problem that the invention seeks to solve]

However, in the conventional interference compensation circuit, in order to obtain the interference signal, it is necessary to receive the signal that causes the interference signal. That is, it was necessary to provide an auxiliary antenna that receives only signals that cause interference. For this reason, when the propagation paths of the main signal and the interference signal are the same, the signal causing the interference cannot be accurately determined, and the interference signal cannot be removed.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and provide an interference compensation circuit that can sufficiently remove interference signals even when the signal causing the interference cannot be directly obtained.

[Means for solving problems]

The interference compensation circuit of the present invention includes a first receiving circuit that receives a signal in which an interference signal is mixed into the main signal, and a second receiving circuit that is provided in a separate system from the first receiving circuit and receives a signal that includes the interference signal. a first adjusting means for adjusting the amplitude and phase of the output signal of the second receiving circuit; a first subtracting means for subtracting the output of the first adjusting means from the output signal of the first receiving circuit; and a first control means for controlling the first adjusting means so that the interference signal included in the output of the first subtracting means is sufficiently small, the second receiving circuit receives the signal received by the first receiving circuit. The second receiving circuit includes a second adjusting means for adjusting the amplitude and phase of the signal received by the second receiving circuit, and a second adjusting means for adjusting the amplitude and phase of the signal received by the second receiving circuit. a second subtracting means for subtracting the output signal of the first receiving circuit from the output of the second subtracting means; and a second adjusting means for controlling the second adjusting means so that the interference signal included in the output of the second subtracting means has a level sufficiently higher than that of the main signal. The present invention is characterized by comprising two control means.

In this specification, "subtraction" refers to addition in reverse phase. Therefore, when the first adjusting means or the second adjusting means adjusts the phase to the opposite phase, the first subtracting means or the second subtracting means respectively add two signals. Furthermore, "addition" includes in-phase addition and anti-phase addition.

A variable amplitude circuit and a variable phase circuit are used as the first adjustment means and/or the second adjustment means. Moreover, a quadrature amplitude modulator may be used instead of these circuits.

The first adjusting means may be connected to the output of the second subtracting means, or may be connected to the received signal of the second receiving circuit. In the former case, the interference signal is removed from the received signal of the first receiving circuit. In the latter case, the two received signals are added together so that the interference signal is sufficiently small.

Further, the first receiving circuit includes a first quadrature phase detector, and first and second analog-to-digital converters that respectively digitize the in-phase component and the quadrature component output from the first quadrature phase detector. The first adjustment means adjusts the phase of the output signal of the second reception circuit by adjusting the phase of the local oscillation signal used in the first reception circuit and supplying the local oscillation signal to the second reception circuit. The first subtracting means includes an adder disposed upstream of the first quadrature phase detector to combine the received signal of the first receiving circuit and the received signal of the second receiving circuit; The one receiving circuit further includes a second quadrature phase detector, and third and fourth analog-to-digital converters that respectively digitize the in-phase component and the quadrature component output from the second quadrature phase detector. ,
The second receiving circuit includes a third quadrature phase detector, and fifth and sixth analog-to-digital converters that respectively digitize the in-phase component and quadrature component output from the third quadrature phase detector. , the second adjusting means includes first to fourth variable couplers that adjust the phase and amplitude of the outputs of the fifth and sixth analog-to-digital converters, and the second subtracting means includes the third and fourth variable couplers. the second control means includes first to fourth full adders that add the outputs of the first to fourth variable couplers to the outputs of the analog-to-digital converters of the third and fourth analog-to-digital converters; a variable coupler control circuit that controls the first to fourth variable couplers by the output of the converter and the outputs of the fifth and sixth analog-to-digital converters; a fifth to fifth variable coupler for adjusting the phase and amplitude of the outputs of the four analog-to-digital converters; a fifth to fifth full adder for adding the outputs of the fifth to fifth variable combiners;
The first control means is a variable coupler control that controls the fifth to fifth variable couplers by the outputs of the first and second analog-to-digital converters and the outputs of the third and fourth analog-to-digital converters. It can also be configured to include a circuit.

[For production]

The phase difference between the main signal and the interference signal via one propagation path is usually different from the phase difference between the main signal and the interference signal via another propagation path. Therefore, signals in which the main signal is mixed with the interference signal are received for each of the plurality of propagation paths. By combining these signals with mutually opposite phases and equal amplitude, a highly pure interference signal can be obtained. Using this interference signal, the interference signal component is removed from the received signal.

If the propagation path is a wireless transmission path, an antenna is provided for each propagation path. However, it is not necessary to point these antennas in different directions. For example, if the interference signal source is in the same direction as the main signal source, a plurality of antennas are directed in the same direction and each receives the main signal mixed with the interference signal.

〔Example〕

FIG. 1 is a block diagram of an interference compensation circuit according to a first embodiment of the present invention.

This interference compensation circuit is equipped with a main antenna 1 and its output circuit as a first receiving circuit that receives a signal in which an interference signal is mixed into a main signal, and is provided in a separate system from this first receiving circuit to receive a signal containing an interference signal. The second receiving circuit is equipped with an auxiliary antenna 4 and its output circuit, and the second receiving circuit is equipped with a variable amplitude circuit 41 and a variable phase circuit 42 as first adjusting means for adjusting the amplitude and phase of the output signal of the second receiving circuit. An adder 40 is provided as a first subtraction means for subtracting the output of the first adjustment means from the output signal of the first receiving circuit, and the variable amplitude circuit 41 and a control circuit 106 that controls the variable phase circuit 42.

Here, the feature of this embodiment is that the auxiliary antenna 4
However, it is configured to receive a signal via a propagation path different from the signal received by the main antenna 1, and the output circuit of the auxiliary antenna 4 includes a second antenna that adjusts the amplitude and phase of the signal received by the auxiliary antenna 4. A variable amplitude circuit 37 and a variable phase circuit 38 are provided as adjustment means, and an adder 39 is provided as a second subtraction means for subtracting the output signal of the first receiving circuit from the output of the second adjustment means. The control circuit 105 controls the variable amplitude circuit 37 and the variable phase circuit 38 so that the interference signal contained in the main signal has a sufficiently higher level than the main signal.

The main antenna 1 and the auxiliary antenna 4 are each directed toward the main signal transmission source. Here, it is assumed that the main signal is a digital signal. In this case the interference sources are also in the same direction. Therefore, the main antenna 1 and the auxiliary antenna 4 simultaneously receive the main signal and the interference signal.

The received signal of the main antenna 1 is distributed and supplied to one of the adders 39 . Further, the received signal of the auxiliary antenna 4 is supplied to the other input of the adder 39 via the variable amplitude circuit 37 and the variable phase circuit 38.

Here, in order to extract the interference signal from the output of the adder 39, it is sufficient that the main signal included in one input of the adder 39 has equal amplitude and opposite phase to the main signal included in the other input. . Therefore, the relative amplitude and phase difference between the received signal received from the auxiliary antenna 4 and the received signal distributed from the main antenna 1 are detected by the control circuit 105, and the output thereof is used to control the variable amplitude circuit 37 and the variable phase circuit 38. Control. As a result, the main signal is canceled out and only the interference signal is obtained in the output of the adder 39.

Using the interference signal extracted as described above, the interference signal mixed into the main signal is removed. This method will be explained.

The interference signal output from the adder 39 is sent to the variable phase circuit 4
2 and a variable amplitude circuit 41 to one input of an adder 40. Moreover, the received signal of the main antenna 1 is supplied to the other input terminal of the adder 40 . Here, in order to remove the interference signal from the output of the adder 40, the adder 4
The interference signals at the two inputs of 0 are made to have equal amplitudes and opposite phases.

Therefore, the control circuit 106 detects the relative amplitude difference and phase difference between the interference signal output from the adder 39 and the interference component in the received signal of the main antenna 1, and determines whether the interference signal and the interference component are equal. The variable phase circuit 42
and controls the variable amplitude circuit 41.

In this way, an interference signal can be automatically extracted from a signal mixed with an interference signal, and interference compensation can be automatically performed using the interference signal.

FIG. 2 is a block diagram of an interference compensation circuit according to a second embodiment of the present invention. This embodiment differs from the first embodiment in that a wired transmission line 1' is used instead of the main antenna 1 and the auxiliary antenna 4. That is, the present invention can be applied not only to wireless signals but also to wired signals.

In the above embodiments, the circuit configurations have been simplified in order to explain the present invention in detail. More specific configurations will be explained in the following examples.

FIG. 3 is a block diagram of an interference compensation circuit according to a third embodiment of the present invention.

This interference compensation circuit includes a main antenna 1, a bandpass filter 2, a frequency converter 3, and a local oscillator 5 as a first receiving circuit that receives a signal in which an interference signal is mixed into the main signal. A second receiving circuit which is provided in a separate system and receives a signal including an interference signal includes an auxiliary antenna 4, a bandpass filter 2, a frequency converter 3, and a local oscillator 5 common to the first receiving circuit. A variable phase circuit 6' and a variable amplitude circuit 7' are provided as first adjustment means for adjusting the amplitude and phase of the output signal of the first adjustment means, and a first subtraction method for subtracting the output of the first adjustment means from the output signal of the first receiving circuit. A phase detector 21 is provided as a first control means for controlling the variable phase circuit 6' and the variable amplitude circuit 7' so that the interference signal included in the output of the first subtraction means becomes sufficiently small. Harmonic removal filter 2
3. Identification circuit 25, demodulator 100 and correlation detection circuit 1
Equipped with 07.

The auxiliary antenna 4 receives a signal via a different propagation path than the signal received by the main antenna 1.

The second reception circuit further includes a variable phase circuit 6 and a variable amplitude circuit 7 as second adjustment means for adjusting the amplitude and phase of the signal received by the auxiliary antenna 4, and the output of the second adjustment means is used to adjust the amplitude and phase of the signal received by the auxiliary antenna 4. An adder 8' is provided as a second subtraction means for subtracting the output signal of the circuit, and the variable phase circuit 6 and the variable amplitude circuit are arranged so that the interference signal contained in the output of the adder 8' has a sufficiently higher level than the main signal. A second control means for controlling the second control means 7 includes a quadrature phase detector 108, a correlation detection circuit 109, and a phase detector 21, a harmonic removal filter 23, and an identification circuit 25, which are common to the first control means.

The main antenna 1 and the auxiliary antenna 4 are directed towards a transmission source that transmits a main signal in digital form. An interference signal leaks into this main signal. Received signals from the main antenna 1 and the auxiliary antenna 4 are supplied to a frequency converter 3 via a bandpass filter 2 for improving S/N. The frequency converter 3 converts each received signal into an intermediate frequency band using a local oscillation signal supplied from a common local oscillator 5.

The signals converted to the intermediate frequency band are sent to a distributor 9.
9' is manually operated. One output of the distributor 9 is sent to the adder 8'
One output of the distributor 9' is input to the variable amplitude circuit 7.
and is inputted via the variable phase circuit 6 to the adder 8'. The variable amplitude circuit 7 and the variable phase circuit 6 are connected to an adder 8'
The main signal components included in the two inputs are feedback-controlled so that they have equal amplitudes and opposite phases. As a result, the main signal component is significantly attenuated in the output of the adder 8'.
The interference signal that leaked into the main signal can be obtained.

This feedback control is performed as follows.

Two main signals received by the main antenna 1 and the auxiliary antenna 4 are added by an adder 8' so that they have opposite phases and equal amplitudes. After this addition, correlation detection is performed between the remaining main signal component and the main signal before addition, and the variable amplitude circuit 7 and the variable phase circuit 6
and adjust amplitude and phase. By dere,
The main signal remaining after synthesis can always be minimized.

Furthermore, regarding the main signal remaining after the addition, the main signal is 1 when the interference compensation operation is started. However, as the interference compensation operation progresses to a steady state, the interference signal component contained in the main signal emerges and is output from the adder 8' as an interference signal.

Specifically, using the reference carrier 10 regenerated by the demodulator 100 on the main signal side, the output of the adder 8', that is, the interference signal remaining after removing the main signal, is sent to the phase detector 21.
Phase detection is performed by the harmonic removal filter 23, harmonic components are removed by the harmonic removal filter 23, and the output of the harmonic removal filter 23 is reproduced by the demodulator 100 or binarized by the identification circuit 25 using the lock signal 36. Thereby, a binarized interference signal is obtained.

The other output of the divider 9' is input to a quadrature phase detector 108 which decomposes the signal into an in-phase component and a quadrature component. This input is phase detected using the reference carrier wave 10 by a quadrature phase detector 20.21. This phase detection output is binarized by identification circuits 24' and 25' after harmonic components are removed by harmonic removal filters 22 and 23. Thereby, binarized main signals of the in-phase component and the quadrature component are obtained. Here, identification circuit 2
4' and 25' are binarized using the clock signal 36 reproduced by the demodulator 100.

The exclusive OR circuit 27 digitally multiplies the main signal of the in-phase component obtained from the identification circuit 25' and the residual main signal (interference signal) output from the identification circuit 25 which has a relatively in-phase relationship. , the results are integrated by an integrator 30. The variable amplitude circuit 7 is controlled by the output of the integrator 30.

Similarly, the main signal of the orthogonal component outputted from the identification circuit 24' and the residual main signal (interference signal) outputted from the identification circuit 25, which is in a relatively orthogonal relationship thereto, are processed by the exclusive OR circuit 31. Digitally multiplies the result and integrator 35
Integrate by. The variable phase circuit 6 is controlled by the output of the integrator 35.

The identification circuits 25, 24' and 25' are provided to ensure the operation of the exclusive OR circuit 31, and are not necessarily necessary.

As described above, it is possible to automatically extract the interference signal mixed into the main signal and cancel this interference signal. In this case, a delay circuit is provided in at least one signal path so that the delay times of the two main signals in the adder 8' match.

Next, this interference signal is used to cancel the interference component remaining in the received signal of the main antenna 1. That is, using the interference signal obtained by the above operation, the variable phase circuit 6'
and variable amplitude circuit 7' are sequentially controlled, and adder 8 adds the output of variable amplitude circuit 7' to the other output of divider 9. At this time, the output signal of the variable amplitude circuit 7' is controlled so that it has approximately the opposite phase and the same amplitude as the interference signal component mixed into the main signal output from the distributor 9.

Therefore, the interference signal component is removed from the output of the adder 8.

Control of the variable phase circuit 6' and variable amplitude circuit 7' will be explained below.

The main signal combined by adder 8 is input to demodulator 100. In the demodulator 100, using the reference carrier wave 10 regenerated from the main signal, quadrature detection is performed on the main signal by quadrature phase detectors 12.13, and the output signals are passed through harmonic removal filters 14.15. and obtain orthogonal baseband signals. The obtained baseband signals are input to error signal generation circuits 101 and 102, respectively. The error signal generation circuits 101 and 102 each consist of an identification circuit 16 and 18 and a subtracter 17 and 19 that takes the difference between the input and output.
An error signal is output from.

Note that when a 16 QAM signal is used as the main signal, a 3-bit or more analog-to-digital converter can also be used as the error signal generation circuit. 16 Q
When the AM signal is demodulated, a four-level baseband signal is obtained. When this 4-value signal is passed through an identification circuit (analog-to-digital conversion circuit) that has an output of 3 bits or more,
As shown in the table above, the top two bits of the output are the identification signal and the third bit from the top is the error signal.
An error signal can be obtained from the third and subsequent bits from the top.

On the other hand, the interference signal outputted from the adder 8' and passed through the distributor 9 is phase-detected by the phase detector 21 using the reference carrier wave 10, harmonic components are removed by the harmonic removal filter 23, and the discriminator circuit It is binarized by 25. This results in a binary interference signal. In addition, the identification circuit 2
5 executes a binarization operation using the clock signal 36 reproduced by the demodulator 100.

Next, correlation detection is performed between the in-phase and quadrature component error signals obtained by the demodulator 100 and the interference signal binarized by the identification circuit 25. That is, the error signal of the in-phase component and the interference signal are digitally multiplied by the exclusive OR circuit 27, the output thereof is integrated by the integrator 30, and the variable amplitude circuit 7' is controlled by the output. On the other hand, the error signal of the orthogonal component and the interference signal are digitally multiplied by the exclusive OR circuit 31, the output thereof is integrated by the integrator 35, and the variable phase circuit 6' is controlled by the output signal.

In this way, interference compensation can be performed automatically. Here, binary multiplication using exclusive OR circuits 27 and 31 is shown as an example, but a binarization circuit for the interference signal is not necessarily necessary, and in that case, analog multiplication can be used instead of the exclusive OR circuit. Use a container.

FIG. 4 is a block diagram of an interference compensation circuit according to a fourth embodiment of the present invention.

This embodiment differs from the third embodiment in that a quadrature amplitude modulator is used instead of a variable amplitude circuit and a variable phase circuit to control the amplitude and phase of the main signal and the amplitude and phase of the interference signal. . That is, the quadrature amplitude modulator 111 is provided as a first adjusting means for adjusting the amplitude and phase of the output signal of the second receiving circuit, and the second adjusting means adjusts the amplitude and phase of the signal received by the second receiving circuit. A quadrature amplitude modulator 110 is provided as a quadrature amplitude modulator.

The quadrature amplitude modulator 110 is a distributor 4 that distributes the human input signal.
3 and 9 which shifts the phase of one of the outputs of this distributor 43 by 90 degrees.
0" phase shifter 11, a π/2 phase bipolar variable attenuator 45 that adjusts the amplitude of the output of this phase shifter 11, and a zero phase bipolar variable attenuator 45 that adjusts the other amplitude of the output of the divider 43. variable attenuator 4
6, and an adder 44 that combines the outputs of bipolar variable attenuators 45 and 46.

Similarly, the quadrature amplitude modulator 111 has a divider 43 and a divider 90.
It is composed of a phase shifter 11, bipolar variable attenuators 45 and 46, and a synthesizer 44.

Zero-phase bipolar variable attenuator 46 in quadrature amplitude modulator 110
is controlled by the output of the integrator 30 of the correlation detection circuit 109, and the π/2 phase bipolar variable attenuator 45 is controlled by the output of the integrator 30 of the correlation detection circuit 109.
Controlled by the output of 5.

Zero-phase bipolar variable attenuator 46 in quadrature amplitude modulator 111
Similarly, the π/2-phase bipolar variable attenuator 45 is controlled by the outputs of the integrators 30 and 35 in the correlation detection circuit 107, respectively.

FIG. 5 is a block diagram of an interference compensation circuit according to a fifth embodiment of the present invention.

This embodiment differs from the fourth embodiment in that control gain is obtained by performing analog multiplication using multipliers 47 and 48 instead of using an exclusive OR circuit for correlation detection.

FIG. 6 is a block diagram of an interference compensation circuit according to a sixth embodiment of the present invention.

This embodiment differs from the fourth embodiment in that analog-to-digital converters 49.50.51.52.53 are used in place of the error signal generation circuits 101.102 and identification circuits 25.24' and 25'. different.

When considering 16 Q A M as the main signal, if an analog-to-digital converter with an output of 3 bits or more is used as shown in the table above, the upper 2 bits of the output will indicate the identification result. , the third bit from the top represents an error signal. Therefore, the error signal can be obtained using the third and subsequent bits from the top.

The analog-to-digital converters 49 to 53 sample their respective input signals using the clock signal 36 reproduced by the main signal demodulator 100. The first bit (polarity signal) from the top of the output of the analog-digital converter 51 that converts the baseband signal of the interference signal into a digital signal, and the third bit (error signal) from the top of the analog-digital converter 49,50. (signal), and the bipolar variable attenuators 45 and 46 of the quadrature amplitude modulator 111 are controlled by the correlation signal. This eliminates the interference signal.

On the other hand, a quadrature phase detector 1 connected to the output of the divider 9'
The analog/digital converters 52 and 53 of 08 each output the first bit (polarity signal) from the top of the orthogonal component and the in-phase component. A correlation is detected between this signal and the first bit of the analog-to-digital converter 51, and the bipolar variable attenuators 45 and 46 of the orthogonal amplitude modulator 110 are controlled by the correlation signal, and the signal is mixed into the main signal. Extract the interference signal.

FIG. 7 is a block diagram of an interference compensation circuit according to a seventh embodiment of the present invention.

In this embodiment, in order to binarize the extracted interference signal,
In order to binarize the output of the divider 9' by using a quadrature phase detector 108 instead of a phase detector, a phase detector 21 and an identification circuit 25' are used instead of a quadrature phase detector, and each correlation detection is performed. This embodiment differs from the third embodiment in that the following steps are performed.

Furthermore, although the configuration of the correlation detection circuit 107 is slightly different, it is the same configuration as the control circuit 104 shown in the conventional example.

FIG. 8 is a block diagram of an interference compensation circuit according to an eighth embodiment of the present invention.

This embodiment differs from the third embodiment in that quadrature phase detectors 20 and 21 are used to binarize the extracted interference signal. This configuration increases the circuit scale compared to the third embodiment, but doubles the control gain and improves control responsiveness.
This has the advantage of good convergence.

The configuration of the correlation detection circuit 107 is the same as that of the seventh embodiment.

FIG. 9 is a block diagram of an interference compensation circuit according to a ninth embodiment of the present invention.

This embodiment differs from the fourth embodiment in that instead of the auxiliary antenna 4, an auxiliary antenna 55 for space diversity reception is shared. As a result, a new auxiliary antenna 4
There is no need to install antennas, making antenna installation more efficient and economical.

Note that the phase shifter 56 is a phase shifter that adjusts the space diversity synthesis phase.

FIG. 10 is a block diagram of an interference compensation circuit according to a ninth embodiment of the present invention.

This embodiment differs from the ninth embodiment in that the main antenna 1 and the sub antenna 55 are shared by an angle diversity receiving antenna 57. As a result, one angle diversity receiving antenna 57 is used in contrast to the two antenna configurations of the ninth embodiment, so that the antenna configuration can be significantly miniaturized.

FIG. 11 is a block diagram of an interference compensation circuit according to a ninth embodiment of the present invention.

This embodiment differs from the fourth embodiment in that the quadrature amplitude modulator 110 is replaced with a transversal filter (an example of a 3-tap configuration) 112. With this configuration, even if the received signal of the main antenna 1 or the received signal of the auxiliary antenna 4 has frequency characteristics, it is possible to cancel the main signal and extract the interference signal.

The transversal filter 112 extracts the interference signal mixed into the main signal by the following operation.

The main signal that has passed through the divider 9' of the reception system of the auxiliary antenna 4 is input to a quadrature amplitude modulator consisting of a delay line with multiple taps, that is, a two-dimensional transversal filter 112, which converts the main signal with frequency characteristics. Amplitude and phase are controlled. This transversal filter 112 further divides one signal output from the divider 9' by a divider 58, supplies one output to a bipolar variable attenuator 59 that controls the in-phase component, and supplies the other output to a bipolar variable attenuator 59 that controls the in-phase component. The output is supplied to a bipolar variable attenuator 60 that relatively controls the orthogonal components, and the outputs of the bipolar variable attenuators 59 and 60 are respectively input to an adder 61 and added.

The output of the distributor 58 is further divided into a data clock period T (or an integer multiple thereof, or [1/1/2
The signal passes through a delay circuit 63 that delays the signal by an integer multiple, and is distributed by the same distributor 58 as described above. This distributor 58
One of the signals distributed by is supplied to a bipolar variable attenuator 59 that controls the in-phase component. The other signal is fed to a bipolar variable attenuator 60 that controls the quadrature component. The outputs of these bipolar variable attenuators 59 and 60 are sent to the adder 6
It is added by 1 and output.

Further, the signals delayed by 2T by the two delay circuits 63 are similarly distributed by the distributor 58, the in-phase component is controlled by the bipolar variable attenuator 59, the orthogonal component is controlled by the bipolar variable attenuator 60, Bipolar variable attenuator 5
9.600 control outputs are added by the adder 61 and output. Each output of the adder 61 is combined by a 90° combiner 62 and output.

On the other hand, the received signal on the main antenna 1 side is distributed by the distributor 9, and inputted to the adder 8' via the delay circuit 63.
It is added to the output of the 90° synthesizer 62.

The delay circuit 63 is for correcting the delay time of the signal to the same delay time T as the center tap of the transversal filter 112.

The two main signals input to the adder 8' have opposite phases and equal amplitudes, and are converted into the same frequency characteristics, so that by adding them together, only the interference signal is extracted.

In this way, by using the transversal filter 112 to add the frequency characteristics of the main signal received from the main antenna 1 and the frequency characteristics of the main signal received from the auxiliary antenna 4 with opposite phases and equal amplitudes, , the main signal is significantly attenuated, and the interference components contained within it become prominent.

In order to control each weight amount of the transversal filter 112, the main signal remaining after adding the two signals,
In other words, correlation detection is performed between the interference signal and one of the main signals before addition, and each weighting is performed so that the amount of correlation is minimized, that is, the amount of the main signal after addition is minimized. The circuit (bipolar variable attenuator 59, 60) is feedback-controlled.

This operation will be specifically explained.

The output of the adder 8' is distributed by a distributor 9 and input to a phase detector 21. This phase detector 21 uses the reference carrier wave 10 regenerated by the main signal demodulator 100 to perform phase detection on the signal from the distributor 9 . The harmonic components of this detection output are removed by the harmonic removal filter 23, and the tarokk signal 36 regenerated by the demodulator 100 is used to pass the signal to the discriminator 2.
It is binarized by 5. As a result, the binary interference signal a
is obtained.

Further, the received signal of the auxiliary antenna 4 is distributed by a distributor 9'. One output of the divider 9' is supplied to the quadrature phase detector 108 via a delay circuit 63 for correcting the same delay time T as the center tap of the transversal filter 112, and further via a delay line τ2. Ru. This signal is generated by using the reference carrier wave 10 regenerated by the demodulator 100.
Phase detection is performed by quadrature phase detectors 20 and 21.

The detected output has harmonic components removed by harmonic removal filters 22 and 23, and is binarized by identification circuits 24' and 25' using the clock signal 36 regenerated by the demodulator 100. As a result, the binary main signal in-phase component a1
and the main signal orthogonal component a, are obtained.

The binarized interference signal a and the binarized main signal in-phase component a1 and main signal orthogonal component a are input to the transversal filter control circuit 113. Output C−+ (=x−
1+ J y−+) , Co (=Xo +J Vo
), C, + (=X, ++J V-+), each bipolar variable attenuator 5 of the transversal filter 112
9.60 is controlled.

FIG. 12 shows the circuit configuration of the transversal filter control circuit 113.

For example, a signal X- controlling a bipolar variable attenuator 59.

is generated as follows. Exclusive OR circuit 64
The binarized interference signal a is input to one input terminal of the , and the binarized main signal in-phase component a is input to the other input terminal.
, is manually inputted by the delay circuit 63 by a delay of T. Exclusive OR circuit 64 multiplies these inputs, and integrator 65 integrates its output. Thereby, a correlation is detected, and according to the obtained output x-r, the bipolar variable attenuator 5 associated with the in-phase component of the transversal filter 112
Control 9.

Similarly, the interference signal a and the binarized main signal orthogonal component a
, and the signal delayed by T by the delay circuit 63 are input to the exclusive OR circuit 64 and multiplied, and then integrated by the integrator 65, and its output 'l-+ is related to the orthogonal component of the transversal filter 112. Bipolar variable attenuator 60
control.

Similarly, each bipolar variable attenuator 59, 60 is controlled by control signals c-, , Co, and C1, respectively.

As a result, the output of the 90° combiner 62 is transmitted to the main signal distributor 9
The output and frequency characteristics match, and they have equal amplitude and opposite phase. Therefore, even if the two received human signals have different frequency characteristics, by combining them, the main signal is almost completely erased, and the remaining interference component stands out. This is output from the adder 8' as an interference signal.

In this embodiment, it is necessary to adjust the relative timing using the delay lines τ1 and T2 to maximize the compensation effect. Further, it is necessary to manually match the relative delay times between the two main signals in the adder 8'.

Note that although the number of taps of the transversal filter is three taps as an example, if the number is increased, the accuracy of extraction of the interference signal can be further improved.

FIG. 13 shows a block diagram of an interference compensation circuit according to a thirteenth embodiment of the present invention.

In this embodiment, the delay time of the delay circuit 13 of the transversal filter 112 is 1/2 of the data clock period T.
At the same time, the delay time of the delay circuit 63' of the transversal filter control circuit 113' becomes T/
This embodiment differs from the thirteenth embodiment in that the number is 2. With such a configuration, it is possible to prevent the compensation effect from deteriorating even if the relative delay times between the two main signals in the adder 8' are not matched.

In this embodiment, a T/2 delay circuit 63' is shown, but a delay circuit 63' that is an integer of T can be similarly implemented.

FIG. 14 shows a circuit configuration of a transversal filter control circuit 113' using a T/2 delay circuit 63'.

FIG. 15 shows a block diagram of an interference compensation circuit according to a thirteenth embodiment of the present invention.

In order to cancel the interference signal mixed into the main signal, this embodiment does not adjust the amplitude and phase of the interference signal using a single-tap quadrature amplitude modulator 111, but uses a transformer consisting of a plurality of tapped delay lines. This embodiment differs from the thirteenth embodiment in that a versal filter 114 is used. With this configuration,
Even when the interference signal is a broadband signal and has frequency characteristics, an interference compensation circuit that can sufficiently remove the interference signal can be obtained.

In FIG. 15, the interference signal output from the adder 8' is passed through the transversal filter 114 to the adder 8'.
supplied to The transversal filter l14 and the transversal filter control circuit 115 have the same configuration as the transversal filter 112 and the transversal filter control circuit 113 described above.

FIG. 16 shows a block configuration diagram of an interference compensation circuit according to a thirteenth embodiment of the present invention, and FIG. 17 shows a circuit configuration of a transversal filter control circuit 115'.

In this embodiment, instead of the transversal filter 112, 114 and the transversal filter control circuit 113, 115 that controls it in the thirteenth embodiment,
Transversal filter 112 shown in the thirteenth embodiment
' and transversal filter control circuit 113'
(The transversal filter 114' has the same configuration as the transversal filter 113) and is different from the thirteenth embodiment in that a transversal filter control circuit 115' is used.

Moreover, the transversal filter 112 of the thirteenth embodiment
In place of , transversal filter 1 of the fourteenth embodiment
12' and correspondingly a transversal filter control circuit 113'. or,
In place of the transversal filter 114 of the thirteenth embodiment, the transversal filter 114' of the fourteenth embodiment
It is also possible to use a transversal filter control circuit 115' correspondingly.

FIG. 18 shows a block diagram of an interference compensation circuit according to a thirteenth embodiment of the present invention.

This embodiment differs from the first embodiment in that the amplitude and phase of the interference signal component contained in the signal received by the auxiliary antenna 4 is adjusted to cancel the interference signal contained in the signal received by the main antenna 1.

This interference compensation circuit is equipped with a main antenna 1 and its output circuit as a first receiving circuit that receives a signal in which an interference signal is mixed into a main signal, and is provided in a separate system from this first receiving circuit to receive a signal containing an interference signal. The second receiving circuit is equipped with an auxiliary antenna 4 and its output circuit, and the second receiving circuit is equipped with a variable amplitude circuit 41 and a variable phase circuit 42 as first adjusting means for adjusting the amplitude and phase of the output signal of the second receiving circuit. An adder 40 is provided as a first subtraction means for subtracting the output of the first adjustment means from the output signal of the first receiving circuit, and a variable amplitude circuit 41 is provided so that the interference signal included in the output of the adder 40 is sufficiently small. A control circuit 106 is provided as a first control means for controlling the variable phase circuit 42.

Here, the feature of this embodiment is that a variable amplitude circuit 37 and a variable phase circuit 38 are provided in the output circuit of the auxiliary antenna 4 as second adjustment means for adjusting the amplitude and phase of the signal received by the auxiliary antenna 4. An adder 39 is provided as a second subtraction means for subtracting the output signal of the first receiving circuit from the output of the second adjustment means, and the interference signal contained in the output of the adder 39 is at a level sufficiently higher than the main signal. The reason is that the control circuit 105 is provided as a second control means for controlling the variable amplitude circuit 37 and the variable phase circuit 38 so that the variable amplitude circuit 37 and the variable phase circuit 38 are controlled.

A method for eliminating interference signals mixed in the main signal will be described below.

In order to eliminate the interference signal from the output of the combiner 40, a variable amplitude circuit is used so that the interference signal in the auxiliary antenna 4 reception signal has the same amplitude and opposite phase to the interference signal in the main antenna 1 reception signal. 41 and variable phase circuit 42.

Therefore, the control circuit 106 detects the correlation between the interference signal output from the adder 39 and the interference component included in the output of the adder 40, and so that the interference component is eliminated.
The variable amplitude circuit 41 and the variable phase circuit 42 are controlled.

Note that in order to make the main signal power to interference signal power (D/U) ratio at the output of the adder 40 larger than the D/U ratio at the input of the main antenna 1 or the auxiliary antenna 4, the variable amplitude circuit 41 is connected to the auxiliary antenna. 4 side as well as the main antenna 1
It can also be inserted into the side or both the main antenna 1 side and the auxiliary antenna 4 side.

As described above, it is possible to automatically compensate for interference signals mixed in the main signal.

A specific example of this embodiment will be shown below.

FIG. 19 is a block diagram of an interference compensation circuit according to a sixteenth embodiment of the present invention.

The signals received from the main antenna 1 and the auxiliary antenna 4 are processed by a frequency converter 3 using a local oscillation signal from a common local oscillator 5 after passing through a bandpass filter 2 to improve the signal-to-noise ratio. Each is converted to an intermediate frequency.

The signals converted to the intermediate frequency band are sent to a distributor 9.
9' is input. One output of the distributor 9 is input to the adder 8 . One output of the distributor 9' is connected to the distributor 66,
The signal is input to the adder 8' via the variable amplitude circuit 72 and the variable phase circuit 6'.

The variable amplitude circuit 7' and the variable phase circuit 6' are connected to a distributor 9.
Feedback control is performed so that one main signal output from the distributor 9' has equal amplitude and opposite phase to the other output main signal. As a result, at the output of the adder 8', the main signal output is significantly attenuated, and an interference signal mixed into the main signal is obtained.

Next, the auxiliary antenna 4 responds to the interference signal in the main antenna 1.
Control so that the interference signals therein have equal amplitude and opposite phases, that is, control of the variable phase circuit 6 and the variable amplitude circuit 7 will be explained.

The main signal combined by adder 8 is input to demodulator 100. In the demodulator 100, the main signal is orthogonally detected by the quadrature phase detector 12.13 using the reference carrier wave lO regenerated from the main signal, and the output signals are passed through harmonic removal filters 14, 15, respectively. Obtain orthogonal baseband signals.

The obtained baseband signals are input to error signal generation circuits 101 and 102, respectively. Error signal generation circuit 10
1.102 each comprises an identification circuit 16.18 and a subtracter 17.19 that takes the difference between the input and output, and error signals are output from these subtracters 17.19.

On the other hand, the interference signal output from the adder 8' is phase-detected by a phase detector 21 using a reference carrier wave 10, harmonic components are removed by a harmonic removal filter 23, and then a binary signal is passed through an identification circuit 25. be converted into This results in a binary interference signal. The identification circuit 25 performs a binarization operation using the clock signal 36 reproduced by the main signal demodulator 100.

Next, correlation detection is performed between the in-phase and quadrature component error signals obtained by the demodulator 100 and the binarized interference signal. That is, the error signal of the in-phase component and the interference signal are digitally multiplied by the exclusive OR circuit 27, the output thereof is integrated by the integrator 30, and the variable amplitude circuit 7 is controlled by the output. On the other hand, the error signal of the orthogonal component and the interference signal are digitally multiplied by the exclusive OR circuit 31, the output thereof is integrated by the integrator 35, and the variable phase circuit 6 is controlled by the output signal.

In this way, interference compensation can be performed automatically.

FIG. 20 is a block diagram of an interference compensation circuit according to a seventeenth embodiment of the present invention.

In this embodiment, when controlling the amplitude phase of the received signal of the auxiliary antenna 4, the variable amplitude circuit and the variable phase circuit were used respectively in the 16th embodiment, but in this embodiment, a quadrature amplitude modulator is used in that part. The use is different from the sixteenth embodiment.

That is, in the sixteenth embodiment, the variable amplitude circuit 7.7' and the right and variable phase circuits 6.6' are controlled by the correlation output from the integrator 30.35, respectively. In contrast, in this embodiment, the equivalent operation is performed using quadrature amplitude modulators 110 and 111.

The quadrature amplitude modulator 110 is a distributor 4 that distributes the input signal.
3 and 9 which shifts the phase of one of the outputs of this distributor 43 by 90 degrees.
A 0° phase shifter 11, a π/2-phase bipolar variable attenuator 45 that adjusts the amplitude of the output of the 90° phase shifter 11, and a zero-phase bipolar variable attenuator 45 that adjusts the amplitude of the other output of the distributor 43. It consists of a bipolar variable attenuator 46 and an adder 44 that adds the outputs of the bipolar variable attenuators 45 and 46.

Similarly, the quadrature amplitude modulator 111 has a divider 43 and a divider 90.
It is composed of a phase shifter 11, bipolar variable attenuators 45 and 46, and an adder 44.

Zero-phase bipolar variable attenuator 46 in quadrature amplitude modulator 110
is controlled by the output of the integrator 30 of the correlation detection circuit 109. The π/2 phase bipolar variable attenuator 45 is controlled by the output of the integrator 35.

The zero-phase bipolar variable attenuator 46 and the π/2-phase bipolar variable attenuator 45 in the other quadrature amplitude modulator 111 are similarly controlled by the outputs of the integrators 30 and 35 in the correlation detection circuit 107, respectively. be done.

FIG. 21 is a block diagram of an interference compensation circuit according to a tenth embodiment of the present invention.

In this embodiment, whereas the seventeenth embodiment used quadrature amplitude modulators 110 and 111 to control the amplitude and phase of the received signal of the auxiliary antenna 4, transversal filters 112 . This embodiment differs from the seventeenth embodiment in that 114 is used. With this configuration, even if the received signal of the main antenna 1 or the auxiliary antenna 4 has frequency characteristics, it is possible to eliminate interference signals mixed in the received signal. Note that the transversal filter 112
．． The configuration of 114 and the configurations of transversal filter control circuits 113 and 115 are equivalent to those shown in FIG. 11, FIG. 12, or FIG. 15.

FIG. 22 is a block diagram of an interference compensation circuit according to a nineteenth embodiment of the present invention.

This embodiment is a transversal filter 112.114 and its control circuit 113.1 in the tenth embodiment.
This embodiment differs from the tenth embodiment in that transversal filters 112', 114' and their control circuits 113' and 115' used in the fourteenth embodiment are used instead of the delay circuit 63 of No. 15.

FIG. 23 is a block diagram of an interference compensation circuit according to a second embodiment of the present invention.

This embodiment circuit includes, as part of the first receiving circuit, a first quadrature phase detector 12,13;
．． a first and a second analog-to-digital converter 49,50 for digitizing the in-phase component and the quadrature component outputted by the first adjusting means, respectively; The phase shifter 5 adjusts the phase of the output signal of the second receiving circuit by adjusting the phase of the oscillation signal and supplying the local oscillation signal to the second receiving circuit. An adder 8 is provided upstream of the first quadrature phase detector 12.13 to combine the received signal of the first receiving circuit and the received signal of the second receiving circuit. Quadrature phase detector 2
0.21, and third and fourth analog-to-digital converters 51 and 51' for digitizing the in-phase component right and the quadrature component output from the quadrature phase detector 20.21, respectively, and further as a second receiving circuit. , a third quadrature phase detector 20', 21', and this quadrature phase detector 20',
and fifth and sixth analog-to-digital converters 52.53 for digitizing the in-phase component and quadrature component outputted by the converter 21', respectively. First to fourth variable couplers 67 to 70 that adjust phase and amplitude
It is equipped with first to fourth full adders 71 to 74 for adding the outputs of the variable couplers 67 to 70 to the outputs of the analog-to-digital converters 51 and 51' as second subtraction means, and a second subtraction means. As a means, an analog-to-digital converter 5
The outputs of 1.51' and 52.53 connect variable couplers 67~
The variable coupler control circuit 117 controls the analog-to-digital converter 5 as the first adjusting means.
1.51' and variable couplers 75 to 78 for adjusting the phase and amplitude of the output of the analog-to-digital converter 49.50. It is equipped with fifth to fifth full adders 79 to 82 that add the outputs of 5 to 78, and as a first control means, an analog-to-digital converter 49.
A variable coupler control circuit 118 is provided which controls the variable couplers 75 to 78 by the output of signal 1'.

The main signal received by the main antenna 1 for main signal reception and the auxiliary antenna 4 is converted into an intermediate frequency band by a frequency converter 3 using a local oscillation signal from a local oscillator 5 after passing through a band pass filter 2. Frequency converted. Note that the phase shifter 56' inserted between the local oscillator 5 and the frequency converter 3 changes the composite phase of the main signals received by the main antenna 1 and the auxiliary antenna 4, and generally is controlled so that the received power is maximized.

The received signals of the main antenna 1 and the auxiliary antenna 4 are combined by an adder 8. This composite signal is input to quadrature phase detectors 12 and 13, and is decomposed into in-phase and quadrature components by reference carrier wave 10 recovered from the main signal.

Further, the received signal of the main antenna 1 is transmitted through a quadrature phase detector 20.
21 and is decomposed into in-phase and quadrature components by the reference carrier wave 10. On the other hand, the received signal from the auxiliary antenna 4 is input to quadrature phase detectors 20' and 21', and is decomposed into in-phase and quadrature components by a reference carrier wave 10.

The in-phase and quadrature components thus obtained are transmitted to quadrature phase detectors 12.13.20.21.20' and 21', respectively.
From, harmonic removal filter 14.15.22.23.2
2'23', an analog-to-digital converter 49.50.51.51', 5 with sufficient quantization precision;
2.53 and digitized. analog·
Digital converter 49.50.5, 51', 52.
As the sampling signal 53, a clock signal obtained by doubling the clock signal reproduced from the main signal by a multiplier 36' is commonly used.

Analog-digital converter 49.50.5L 51'
A circuit configuration for removing the main signal component from the in-phase and quadrature components of the main signal output from the 52.53 to obtain an interference signal will be described.

The output signal of the analog-to-digital converter 52 is input to a variable coupler 67, 69. These variable couplers 67
．． 69 output, and an analog-to-digital converter 51',
The outputs of 51 are added by full adders 71 and 73, respectively.

Similarly, the output signal of the analog-to-digital converter 53 is input to a variable combiner 68.70, and these outputs and the output of a full adder 71.73 are added by a full adder 72.74. From the outputs of these full adders 72 and 74, the main signal components of the in-phase and quadrature components are eliminated, and a signal a! of only the interference signal component is obtained. %al can be obtained. However, in the interference signals a1, a, the main signal component is predominant at the time when the interference compensation control is started, and the interference component increases as the control enters a steady state.

Based on this interference signal al,a, the interference component mixed into the main signal is canceled.

For this purpose, the output signal of the full adder 74, that is, the orthogonal component interference signal a, is input to the variable coupler 75.77, and the output signal of the variable coupler 75.77 and the output of the analog-to-digital converter 50.49 are input to the variable coupler 75.77. are added by full adders 79 and 81.

On the other hand, the output signal of the full adder 72, that is, the in-phase component interference signal a1, is input to the variable couplers 76 and 78. The output of this variable combiner 76.78 and the full adder 79.81
The outputs of are added by full adders 80 and 82. As a result, a compensation signal with the opposite phase and equal amplitude to the interference component mixed in the main signal system is created, and by adding this compensation signal to the interference component mixed in the main signal system, this interference component can be canceled. can.

Next, variable coupler 75.76.77.78.67.68
．． The control methods of 69 and 70 will be specifically explained.

In order to eliminate the main signal and obtain only the interference signal, it is necessary to add the main signal received by the main antenna 1 and the main signal received by the auxiliary antenna 4 with opposite phases and equal amplitudes.

Therefore, the baseband signals of the in-phase and quadrature components obtained from each of the above-mentioned received signals are transmitted to the variable coupler 67 and 68.
．． Add by 69 and 70. In this case, the in-phase and quadrature component output after addition, that is, the full adder 72.7
The outputs a, , aa of 4 must be controlled so that the main signal component is minimized.

To do this, correlation detection is performed between the main signal after addition and the output signal of auxiliary antenna 4 or main antenna 1 before addition, and variable coupler control circuit 117 is used to minimize the amount of correlation. , variable couplers 67, 68, 69 and 70, respectively, are feedback-controlled. In addition, in this embodiment, the polarity signals "Q, aI" of the interference signal,
Polar signal a@r of the main signal received by the sub antenna 4
, arr.

Based on the in-phase and quadrature component interference signals thus obtained, the interference components mixed into the main signal are eliminated. For this purpose, variable couplers 75, 76, 77 and 78 are controlled.

For this purpose, error signals ea, e obtained from the outputs of the full adders 80 and 82, that is, the main signal outputs after interference compensation, are
, and the outputs of the full adders 72 and 74, that is, the in-phase fluctuation and quadrature component of the interference signal, are input to the variable coupler control circuit 118, and correlation detection is performed between the two so that the amount thereof is minimized. Feedback control.

For example, in the case of the 16 QAM system, the error signal else can be obtained from the third and subsequent bits from the top, as shown in the table above. Here, it is assumed that correlation detection is performed using only the polarity signals al and al of the interference signal.

Note that the delay adjustment line τ shown in FIG.
．． 21 and each signal passing through the full adders 79, 80 .
81 and 82 are for time adjustment so that they are added at the same time. Similarly, the delay adjustment line τ2 is connected to the quadrature phase detectors 20 and 21 and the quadrature phase detector 2.
0', 21', each signal passes through the full adder 71.
This is for time adjustment so that 72, 73 and 74 are added at the same time.

FIG. 24 is a circuit configuration diagram showing an example of a variable coupler.

Here, an example is shown in which the delay circuit is configured with a three-tap configuration.

The variable coupler is composed of a tapped delay circuit 63', a bipolar variable attenuator 83 connected to each of these taps, and an adder 84 that adds the outputs of the bipolar variable attenuator 83. The amplitude of the signal input to 63' is adjusted and outputted from adder 84.

25 and 26 show the variable coupler control circuit 117.
118 is a circuit configuration diagram showing an example of 118. FIG.

Each error signal ea, er% of the main signal and each polarity signal ai, ats of the interference signal or the auxiliary antenna 4
Each polarity signal a, r, a, r, of the main signal received by
a,,al to the delay circuit 63 or T/2 delay circuit 63
′, the exclusive OR circuit 64 takes the correlation, and the correlation output is manually integrated by the integrator 65.
The output controls the variable coupler.

In this way, by using a plurality of weighting circuits in the variable coupler, a large compensation effect can be obtained even when the main signal and the interference signal have frequency characteristics.

〔Effect of the invention〕

As explained above, the interference compensation circuit of the present invention receives a signal in which an interference signal is mixed into a main signal for each of a plurality of propagation paths. By combining these signals with the main signal having opposite phases and equal amplitude, a highly pure interference signal is obtained. Therefore, there is no need to directly receive the signal that causes the interference signal, and even if the directions of the main signal source and the interference signal source are the same, the signal that causes the interference can be accurately determined and the signal that causes the interference signal can be received. This has the effect of highly accurate removal of interference signals mixed into the signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an interference compensation circuit according to a first embodiment of the present invention. FIG. 2 is a block diagram of an interference compensation circuit according to a second embodiment of the present invention. FIG. 3 is a block diagram of an interference compensation circuit according to a third embodiment of the present invention. FIG. 4 is a block diagram of an interference compensation circuit according to a fourth embodiment of the present invention. FIG. 5 is a block diagram of an interference compensation circuit according to a fifth embodiment of the present invention. FIG. 6 is a block diagram of an interference compensation circuit according to a sixth embodiment of the present invention. FIG. 7 is a block diagram of an interference compensation circuit according to a seventh embodiment of the present invention. FIG. 8 is a block diagram of an interference compensation circuit according to an eighth embodiment of the present invention. FIG. 9 is a block diagram of an interference compensation circuit according to a ninth embodiment of the present invention. FIG. 10 is a block diagram of the interference compensation circuit according to the first embodiment of the present invention. FIG. 11 is a block diagram of the interference compensation circuit according to the first embodiment of the present invention. FIG. 12 is a diagram showing the circuit configuration of a transversal filter control circuit. FIG. 13 is a block diagram of an interference compensation circuit according to a thirteenth embodiment of the present invention. FIG. 14 is a diagram showing the circuit configuration of a transversal filter control circuit. FIG. 15 is a block diagram of an interference compensation circuit according to a thirteenth embodiment of the present invention. FIG. 16 is a block diagram of the interference compensation circuit according to the first embodiment of the present invention. FIG. 17 is a diagram showing the circuit configuration of a transversal filter control circuit. FIG. 18 is a block diagram of an interference compensation circuit according to a thirteenth embodiment of the present invention. FIG. 19 is a block diagram of the interference compensation circuit according to the first embodiment of the present invention. FIG. 20 is a block diagram of the interference compensation circuit according to the first embodiment of the present invention. FIG. 21 is a block diagram of the interference compensation circuit according to the first embodiment of the present invention. FIG. 22 is a block diagram of the interference compensation circuit according to the first embodiment of the present invention. FIG. 23 is a block diagram of the interference compensation circuit according to the first embodiment of the present invention. FIG. 24 is a diagram showing the circuit configuration of a variable coupler. FIG. 25 is a diagram showing the circuit configuration of the variable coupler control circuit. FIG. 26 is a diagram showing the circuit configuration of the variable coupler control circuit. FIG. 27 is a block diagram of a conventional interference compensation circuit. 1... Main antenna, 1'... Wired transmission line 1', 2...
...Bandpass filter, 3...Frequency converter, 4...
・Auxiliary antenna, 5...Local oscillator, 6.6', 38
．． 42...Variable phase circuit, 7.7', 37.41...
・Variable amplitude circuit, 8.8'39.40.44.61.8
4...Adder, 9.9'43.58...Distributor, 1
1...90° phase shifter, 12.13.20.20',
21.21', 108... quadrature phase detector, 14.
15.22.23.22', 23'...Harmonic removal filter, 16.18.24.25...Identification circuit, 1
7.19...Subtractor, 26.27.64.31.32
．． 64...Exclusive OR circuit, 28.29.33.3
4...Resistance, 30.35.65...Integrator, 36'
... Multiplier, 45.46.59.60.83 ... Bipolar variable attenuator, 47.48 ... Multiplier, 49-53
...Analog-digital converter, 55... Sub-antenna, 56.56'... Phase shifter, 57... Receiving antenna for angle diversity, 61.62...90'
Synthesizer, 63.63'...Delay circuit, 67-70.7
5-78... variable coupler, 71-82... full adder, 100... demodulator, ioi, 102... error signal generation circuit, 105.106... control circuit, 107
．． 109... Correlation detection circuit, 110.111... Quadrature amplitude modulator, 112... Transversal filter, 113.113'115.115'... Transversal filter control circuit, 117... Variable Combiner side control circuit. shoulder irises

Claims (1)

[Claims] 1. A first receiving circuit that receives a signal in which an interference signal is mixed into the main signal; and a second receiving circuit that is provided in a separate system from the first receiving circuit and receives a signal that includes the interference signal. a first adjusting means for adjusting the amplitude and phase of the output signal of the second receiving circuit; a first subtracting means for subtracting the output of the first adjusting means from the output signal of the first receiving circuit; and a first control means for controlling the first adjustment means so that the interference signal included in the output of the first subtraction means becomes sufficiently small, the second receiving circuit comprising: The second receiving circuit is configured to receive a signal via a propagation path different from the signal received by the second receiving circuit, and the second receiving circuit includes a second adjusting means for adjusting the amplitude and phase of the signal received by the second receiving circuit; a second subtracting means for subtracting the output signal of the first receiving circuit from the output of the second adjusting means; An interference compensation circuit comprising: second control means for controlling the adjustment means. 2. The first receiving circuit includes a first quadrature phase detector (12, 1
3), and first and second analog-to-digital converters (49, 50) that respectively digitize the in-phase component and the quadrature component output from the first quadrature phase detector, and the first adjusting means includes: , a phase shifter (5) that adjusts the phase of the output signal of the second receiving circuit by adjusting the phase of the local oscillation signal used in the first receiving circuit and supplying the local oscillation signal to the second receiving circuit; ), the first subtraction means includes an adder (8) disposed upstream of the first quadrature phase detector and combining the received signal of the first receiving circuit and the received signal of the second receiving circuit. The first receiving circuit further includes a second quadrature phase detector (2
0, 21), and third and fourth analog-to-digital converters (51, 51) that digitize the in-phase and quadrature components output from the second quadrature phase detector, respectively.
′), and the second receiving circuit includes a third quadrature phase detector (20′,
21'), and fifth and sixth analog-to-digital converters (52, 53) that digitize the in-phase and quadrature components output from the third quadrature phase detector, respectively.
The second adjustment means includes first to fourth variable couplers (67 to 70) that adjust the phase and amplitude of the outputs of the fifth and sixth analog-to-digital converters; The subtraction means includes first to fourth full adders (71 to 7) that add the outputs of the first to fourth variable couplers to the outputs of the third and fourth analog-to-digital converters.
4), the second control means controls the variable coupling of the first to fourth by the outputs of the third and fourth analog-to-digital converters and the outputs of the fifth and sixth analog-to-digital converters; Variable coupler control circuit (117) that controls the device
The first adjusting means further includes fifth to fifth variable couplers (75 to 78) for adjusting the phase and amplitude of the outputs of the third and fourth analog-to-digital converters, The subtracting means further includes a fifth to fifth full adder (7) for adding the output of the fifth to fifth variable coupler to the output of the first and second analog-to-digital converters.
9 to 82), the first control means controls the output of the fifth to fifth analog-to-digital converters by the outputs of the first and second analog-to-digital converters and the outputs of the third and fourth analog-to-digital converters. Variable coupler control circuit (118) that controls the variable coupler
The interference compensation circuit according to claim 1, comprising: