JPH02100371A - Quantum fine line field effect transistor - Google Patents
Quantum fine line field effect transistorInfo
- Publication number
- JPH02100371A JPH02100371A JP25399088A JP25399088A JPH02100371A JP H02100371 A JPH02100371 A JP H02100371A JP 25399088 A JP25399088 A JP 25399088A JP 25399088 A JP25399088 A JP 25399088A JP H02100371 A JPH02100371 A JP H02100371A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- effect transistor
- field effect
- fine line
- lattice
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 43
- 230000000694 effects Effects 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 32
- 238000001312 dry etching Methods 0.000 description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 description 1
- 239000002772 conduction electron Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- -1 silicon metal-oxide Chemical class 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Nanotechnology (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野〕
本発明は電界効果トランジスタに関し、特に格子歪みポ
テンシャルを利用した量子細線電界効果トランジスタに
関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a field effect transistor, and particularly to a quantum wire field effect transistor that utilizes lattice strain potential.
断面方向の長さが電子のドブロイ波長程度（〜１０ｎｍ
）である細線は量子細線と呼ばれ、その−次元性から極
めて高い移動度（９１０”ｍ”／ Ｖ ｓ ）を有する
ことが予想されている。この量子細線を電界効果トラン
ジスタのチャネルに適用した例が、Ｗ、Ｊ、スコッチポ
ルらによる文献［フィジカル・レビュー・レターズ 第
５６巻 ２８６５頁（１９８６年）」（Ｐｈｙｓｉｃａ
ｌ Ｒｅｖｉｅｗ Ｌｅｔｔｅｒｓ Ｆｑ６２８６５（
１９８ｆｉ） ）に掲載されている。The length in the cross-sectional direction is about the de Broglie wavelength of an electron (~10 nm)
) is called a quantum wire, and is expected to have extremely high mobility (910"m"/Vs) due to its -dimensionality. An example of applying this quantum wire to the channel of a field effect transistor is given in the paper by W. J. Scotchpol et al. [Physical Review Letters Vol. 56, p. 2865 (1986)
l Review Letters Fq62865(
198fi)).
スコッチポルらは、シリコンによる金属−酸化膜−半導
体トランジスタ（ＭＯ５＋−ランリスタ）を、ドライエ
ツチング法により、数１０ｎｍ幅の細線に切り出し、量
子細線電界効果トランジスタを得ている。Scotchpol et al. cut out a silicon metal-oxide film-semiconductor transistor (MO5+-runlister) into thin wires with a width of several tens of nanometers by dry etching to obtain a quantum wire field effect transistor.
第３図はこのトランジスタ構造を説明する斜視図で、７
はゲート電極、８はチャネル、９は基板を示している。Figure 3 is a perspective view illustrating this transistor structure.
8 represents a gate electrode, 8 represents a channel, and 9 represents a substrate.
チャネル８の幅は数１０ｎｍごある。The width of the channel 8 is several tens of nanometers.
この量子細線電界効果トランジスタにおいて、ゲート電
極７に電圧を印加すると、チャネル８に反転層ができ、
そこに伝導電子が発生ずる。この反転層の厚さは、Ｍ、
Ｓ、 ラニーによる文献「フィジックス・オブ・セミコ
ンダクタ・デバイスイズ」（Ｐｈｙｓｉｃｓ ｏｆ Ｓ
ｅｍ１ｃｏｎｄｕｃｔｏｒ Ｄｅｖｉｃｅｓ）＋ １９
８１年ジョンズ・ウィリー・アンド・サンズ社（Ｊｏｈ
ｎｓＷｉｌｅｙ ａｎｄ ５ｏｎｓ’）に述べられてい
るように数ｎｍである。従って、このＭＯＳトランジス
タのチャネルは量子細線と見做すことができ、量子細線
特有の高移動度のためにトランジスタ特性が大幅に向上
することが期待される。In this quantum wire field effect transistor, when a voltage is applied to the gate electrode 7, an inversion layer is formed in the channel 8.
Conduction electrons are generated there. The thickness of this inversion layer is M,
``Physics of Semiconductor Devices'' by S. Ranney.
em1conductor Devices) + 19
1981 Johns Willey & Sons Co.
nsWiley and 5ons'). Therefore, the channel of this MOS transistor can be regarded as a quantum wire, and it is expected that the transistor characteristics will be significantly improved due to the high mobility peculiar to quantum wires.
しかしながら、実際の動作の際、チャネル８の加工面を
空気に接触させると、チャネル表面層が空気と化学変化
を起こし、表面準位が形成される。However, during actual operation, when the processed surface of the channel 8 is brought into contact with air, the channel surface layer undergoes a chemical change with the air, and surface states are formed.
これら表面準位は量子細線の輸送特性を悪化させる。These surface states deteriorate the transport properties of the quantum wire.
従って、ドライエツチング法による加工の後、チャネル
の保８！！膜を形成する必要があるが、ドライエツチン
グ後、保護膜を空気に接触させずに形成しなければなら
ず、プロセスが繁雑となる。また、ドライエ“ツチング
法による加工面は凹凸が激しく、チャネル８の空気接触
面を確実に被覆することは困難である。更に保護膜がう
まく形成されても、表面準位が依然として悪影響を及ぼ
すこともある。Therefore, after processing by dry etching, the channel is preserved. ! Although it is necessary to form a film, a protective film must be formed without contacting air after dry etching, which makes the process complicated. In addition, the surface processed by the dry etching method is extremely uneven, making it difficult to reliably cover the air contact surface of the channel 8.Furthermore, even if a protective film is successfully formed, surface states may still have an adverse effect. There is also.
本発明の目的は、ドライエツチング法を利用せず、格子
歪みポテンシャルを利用することで、表面準位の影響の
ない量子細線を得、トランジスタ特性を大幅に向上でき
る量子細線電界効果トランジスタを提供することにある
。An object of the present invention is to provide a quantum wire field-effect transistor that uses lattice strain potential without using a dry etching method to obtain quantum wires that are not affected by surface states, and that can significantly improve transistor characteristics. There is a particular thing.
本発明の量子細線電界効果トランジスタは、第１の半導
体層が、この第１の半導体層と格子定数が異なり前記第
１の半導体層よりも電子親和力の小さい第２の半導体層
によって挟まれ、＋ｉＤ記第２の半導体層の一方に溝が
形成され、更にゲート電極が設けられていることを特徴
とする。In the quantum wire field effect transistor of the present invention, a first semiconductor layer is sandwiched between second semiconductor layers having a lattice constant different from that of the first semiconductor layer and having a smaller electron affinity than the first semiconductor layer, and +iD A groove is formed in one of the second semiconductor layers, and a gate electrode is further provided.
本発明では、第２の半導体層の一方の表面にエツチング
によって溝を形成して、その半導体層の厚さを空間変化
させ、それによって生じる格子歪みポテンシャルの高低
を利用して電子を一次元構造に閉じ込め、量子細線電界
効果トランジスタを得る。In the present invention, a groove is formed on one surface of the second semiconductor layer by etching to spatially change the thickness of the semiconductor layer, and the height of the resulting lattice strain potential is utilized to create a one-dimensional structure of electrons. to obtain a quantum wire field-effect transistor.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は、本発明の一実施例を示す斜視図である。第１
図において、ｌはエツチングにより溝５を掘られた第２
の半導体層、２は第１の半導体層、３は第２の半導体層
、４はゲート電極を示しており、第１の半導体層２は第
２の半導体層１と３とに挟まれている。第２の半導体層
は、第１の半導体層と格子定数が異なり第１の半導体層
よりも電子親和力が小さい。FIG. 1 is a perspective view showing an embodiment of the present invention. 1st
In the figure, l is the second groove in which the groove 5 is etched.
, 2 is a first semiconductor layer, 3 is a second semiconductor layer, 4 is a gate electrode, and the first semiconductor layer 2 is sandwiched between the second semiconductor layers 1 and 3. . The second semiconductor layer has a different lattice constant from the first semiconductor layer and has a smaller electron affinity than the first semiconductor layer.
第１の半導体層として例えば砒化ガリウムを、第２の半
導体層として例えば砒化アルミニウム、ガリウムを選ぶ
ことができる。砒化アルミニウムガリウムは砒化ガリウ
ムと格子定数が異なり、また、前者は後者より電子親和
力が小さい。このため、第１の半導体層に電子が貯えら
れる。またゲート電極の材料として、例えばアルミニウ
ムを用いることができる。For example, gallium arsenide can be selected as the first semiconductor layer, and aluminum arsenide or gallium, for example, can be selected as the second semiconductor layer. Aluminum gallium arsenide has a different lattice constant from gallium arsenide, and the former has a lower electron affinity than the latter. Therefore, electrons are stored in the first semiconductor layer. Furthermore, aluminum, for example, can be used as a material for the gate electrode.
第２図は、本実施例において歪みポテンシャルの井戸が
形成される原理を説明するものである。FIG. 2 explains the principle by which strain potential wells are formed in this embodiment.
第２図（ａ）は第１図の実施例の断面図、第２図（ｂ）
は第１の半導体層２中の格子定数の空間変化（ａｏは平
衡時の格子定数）、第２図（Ｃ）は格子不整合による歪
みポテンシャルの空間変化を示す。第２の半導体層１が
厚い領域では第１の半導体層２中の格子歪みが太き（、
歪みポテンシャルも大きい。第２の半導体層１が溝を掘
られ、薄くなっている領域では、第１の半導体層２中の
格子歪みが小さく、歪みポテンシャルが小さい。従って
、第２図（Ｃ）に示すように歪みポテンシャルの井戸が
形成される。Figure 2(a) is a sectional view of the embodiment shown in Figure 1, Figure 2(b)
shows a spatial change in the lattice constant in the first semiconductor layer 2 (ao is the lattice constant at equilibrium), and FIG. 2C shows a spatial change in the strain potential due to lattice mismatch. In the region where the second semiconductor layer 1 is thick, the lattice strain in the first semiconductor layer 2 is large (,
The distortion potential is also large. In the region where the second semiconductor layer 1 is grooved and thinned, the lattice strain in the first semiconductor layer 2 is small and the strain potential is small. Therefore, a strain potential well is formed as shown in FIG. 2(C).
次に、この歪みポテンシャルの大きさを見積もることと
する。第１の半導体層として用いられた砒化ガリウムの
場合、フォーセットらによる文献［ジャーナル・オブ・
フィジックス・アンド・ケミストリイ・オブ・ソリッズ
Ｊ （Ｊ、 Ｐｈｙｓ、 Ｃｈｅｍ、５ｏｌｉｄｓ）
第３１巻 １９６３頁（１９７０）に掲載されている論
文によると、格子の変形ポテンシャルは〜１０９ｅ Ｖ
／ ｃ ｍである。格子不整合による歪みが、〜（０
，０１〜０．１）人であるから、変形ポテンシャルは０
．１〜１ｅＶとなる。通常の量子井戸構造による閉じ込
めでは、電子親和力の差によって生じる伝導帯のバンド
・オフセットを利用しているが、前記ラニーの文献によ
れば、通常用いられる半導体の組み合わせで０．１〜１
ｅＶの大きさである。従って本発明の原理による電子の
閉じ込めは十分に可能である。Next, let us estimate the magnitude of this distortion potential. In the case of gallium arsenide used as the first semiconductor layer, the paper by Fawcett et al. [Journal of
Physics and Chemistry of Solids J (J, Phys, Chem, 5olids)
According to the paper published in Volume 31, page 1963 (1970), the deformation potential of the lattice is ~109e V
/ cm. The distortion due to lattice mismatch is ~(0
,01~0.1) Since it is a person, the deformation potential is 0.
．． It becomes 1 to 1 eV. In conventional confinement using a quantum well structure, the band offset of the conduction band caused by the difference in electron affinity is used, but according to the above-mentioned Raney literature, the band offset of the conduction band is 0.1 to 1.
It is the magnitude of eV. Therefore, electron confinement according to the principles of the present invention is fully possible.
以上の説明から明らかなように上記実施例で溝を掘られ
た第２の半導体層ｌの溝５の下部に量子ｉＩ線すなわち
チャネル６が実現され、しかも、この量子細線はすべて
の面が空気と非接触である。As is clear from the above description, a quantum iI line, that is, a channel 6 is realized under the groove 5 of the second semiconductor layer l which is grooved in the above embodiment, and furthermore, this quantum wire has air on all surfaces. and non-contact.
従って量子細線の輸送特性は理論的予想に近いものとな
り、トランジスタ特性の改善がなされる。Therefore, the transport characteristics of the quantum wire become close to theoretical predictions, and the transistor characteristics are improved.
なお、本実施例では、第１の半導体層として砒化ガリウ
ム、第２の半導体層として砒化アルミニウムガリウムを
選んだが、他に様々な組み合わせが可能であり、例えば
、第１の半導体層としてシリコンゲルマニウム、第２の
半導体層としてシリコンを用いることも考えられる。こ
の組み合わせでは格子に４％の不整合があり、より大き
い歪みエネルギーが得られる。In this example, gallium arsenide was selected as the first semiconductor layer, and aluminum gallium arsenide was selected as the second semiconductor layer, but various other combinations are possible. For example, silicon germanium, silicon germanium, It is also possible to use silicon as the second semiconductor layer. This combination has a 4% mismatch in the lattice, resulting in higher strain energy.
以上説明したように本発明は格子の歪みポテンシャルを
利用することにより、表面準位の影響のない量子細線を
得、電界効果ｌ・ランリスタに応用可能となるという効
果を有する。As explained above, the present invention has the advantage that by utilizing the strain potential of the lattice, a quantum wire without the influence of surface states can be obtained, and it can be applied to a field effect l-run lister.
第１図は本発明の一実施例を示す斜視図、第２図は歪み
ポテンシャルによる電子の閉じ込め原理を説明する断面
図、
第３図は従来の量子細線電界効果トランジスタを示す斜
視図である。
１・・・・・溝を掘られた第２の半導体層２・・・・・
第１の半導体層
３・・・・・第２の半導体層
４・・・・・ゲート電極
５・・・・・溝
６・・・・・チャネル
第１図
第２図FIG. 1 is a perspective view showing an embodiment of the present invention, FIG. 2 is a cross-sectional view illustrating the principle of electron confinement using a strain potential, and FIG. 3 is a perspective view showing a conventional quantum wire field effect transistor. 1... Grooved second semiconductor layer 2...
First semiconductor layer 3... Second semiconductor layer 4... Gate electrode 5... Groove 6... Channel Figure 1 Figure 2
Claims (1)
数が異なり前記第１の半導体層よりも電子親和力の小さ
い第２の半導体層によって挟まれ、前記第２の半導体層
の一方に溝が形成され、更にゲート電極が設けられてい
ることを特徴とする格子歪みポテンシャルを利用した量
子細線電界効果トランジスタ。(1) A first semiconductor layer is sandwiched between second semiconductor layers having a different lattice constant from the first semiconductor layer and a lower electron affinity than the first semiconductor layer, and one of the second semiconductor layers A quantum wire field effect transistor utilizing lattice strain potential, characterized in that a groove is formed in the lattice strain potential, and a gate electrode is further provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25399088A JPH0812927B2 (en) | 1988-10-07 | 1988-10-07 | Quantum wire field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25399088A JPH0812927B2 (en) | 1988-10-07 | 1988-10-07 | Quantum wire field-effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02100371A true JPH02100371A (en) | 1990-04-12 |
| JPH0812927B2 JPH0812927B2 (en) | 1996-02-07 |
Family
ID=17258736
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25399088A Expired - Lifetime JPH0812927B2 (en) | 1988-10-07 | 1988-10-07 | Quantum wire field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0812927B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5285081A (en) * | 1991-12-09 | 1994-02-08 | Nec Corporation | Field effect transistor having quasi one-dimensional electron gas confined under electron resonance |
| JPH07231083A (en) * | 1993-12-22 | 1995-08-29 | Hikari Gijutsu Kenkyu Kaihatsu Kk | Semiconductor element |
-
1988
- 1988-10-07 JP JP25399088A patent/JPH0812927B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5285081A (en) * | 1991-12-09 | 1994-02-08 | Nec Corporation | Field effect transistor having quasi one-dimensional electron gas confined under electron resonance |
| JPH07231083A (en) * | 1993-12-22 | 1995-08-29 | Hikari Gijutsu Kenkyu Kaihatsu Kk | Semiconductor element |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0812927B2 (en) | 1996-02-07 |
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