JPH0812927B2 - Quantum wire field-effect transistor - Google Patents
Quantum wire field-effect transistorInfo
- Publication number
- JPH0812927B2 JPH0812927B2 JP25399088A JP25399088A JPH0812927B2 JP H0812927 B2 JPH0812927 B2 JP H0812927B2 JP 25399088 A JP25399088 A JP 25399088A JP 25399088 A JP25399088 A JP 25399088A JP H0812927 B2 JPH0812927 B2 JP H0812927B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- quantum wire
- effect transistor
- lattice
- wire field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005669 field effect Effects 0.000 title claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 39
- 239000010410 layer Substances 0.000 description 34
- 238000001312 dry etching Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000002772 conduction electron Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は電界効果トランジスタに関し、特に格子歪み
ポテンシャルを利用した量子細線電界効果トランジスタ
に関する。The present invention relates to a field effect transistor, and more particularly to a quantum wire field effect transistor utilizing a lattice strain potential.
断面方向の長さが電子のドブロイ波長程度（〜10nm）
である細線は量子細線と呼ばれ、その一次元性から極め
て高い移動度（102m2/Vs）を有することが予想されて
いる。この量子細線を電界効果トランジスタのチャネル
に適用した例が、W.J.スコッチポルらによる文献「フィ
ジカル・レビュー・レターズ 第56巻 2865頁（1986
年）」（Physical Review Letters 56 2865（1986））
に掲載されている。Length in cross section is about de Broglie wavelength of electron (~ 10nm)
Is a quantum wire, and it is expected to have extremely high mobility (10 2 m 2 / Vs) due to its one-dimensional property. An example of applying this quantum wire to the channel of a field-effect transistor is the article by WJ Scotchpol et al., “Physical Review Letters, Vol. 56, page 2865 (1986).
(Year) ”(Physical Review Letters 56 2865 (1986))
It is published in.
スコッチポルらは、シリコンによる金属−酸化膜−半
導体トランジスタ（MOSトランジスタ）を、ドライエッ
チング法により、数10nm幅の細線に切り出し、量子細線
電界効果トランジスタを得ている。Scotchpol et al. Obtained a quantum wire field effect transistor by cutting a metal-oxide film-semiconductor transistor (MOS transistor) made of silicon into a thin wire with a width of several tens nm by a dry etching method.
第３図はこのトランジスタ構造を説明する斜視図で、
７はゲート電極、８はチャネル、９は基板を示してい
る。チャネル８の幅は数10nmである。この量子細線電界
効果トランジスタにおいて、ゲート電極７に電圧を印加
すると、チャネル８に反転層ができ、そこに伝導電子が
発生する。この反転層の厚さは、M.S.ツェーによる文献
「フィジックス・オブ・セミコンダクタ・デバイスィ
ズ」（Physics of Semiconductor Devices）,1981年ジ
ョンズ・ウィリー・アンド・サンズ社（Johns Wiley an
d Sons'）に述べられているように数nmである。従っ
て、このMOSトランジスタのチャネルは量子細線と見倣
すことができ、量子細線特有の高移動度のためにトラン
ジスタ特性が大幅に向上することが期待される。FIG. 3 is a perspective view for explaining this transistor structure.
Reference numeral 7 is a gate electrode, 8 is a channel, and 9 is a substrate. The width of the channel 8 is several 10 nm. In this quantum wire field effect transistor, when a voltage is applied to the gate electrode 7, an inversion layer is formed in the channel 8 and conduction electrons are generated there. The thickness of this inversion layer is determined by MS Tze in the article "Physics of Semiconductor Devices", Johns Wiley and Sons, 1981.
It is a few nm, as described in d Sons'). Therefore, the channel of this MOS transistor can be regarded as a quantum wire, and it is expected that the transistor characteristics are significantly improved due to the high mobility peculiar to the quantum wire.
しかしながら、実際の動作の際、チャネル８の加工面
を空気に接触させると、チャネル表面層が空気と化学変
化を起こし、表面準位が形成される。これら表面準位は
量子細線の輸送特性を悪化させる。However, in actual operation, when the processed surface of the channel 8 is brought into contact with air, the channel surface layer undergoes a chemical change with air and a surface level is formed. These surface states deteriorate the transport properties of the quantum wire.
従って、ドライエッチング法による加工の後、チャネ
ルの保護膜を形成する必要があるが、ドライエッチング
後、保護膜を空気に接触させずに形成しなければなら
ず、プロセスが繁雑となる。また、ドライエッチング法
による加工面は凹凸が激しく、チャネル８の空気接触面
を確実に被覆することは困難である。更に保護膜がうま
く形成されても、表面準位が依然として悪影響を及ぼす
こともある。Therefore, after processing by the dry etching method, it is necessary to form a protective film for the channel, but after dry etching, the protective film must be formed without contact with air, which complicates the process. In addition, the surface processed by the dry etching method has large irregularities, and it is difficult to reliably cover the air contact surface of the channel 8. Further, even if the protective film is successfully formed, the surface level may still have an adverse effect.
本発明の目的は、ドライエッチング法を利用せず、格
子歪みポテンシャルを利用することで、表面準位の影響
のない量子細線を得、トランジスタ特性を大幅に向上で
きる量子細線電界効果トランジスタを提供することにあ
る。An object of the present invention is to provide a quantum wire field effect transistor capable of obtaining a quantum wire free from the influence of surface states and significantly improving transistor characteristics by utilizing a lattice strain potential without using a dry etching method. Especially.
本発明の量子細線電界効果トランジスタは、 第１の半導体層が、この第１の半導体層と格子定数が
異なり前記第１の半導体層よりも電子親和力の小さい第
２の半導体層によって挟まれ、前記第２の半導体層の一
方に溝が形成され、更にゲート電極が設けられているこ
とを特徴とする。In the quantum wire field-effect transistor of the present invention, the first semiconductor layer is sandwiched by a second semiconductor layer having a lattice constant different from that of the first semiconductor layer and having an electron affinity smaller than that of the first semiconductor layer, A groove is formed in one of the second semiconductor layers, and a gate electrode is further provided.
本発明では、第２の半導体層の一方の表面にエッチン
グによって溝を形成して、その半導体層の厚さを空間変
化させ、それによって生じる格子歪みポテンシャルの高
低を利用して電子を一次元構造に閉じ込め、量子細線電
界効果トランジスタを得る。According to the present invention, a groove is formed on one surface of the second semiconductor layer by etching, the thickness of the semiconductor layer is spatially changed, and the height of the lattice strain potential generated thereby is used to generate electrons in a one-dimensional structure. To obtain a quantum wire field effect transistor.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は、本発明の一実施例を示す斜視図である。第
１図において、１はエッチングにより溝５を掘られた第
２の半導体層、２は第１の半導体層、３は第２の半導体
層、４はゲート電極を示しており、第１の半導体層２は
第２の半導体層１と３とに挟まれている。第２の半導体
層は、第１の半導体層と格子定数が異なり第１の半導体
層よりも電子親和力が小さい。FIG. 1 is a perspective view showing an embodiment of the present invention. In FIG. 1, reference numeral 1 is a second semiconductor layer in which a groove 5 is formed by etching, 2 is a first semiconductor layer, 3 is a second semiconductor layer, and 4 is a gate electrode. Layer 2 is sandwiched between second semiconductor layers 1 and 3. The second semiconductor layer has a lattice constant different from that of the first semiconductor layer and has an electron affinity smaller than that of the first semiconductor layer.
第１の半導体層として例えば砒化ガリウムを、第２の
半導体層として例えば砒化アルミニウムガリウムを選ぶ
ことができる。砒化アルミニウムガリウムは砒化ガリウ
ムと格子定数が異なり、また、前者は後者より電子親和
力が小さい。このため、第１の半導体層に電子が貯えら
れる。またゲート電極の材料として、例えばアルミニウ
ムを用いることができる。For example, gallium arsenide can be selected as the first semiconductor layer, and aluminum gallium arsenide can be selected as the second semiconductor layer. Aluminum gallium arsenide has a different lattice constant from gallium arsenide, and the former has a smaller electron affinity than the latter. Therefore, electrons are stored in the first semiconductor layer. Aluminum can be used as the material of the gate electrode, for example.
第２図は、本実施例において歪みポテンシャルの井戸
が形成される原理を説明するものである。第２図（ａ）
は第１図の実施例の断面図、第２図（ｂ）は第１の半導
体層２中の格子定数の空間変化（a0は平衡時の格子定
数）、第２図（ｃ）は格子不整合による歪みポテンシャ
ルの空間変化を示す。第２の半導体層１が厚い領域では
第１の半導体層２中の格子歪みが大きく、歪みポテンシ
ャルも大きい。第２の半導体層１が溝を掘られ、薄くな
っている領域では、第１の半導体層２中の格子歪みが小
さく、歪みポテンシャルが小さい。従って、第２図
（ｃ）に示すように歪みポテンシャルの井戸が形成され
る。FIG. 2 illustrates the principle of forming a well of strain potential in this embodiment. Fig. 2 (a)
1 is a cross-sectional view of the embodiment of FIG. 1, FIG. 2 (b) is a spatial variation of the lattice constant in the first semiconductor layer 2 (a 0 is the lattice constant at equilibrium), and FIG. 2 (c) is the lattice. The spatial variation of strain potential due to mismatch is shown. In the region where the second semiconductor layer 1 is thick, the lattice strain in the first semiconductor layer 2 is large and the strain potential is also large. In the region where the second semiconductor layer 1 is grooved and thinned, the lattice strain in the first semiconductor layer 2 is small and the strain potential is small. Therefore, a well of strain potential is formed as shown in FIG. 2 (c).
次に、この歪みポテンシャルの大きさを見積もること
とする。第１の半導体層として用いられた砒化ガリウム
の場合、フォーセットらによる文献「ジャーナル・オブ
・フィジックス・アンド・ケミストリィ・オブ・ソリッ
ズ」（J.Phys.Chem.Solids）第31巻 1963頁（1970）に
掲載されている論文によると、格子の変形ポテンシャル
は〜109eV/cmである。格子不整合による歪みが、〜（0.
01〜0.1）Åであるから、変形ポテンシャルは0.1〜1eV
となる。通常の量子井戸構造による閉じ込めでは、電子
親和力の差によって生じる伝導帯のバンド・オフセット
を利用しているが、前記ツェーの文献によれば、通常用
いられる半導体の組み合わせで0.1〜1eVの大きさであ
る。従って本発明の原理による電子の閉じ込めは十分に
可能である。Next, the magnitude of this strain potential will be estimated. In the case of gallium arsenide used as the first semiconductor layer, the document “Journal of Physics and Chemistry of Solids” (J.Phys.Chem.Solids) 31: 1963 (1970) by Fawcett et al. ), The deformation potential of the lattice is ~ 10 9 eV / cm. The strain due to lattice mismatch is ~ (0.
01 ~ 0.1) Å, the deformation potential is 0.1 ~ 1 eV
Becomes In the confinement by the usual quantum well structure, the band offset of the conduction band caused by the difference in the electron affinity is used.According to the Tse reference, the size of 0.1 to 1 eV can be obtained in the combination of the semiconductors that are usually used. is there. Therefore, electron confinement according to the principles of the present invention is fully possible.
以上の説明から明らかなように上記実施例で溝を掘ら
れた第２の半導体層１の溝５の下部に量子細線すなわち
チャネル６が実現され、しかも、この量子細線はすべて
の面が空気と非接触である。従って量子細線の輸送特性
は理論的予想に近いものとなり、トランジスタ特性の改
善がなされる。As is apparent from the above description, a quantum wire, that is, a channel 6 is realized below the groove 5 of the second semiconductor layer 1 in which the groove has been formed in the above-described embodiment, and moreover, all surfaces of the quantum wire are air. It is non-contact. Therefore, the transport characteristics of the quantum wire are close to theoretical expectations, and the transistor characteristics are improved.
なお、本実施例では、第１の半導体層として砒化ガリ
ウム、第２の半導体層として砒化アルミニウムガリウム
を選んだが、他に様々な組み合わせが可能であり、例え
ば、第１の半導体層としてシリコンゲルマニウム、第２
の半導体層としてシリコンを用いることも考えられる。
この組み合わせでは格子に４％の不整合があり、より大
きい歪みエネルギーが得られる。Although gallium arsenide is selected as the first semiconductor layer and aluminum gallium arsenide is selected as the second semiconductor layer in this embodiment, various other combinations are possible, for example, silicon germanium as the first semiconductor layer, Second
It is also conceivable to use silicon as the semiconductor layer.
With this combination, there is a 4% mismatch in the lattice, resulting in greater strain energy.
以上説明したように本発明は格子の歪みポテンシャル
を利用することにより、表面準位の影響のない量子細線
を得、電界効果トランジスタに応用可能となるという効
果を有する。As described above, the present invention has an effect that a quantum wire free from the influence of surface states can be obtained by utilizing the strain potential of the lattice and can be applied to a field effect transistor.
第１図は本発明の一実施例を示す斜視図、 第２図は歪みポテンシャルによる電子の閉じ込め原理を
説明する断面図、 第３図は従来の量子細線電界効果トランジスタを示す斜
視図である。 １……溝を掘られた第２の半導体層 ２……第１の半導体層 ３……第２の半導体層 ４……ゲート電極 ５……溝 ６……チャネルFIG. 1 is a perspective view showing an embodiment of the present invention, FIG. 2 is a sectional view for explaining the principle of electron confinement by strain potential, and FIG. 3 is a perspective view showing a conventional quantum wire field effect transistor. 1 ... second semiconductor layer with trenches 2 ... first semiconductor layer 3 ... second semiconductor layer 4 ... gate electrode 5 ... groove 6 ... channel
Claims (1)
格子定数が異なり前記第１の半導体層よりも電子親和力
の小さい第２の半導体層によって挟まれ、前記第２の半
導体層の一方に溝が形成され、更にゲート電極が設けら
れていることを特徴とする格子歪みポテンシャルを利用
した量子細線電界効果トランジスタ。1. A first semiconductor layer is sandwiched between a second semiconductor layer having a lattice constant different from that of the first semiconductor layer and an electron affinity smaller than that of the first semiconductor layer, and the second semiconductor layer. A quantum wire field-effect transistor utilizing a lattice strain potential, characterized in that a groove is formed on one side of the gate and a gate electrode is further provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25399088A JPH0812927B2 (en) | 1988-10-07 | 1988-10-07 | Quantum wire field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25399088A JPH0812927B2 (en) | 1988-10-07 | 1988-10-07 | Quantum wire field-effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02100371A JPH02100371A (en) | 1990-04-12 |
| JPH0812927B2 true JPH0812927B2 (en) | 1996-02-07 |
Family
ID=17258736
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25399088A Expired - Lifetime JPH0812927B2 (en) | 1988-10-07 | 1988-10-07 | Quantum wire field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0812927B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2701633B2 (en) * | 1991-12-09 | 1998-01-21 | 日本電気株式会社 | Semiconductor device |
| JP2920279B2 (en) * | 1993-12-22 | 1999-07-19 | 光技術研究開発株式会社 | Semiconductor element |
-
1988
- 1988-10-07 JP JP25399088A patent/JPH0812927B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02100371A (en) | 1990-04-12 |
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