JPH021001A - Sequence controller - Google Patents

Abstract

PURPOSE:To execute sequence with steps whose number is equal to the number of contacts by providing a sequence executing part which processes instructions translated to five kinds of code of a ladder circuit, an OR address code, and a contact address by a compiler. CONSTITUTION:When code (st) is added, preceding contents of a line memory 10 are inputted to the OR address in the left of the contact in a memory 11 before the processing of the contact, and AND between preceding contents of the memory 10 and the logic of the contact is operated and the result is inputted to the memory 10. When code (end) is added, AND between preceding contents of the memory 10 and the logic of the contact is operated and the result is inputted to the memory 10, and OR between the logic of the memory 10 and the logic in the OR address in the right of the contact in the memory 12 is operated and the result is inputted to the same address of the memory 12.

Description

[Detailed description of the invention]

INDUSTRIAL APPLICATION FIELD The present invention relates to a sequence control device that processes a sequence program (ladder circuit). BACKGROUND OF THE INVENTION FIG. 1 is an example of a ladder circuit for explaining the present invention and the prior art. Figure 2 shows that in the conventional technology, the first
It shows a form of processing for executing the ladder circuit shown in the figure. A conventional sequence control device processes a sequence program (ladder circuit) in the ladder circuit shown in FIG. 1 in the form of processing shown in FIG. 2. In other words, O in the sequence program (ladder circuit)
If an R circuit exists, one circuit is divided into many blocks as shown by dotted lines 1 to 8 in Figure 1, the blocks are treated as a group, and the contacts within the blocks are ANDed.
-OR and then AND those blocks again
-Sequence program (ladder circuit) by ORing
The entire process is being carried out. Problems to be Solved by the Invention However, in the above processing format, the sequence program (ladder circuit) is considered divided into blocks, so not only one contact and one step, but also the processing shown by 9 in Fig. 2 is inevitable. This is one of the factors that slows down the processing speed in sequence control that requires high speed. In addition, in this processing mode, each block has one memory for processing, so if a large number of complex OR circuits appear in the sequence program (ladder circuit), the memory will be reduced accordingly. Must be placed in the sequence controller. Further, since the number of memories is limited depending on the sequence control device, the number of OR circuits to be constructed is limited due to the hardware configuration of each sequence control device. Therefore, the present invention makes it possible to perform one contact in a ladder diagram in one step, that is, in the same number of steps as the number of contacts used in the ladder circuit, and to incorporate an unlimited number of OR circuits without depending on the sequence control device. It is intended to do so. Means to solve the problem In order to solve the above problems, we have developed five types of contact points and OR
It is equipped with a configuration including an OR address common to the circuit, a compiler that translates six types of contacts, a memory for each OR address, and a sequence execution unit that processes coded instructions. The effects of this configuration are as follows. In a sequence program (ladder circuit), the sequence execution unit that processes instructions translated into 5 types of codes, OR address codes, and contact addresses by the compiler converts the ladder circuit from memory for each OR address even in OR instruction processing. This means that the information before processing can be read out and executed in the same number of steps as the number of contacts. Furthermore, the memory for each OR address is common to all circuits, so there is no limit to the number of OR circuits. Embodiment Next, the present invention will be explained in detail with reference to the block diagram of an embodiment of the present invention shown in FIG. 3 and the sample sequence program (ladder circuit) shown in FIG. The memory 10 in Fig. 3 stores information up to the contact point currently being processed in one circuit (the smallest vertically closed circuit between the left and right busbars in the ladder circuit diagram) in a sequence program (ladder circuit). It shows the logic of the circuit. The memory 11 is a memory for storing the logic up to that point for each OR address before processing a certain contact point. The memory 12 is a memory for storing the logic up to that point for each OR address after processing a certain contact point. Further, FIG. 4 shows a processing form when the sequence program (ladder circuit) of FIG. 1 is processed by the sequence control device of the present invention. FIG. 6 shows OFt addresses in the ladder circuit diagram. FIG. 6 shows six types of codes. Also the 7th
The figure shows the flow of processing of a sequence control device using the present invention. First, when a sequence program (ladder circuit) as shown in FIG. 1 is processed by the sequence control device of the present invention, the fourth
The processing order is as shown in the figure, and the processing is performed using three types of codes, such as the 13 additional codes in Fig. 4, with six possible combinations. Before processing, which OR address each contact in the sequence program (ladder circuit) is connected to is added as shown at 14 in Figure 6, and the sequence execution unit writes the OR address code. Decipher and process. The processing order is based on the sequence program (ladder circuit) shown in Figure 1, where numbers are assigned from the top left to the right, and the processing order numbers start from the top left, starting at the intersection (T
, +, juice), if the line below that intersection has an intersection in the shape of an l, '' or 10, move to the line of - and repeat the search in the same way to find the area within one circuit. Determine processing order. Additional codes (st, θld, ob) are attached to the contacts as shown below. At Apply the sequence program (ladder circuit) to the actual relay circuit, and attach it to the contact point where the current branch begins before that contact point. end Apply the sequence program (ladder circuit) to the actual relay circuit, and attach it to the contact where the current flows into the contact after that contact. ob Attached to the ending contact of the OR circuit block. In the sequence control device configured as above,
The operation of the present invention is as follows. - At the beginning of the circuit, the memory 10 in FIG. 3 contains the bit [1] whose logic is established. It is also assumed that the memory 12 contains a bit [o] whose logic is not established. If no additional code is attached, the processing method is to AND the previous line memory 1o and the logic of its contact.
Take Q and input into memory 1o. If the code (st) is attached, make a note of the previous line memory 1o before processing that contact.
J11iC, it is input to the left OR address of that contact, and then the previous line memory 1o and the logic of that contact are ANDed and input to the memory 1o. When the (end) code is attached, the process begins with the difference between the previous line memory 1o and the logic of its contacts.
Di is taken and inputted to the memory 10, and then the logic of the memory 10 is ORed with the logic at the right OR address of the contact in the memory 12, and the result is inputted to the same location in the memory 12. Also, what is the process for the next contact after the one to which this code is attached? First, the logic at the left OR address of that contact in the memory 11 is input to the memory 1o, and then processing is performed according to the code added to that contact. If the code (ob) is attached, the process is to first perform an AND operation between the previous line memory 10 and the logic of its contacts.
Then, the logic of the memory 10 and the logic at the right OR address of the contact in the memory 12 are ORi, and the result is input to the memory 10. After that, in the memory 12, there is a logic failure at the OR address to the right of that contact.

Enter [0]. By performing the above-described operations in the processing order described above, when the output is finally processed, the logic stored in the memory 1o becomes the output. As mentioned above, in a sequence program (ladder circuit), the sequence execution unit that processes instructions translated into 6 types of codes, OR address code, and contact address by the compiler converts the ladder circuit into OR address in OFt instruction processing. This means that the pre-processing information can be read from each memory and executed in the same number of steps as the number of contacts. Furthermore, the memory for each OR address is common to the previous circuit, so there is no limit to the number of OR circuits. As more than the effect of invention, sequence program (ladder circuit diagram)
In this process, in order to store the states before and after processing the contacts in the ladder circuit, an OR address is added in the vertical direction between the contacts in the ladder circuit, and two types of memory are provided for each OR address. Furthermore, by adding five types of codes to each contact point, the process is executed in the same number of steps as the number of contacts in the ladder circuit, increasing the processing speed, and OR circuits can be incorporated without restriction.

[Brief explanation of the drawing]

Fig. 1 shows a sequence program for explaining the processing method of the sequence control device of the present invention, and Fig. 2 shows the processing order when Fig. 1 is processed using a conventional sequence control device. 3 is a block diagram of the sequence program (ladder circuit) processing portion of the sequence control device of the present invention, and FIG. 4 is a diagram showing the sequence program (ladder circuit) of FIG. 1. , Figure 5 is a diagram showing the processing order and code for processing, Figure 5 is a diagram showing OR addresses in the ladder circuit diagram, Figure 6 is 6
FIG. 7 is a diagram showing the types of codes, and FIG. 7 is a diagram showing the processing flow of the sequence control device using the present invention. 1o~12...Memory. Name of agent: Patent attorney Toshio Nakao and 1 other person 18 STEP'! Figure Rutter rotation Rakuzu Figure size addition code = p The processing is done ←, on the form! 2! other than

Claims (1)

[Claims] A ladder circuit with several types of codes and a common OR circuit
Consisting of a compiler that translates address codes and contact addresses into machine language, a memory for each OR address, and a sequence execution unit that processes coded instructions,
A sequence control device characterized in that the sequence control device executes the process in the same number of steps as the number of contacts.