JPH02100021A - Liquid crystal device - Google Patents

Abstract

PURPOSE:To prevent the display quality from deteriorating by providing an image nondisplay part formed of a 3rd electrode which is arranged outside an image display part in parallel to scanning electrodes, outputting a voltage to the 3rd electrode for a specific number of selected scanning electrodes, and increasing the specific number as the outside temperature rises. CONSTITUTION:Transparent electrodes (transparent electrode for frame) 150 which cross a common-side transparent electrode are provided outside an effective display area and driven properly to form a frame part. As the transparent electrodes 150 for the frame, for example, 16 electrodes 150 are arranged on both sides of the arrangement range of the common-side transparent electrode on an upper glass substrate 110. The voltage is outputted to the electrodes 150 for the specific number of selected scanning electrodes and the specific number is increased as the outside temperature rises. Consequently, a light transmission area and a nontransmission area do not coexist in the area on a display screen 102. Consequently, the display quality can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a liquid crystal device, and more particularly to a liquid crystal device using a ferroelectric liquid crystal having memory properties.

[Prior art]

Clark and Lagerwall are Applied Phys.
sics Letters Volume 36, No. 11 (1980
Published June 1, 2013), P, 899-901. or U.S. Patent No. 4,367.924, U.S. Patent No. 4,563,05
9, surface-stabilized ferroelectric liquid crystal (Surface-st
ableized ferroelectric
A bistable ferroelectric liquid crystal (uid crystal) has been revealed. This bistable ferroelectric liquid crystal is arranged between a pair of substrates with a spacing sufficiently small to suppress the formation of a helical alignment structure of liquid crystal molecules in a chiral smectic phase in the bulk state, and a plurality of liquid crystal molecules This was achieved by aligning vertical molecular layers organized in one direction.

A liquid crystal device equipped with a display screen made of such ferroelectric liquid crystal can display large-capacity pixels by using the multiplexing drive method described in, for example, U.S. Pat. No. 4,655,561 by Shindo et al. Images can be formed on the screen. The above liquid crystal device is used in word processors, personal computers, micro printers,
It can be used as a display screen for televisions, etc., but for this purpose it is necessary to incorporate the liquid crystal cell into the housing, fix the periphery of the liquid crystal cell with a frame-shaped fixing member, and use the inside of the frame as the display screen. There is.

Generally, a liquid crystal cell uses a pair of thin glasses facing each other, and it is difficult to curve the liquid crystal cell itself like a CRT display screen, resulting in a flat display screen. For this reason, when the liquid crystal cell is incorporated into the housing, the edge area of the flat liquid crystal display screen is hidden by the convex part of the frame-shaped fixing member mentioned above, and especially the upper part of the display screen from the normal viewing direction. Also, there was a problem in that the displayed image in the lower end area could not be viewed.

Therefore, it is necessary to provide a non-display area in which no display image is formed over an edge area of a width of several mm to several cm within the liquid crystal display screen.

By the way, the ferroelectric liquid crystal element at the time of initial alignment described above is
In the absence of an electric field, domains that produce a bright state and domains that produce a dark state coexist, and depending on the polarity of the applied voltage, the domain produces either a bright state or a dark state. The alignment state of the ferroelectric liquid crystal in the non-display area mentioned above remains the same as the initial alignment state, so domains that cause bright and dark states coexist, which causes display quality to deteriorate. There was a problem with the decline.

[Summary of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal device in which the above-mentioned problems, particularly the deterioration of display quality, are improved.

The present invention provides: (a) an image display section formed by arranging pixels formed at intersections of scanning electrodes and information electrodes in a plurality of rows and columns; a liquid crystal panel having an image non-display area formed by a third electrode; b; scanning line driving means for outputting a scanning signal to the scanning electrode; outputting an information signal to the information electrode so that an image is formed on the image display area; and a frame display driving means for outputting a voltage to the third electrode so that the image non-display portion is in either a bright state or a dark state, and A liquid crystal device comprising a control means for outputting a voltage to the electrode of No. 3 for each predetermined number of selected scanning electrodes, and controlling the driving means so that the predetermined number increases in accordance with a change in external temperature toward a higher temperature side. There are characteristics.

[Detailed description of aspects of the invention]

FIG. 1 shows an embodiment of the invention. Here, l is a main body of a word processor serving as a host device that serves as a source of image data for display to the display device according to this example. 50
1 is a display control device according to this example, which controls the drive of a display according to display data etc. supplied from the word processor main body 1. Reference numeral 100 denotes a display device constructed using FLC (ferroelectric liquid crystal).

200 and 300 respectively control the display device 10 according to drive data etc. supplied from the display control device main body 50 side.
An information line drive circuit that drives information electrodes provided at 0 and a scan line drive circuit that drives scan electrodes. Reference numeral 400 denotes a temperature sensor provided at an appropriate position on the display 100, for example, at a location exhibiting an average temperature.

In the display device 100, 102 is a display screen, 104 is an effective display area on the display screen 102, and 106 is a display screen 10.
This is a frame display section provided outside the effective display area 104 on 2.

In this example, electrodes corresponding to the frame display section 106 are arranged on the display 100 and are driven to form a frame section on the screen 102.

In the display control device 50, 500 is a control section which will be described later with reference to FIG. 4, and controls the transmission and reception of various data with the display 100 and the word processor main body 1. Reference numeral 600 denotes a data output unit, which will be described later with reference to FIG.
0.300, etc., and startup for data setting of the control unit 500. Reference numeral 700 denotes a frame driving section, which forms the frame section 106 on the display screen 102 based on output data from the data output section 600.

Reference numeral 800 denotes a power supply controller which, under the control of the control section 500, appropriately transforms the voltage signal from the word processor main body 1 to generate a voltage to be applied to the electrodes by the display drive sections 200 and 300. Reference numeral 900 denotes a D/A converter placed between the control unit 500 and the power supply controller 800, which converts the digital quantity setting data of the control unit 500 into analog quantity data and supplies it to the power supply controller 800.

Reference numeral 950 denotes an A/D converter disposed between the temperature sensor 400 and the control section 500, which converts analog temperature data detected by the display 100 into a digital amount and supplies it to the control section.

The word processor main body 1 has a function as a host device that is a source of display data for the display device 100 or the display control device 50, and of course can also be used as a host device of other forms, such as a computer or an image reading device. The following data can be exchanged in this example. That is, first, as data supplied to the display control device 50, D = a signal including image data, address data for specifying the display position of the data, and a horizontal synchronization signal.

The address data for making it possible to specify the display address of the image data (corresponding to the display device on the effective display area 104) is the V corresponding to the effective display area 104.
If the host device has a RAM, the address data can be output as is, for example. In this example, the word processor main body 1 superimposes this signal on the horizontal synchronization signal or the blanking signal and supplies it to the data output section 600.

CLK: Image data PDO-PD3 transfer lock.

The data is supplied to the data output section 600.

PDOWN: A signal to notify that the power to the system will be cut off.

It is supplied to the control unit 500 as a non-maskable interrupt (NMI).

shall be.

In addition, as data supplied by the display control device 50 to the word processor main body 1, P ON, 10FF: Notifies that the display control device 50 side has completed startup and shutdown, respectively, when powering on and powering off the system. status.

The control unit 500 outputs.

L i g 11t: A signal instructing on/off of the light source FL combined with the display device 100.

The control unit 500 outputs.

Busy: A synchronization signal that causes the word processor main body 1 to wait for signal transfer, etc. in order for the display control device 50 to perform various settings during initial operation and display operation.

In other words, in this example The processor body 1 receives this Busy signal. Reception is possible.

The control unit 500 supplies the data via the data output unit 600.

FIGS. 2 and 3 are an exploded perspective view and a cross-sectional view, respectively, showing an example of the structure of the display device 100 using FLC. In these figures, 110 and 120 are glass plates placed at the top and bottom, respectively, and provided with polarizers arranged so as to be crossed nicols with respect to the orientation direction of the FLC element. A wiring section 122 is provided on the lower glass substrate 120, and includes a transparent electrode 124 made of, for example, ITO, and an insulating film 126. 128 is a metal layer that is added on the transparent electrode 124 when it is necessary to lower the electrode resistance, and it may not be added if the display is small. 112 is a wiring section provided on the upper glass substrate 110; Transparent electrodes 114 similar to each section 124 and 126 in the wiring section 122 of the lower glass substrate 120
and an insulating film 116.

The wiring directions of wiring portions 112 and 122 are orthogonal to each other. Further, for example, if the effective display area 104 is set to the size of an A5 plate and its long side is used as the horizontal scanning direction,
If a resolution of 0x800 dots is to be provided, the wiring section should have 400 or 80 lines corresponding to the effective display area.
Zero transparent electrode groups are provided.

In this example, the horizontal scanning direction is set to the common side, and a group of 400 transparent electrodes 114 is provided in the upper wiring section 112, and a group of 800 transparent electrodes 124 is provided in the lower wiring section 122. In addition, the effective display area 1 inside the display screen 102
04, transparent electrodes 150.04 for displaying a frame are provided. 151 are provided in the same or different shape from the transparent electrodes 124 and 114 for data display.

130 is an enclosing part for the FLc, 32, which includes a pair of alignment films 136 for aligning the FLC, and a spacer 1 for defining the distance between the alignment films 136 so as to maintain a bistable state.
34. 140 is a sealing material such as epoxy for sealing FLc and 32; 142 is FLc in the enclosing part 130;
A filling port 144 is a sealing member that seals the filling port 142 after filling.

210 and 310 are information line drive circuits 200, respectively.
The segment drive element is a component of the scanning line drive circuit 300, and the common drive element is a common drive element that is a component of the scanning line drive circuit 300. In this example, they are integrated circuits that drive 80 transparent electrodes, and 10 and 5 of them are used, respectively. Arrange.

280 and 380 are boards on which the segment drive element 210 is mounted, and a board on which the common drive element 310 is mounted, 282 and 382 are flexible cables connected to the boards 280 and 380, respectively, and 299 is a flexible cable. This is a connector that connects 282 and 382 and is coupled to the display control device 50 shown in the first diagram.

Reference numerals 115 and 125 indicate lead-out electrodes formed continuously from the transparent electrodes 114 and 124, respectively, and are connected to the drive elements 310 and 210 via film-like conductive members 384 and 284, respectively.

In this example, light is irradiated from the light source FL placed below the lower glass substrate 120, and the FLC element is exposed to the first
Alternatively, display is performed by driving to the second stable state.

When applying the display device shown in FIGS. 2 and 3, there are various problems regarding the characteristics of the FLC element, and in this example, we will focus on these and
The present invention aims to realize an appropriate configuration of a display device 100 using elements and appropriate drive control thereof.

When the display device 100 is configured as shown in FIGS. 2 and 3, a group of transparent electrodes 114 on the common side and a group of transparent electrodes 124 on the segment side are arranged on the display screen 102 corresponding to the range arranged in a matrix. This area is defined as the area where image data can actually be displayed, that is, the effective display area 104, but it is outside the matrix arrangement range of the transparent electrode group (i.e., the scanning electrode group) on the common side, and the sealing material 1
In order to make the effective display area 104 completely visible, it is desirable to make the display screen 102 include a small area (corresponding to a portion) inside the display area 40.

However, if only the transparent electrode group on the common side is placed, the electrode group on either side passes through such a part, and therefore the FLC of that part is not involved in displaying image data. , it becomes something floating. In other words, in such a state, the FLC in that part can be in a bistable state, so the area on the display screen 102 corresponding to that part includes a light-transmitting area (white) and a non-light-transmitting area (black). As a result, not only the aesthetic appearance of the display is impaired, but also it becomes difficult to clearly indicate the effective display area 104, and a situation may occur that may cause an illusion to the operator.

Therefore, in this example, such an effective display area 104
There is also a transparent electrode (
A frame portion 106 is formed by providing a peripheral transparent electrode (hereinafter referred to as a frame peripheral transparent electrode) 15o and driving these appropriately. As the frame circumferential transparent electrodes 150, for example, 16 electrodes 150 are arranged on both sides of the arrangement range of the common-side transparent electrode 114 on the upper glass substrate 110. Note that in FIG. 2, the glass substrate 120. 110
Only one on each side is shown above as a representative, but the wide one
It may also be a transparent electrode around the frame of a book.

FIG. 4 shows an example of the configuration of the control section 500. Here, 50
1 is a CPU in the form of a microprocessor, for example, which controls each part according to the control procedure shown in FIG. 6, and 503 is a CPU 5.
This is a ROM in which a table of programs corresponding to the control procedure shown in FIG. 6, executed by 01, is developed. 505 is CP
U501 is a RAM used for work, etc. in the process of executing control procedures.

PORTI to PORT6 are port sections whose input/output directions can be set, and ports PIO to P17 and P2, respectively.
0~P27, P30~P37, P40~P47, P50
~P57 and P60~P67. PORT
7 is an output port and has P2O-P74.

DDR1 to DDR6 are each a port section PORTI.
This is an input/output setting register (data direction register) for setting the switching of the input/output direction of PORT6. Note that in this example, the port section PORTI
ports P13 to P17 (corresponding to signals A3 to A7), ports P21 to P25 and P27 of port section PORT2
, P2O and P41 of port section PORT4 (corresponding to signals A8 and A9, respectively), ports P53 to P57 of port section PORT5, and port P6 of port section PORT6.
2 and ports P72 to P74 of port section PORT7,
and each terminal MPO, MPI and 5T of CPU50L
BY is unused.

507 and 509 are a reset unit for resetting the CPU 501 and a clock generation unit for supplying an operation reference clock (4MH2) to the CPU 501, respectively.

TMRI, TMR2, and SCI are timers that have a reference clock generation source and a register, and can divide the reference clock according to settings in the register. First, the timer TMR2 divides the reference clock according to the register settings and generates a signal Tout that becomes the system clock of the data output section 600. In the data output section 600, one horizontal scanning period (IH
) is generated. Timer TMR1
is used to adjust the operating time on the program and the IH of the display screen 102, and this adjustment is realized according to the set value to the register.

Furthermore, these timers TMRI and TMR2 supply a signal IRQ3 as an internal interrupt to the CPU 501 when the set time based on the set value expires or when the next time measurement operation starts due to the time up, and the CPU 501 accepts the signal as necessary. .

Note that the timer SCI is not used in this example.

In addition, in FIG. 4, AB and DB are respectively
Internal address bus and data bus connecting the CPU 501 and each section, 511 is a port section PORT5゜POR
This is a handshake controller between T6 and CPU 501.

FIG. 5 shows an example of the configuration of the data output section 600. Here, 601 is a data input section that is connected to the word processor main body 1 and receives a signal and a transfer lock CLK. The signal is sent by the word processor main body 1 with the image signal and horizontal synchronization signal added, and in this example, real address data is superimposed and supplied during the horizontal synchronization signal or horizontal blanking period. be done. Thus, the data input section 601 switches the data output progress depending on whether or not a horizontal synchronizing signal or a horizontal blanking period is detected, and upon detection, recognizes the signal component superimposed at that time as real address data. It is output as real address data RA/D, and when it is not detected, the signal component in between is recognized as image data, and 4-bit parallel image data Do-D3 is output.
Output as .

Further, when the data input section 601 recognizes the input of real address data, it activates the address/data identification signal A/D, and this signal A/D is transmitted to the IRQ generation section 603 and the D.
The signal is guided to the ACT generating section 605. The IRQ generation unit 603 outputs an interrupt signal 1 in response to the input of the signal A/D, and this is supplied to the control unit 500 as an interrupt command IRQI or “℃7 according to the setting of the switch 520, and the line An operation is performed in access mode or block access mode.On the other hand, the DACT generation unit 605
TeL! , signal A/D (7) Indicator 100 according to the incoming
It outputs a DACT signal for identifying whether or not there is an access, and guides this to the control section 500, the m generation section 611, and the gate array 680.

The FEN generating section 611 generates a signal n1 for activating the gate array 680 in response to input of a trigger signal from the FEN trigger generating section 613 when the DACT signal is activated. In the nτ trigger generation section, the control section 500 performs A, /D
A trigger signal is generated by a write signal ADWR that instructs the conversion unit 950 to take in temperature information from the temperature sensor 400. Also, at this time, the m trigger generation section 61
3 is selected by the chip select signal DSO generated by the device selector 621. That is, in order for the control section 500 to read the temperature data, the A/D conversion section 9
When performing the chip selection of No. 50, the HΔ trigger generation section 613 is also selected, and the frame drive is also activated in response to the write signal ADWR.

619 is a signal B that notifies the busy state of the display control device 50 in response to the busy signal IBUSY from the control unit 500.
This is a busy gate that sends USY to the word processor main body 1.

621 receives signals AIO to A15 from the control unit 500, and outputs signals DSO to DS2 for chip selection of the A/D conversion unit 950, D/A conversion unit 900, and data output unit 600 according to the values thereof. Output. 623 is activated in response to the signal m, and at this time, the latch pulse gate array 625 is activated based on the signal AO-A4 from the control unit 500.
Perform a set of The latch pulse gate array 625 is
It is used to select each register in the register section 630, and is configured with a number of bits corresponding to the number of registers in the register section 630. In this example, the register section 630
has 22 areas of 1 byte each, and the latch pulse gate array 625 has a 22-bit structure in which 1 bit corresponds to each area. That is, register selector 623
When a pit is set in the latch pulse gate array 625, the area corresponding to the bit is selected, and the control unit 500 sets a pit in the latch pulse gate array 625.
In response to the supply of the read signal (1) or the write signal WR to the register 5, data is read or written to the selected register via the system data bus.

In the register section 630, RA/DL and R,A/
DU is a real address data register that stores the lower and upper bytes of real address data RA/D, respectively, and this storage is performed by the real address storage control unit 641.

DCL and DCU are horizontal dot count data registers that respectively store the lower and upper bytes of data corresponding to the number of dots in the horizontal scanning line direction of the display (800 dots in this example). The horizontal dot number counter 643, which is activated at the start of transfer of image data DO to D3 and counts an appropriate clock, generates the latch signal LATI ( The unit 645 is caused to generate the generated information.

DM is a drive mode register, into which mode data corresponding to line access or block access is written.

DLL and DLU are registers for common line selection address data, and store the lower and upper bytes of each 16-bit data.

The data stored in the register DL L is block designation address data CA6. CA5 and line designating address data CA4 to CAO are output. Further, the data stored in the register DLU is supplied to the decoder section 650 and output as chip select signals Cπ to C2 for selecting the common drive element 310.

CLI and CL2 are 1-byte areas for storing drive data to be supplied to the common-side drive section 300 when driving common-side lines (line writing) in block access mode, and SLI and SL2 are 1-byte areas for storing drive data to be supplied to the common-side driving unit 300 when driving common-side lines in block access mode. Store drive data to be supplied to the side drive unit 200! This is a byte area.

CBI and CB2 are 1-byte areas that store drive data to be supplied to the common side drive section 300 when driving the common side line during block erase in block access mode, and SBI and SB2 are similarly supplied to the segment side drive section 200. This is a 1-byte area for storing drive data.

CCI and CC2 are 1-byte areas that store data to be supplied to the common side drive section 300 when driving the common side line during line writing in line access mode, and SCI and SC2 are similarly supplied to the segment side drive section 200. This is a 1-byte area for storing drive data.

Continuation (The three 1-byte areas are areas that store data for switching the frame drive unit 700, and are divided into 4-bit units and stored in registers FVI and FCVc.

FV2. FV3. FSVc and FV4 are provided.

A multiplier 661 multiplies the pulse signal Tout from the control unit 500 by, for example, two times. 663A, 663
B.

663C and 663D are three-phase outputs of the multiplier 661.

These are 4-phase, 6-phase, and 12-phase ring counters that divide the horizontal scanning period (IH) into 4 and 3, respectively.

Used for dividing into two and not dividing. This divided period is hereinafter referred to as ΔT. For example, in the case of three divisions, IH is formed by 3ΔT.

665 is a multiplexer for selecting one of the outputs of the ring counters 663A to 663D, and is set according to the contents of the drive mode register DM, that is, according to data indicating how many minutes of lH should be used for driving. be done. For example, in the case of three divisions, the four-phase ring counter 663
Select the output of B.

667 is a four-phase ring counter for each output of ring counters 663A to 663D, and 669 is a multiplexer set similarly to multiplexer 665.

FIG. 6 shows an overview of display control used in the present invention.

First, when the word processor main unit 1 is powered on, the INIT routine is automatically started (step 5l).
ot). Here, the Busy signal is set to "ON" to drive the frame 106, erase the effective display area 104, and perform temperature compensation for each when the power is turned on.Finally, the Busy signal is set to "OFF" to perform the interrupt request "1".
Wait until ℃1 or IRQ2 arrives. This interrupt request m
Alternatively, IRQ2 is generated when address data is transferred from the word processor main body 1, and if address data does not arrive, the program will not be executed and will remain on the display screen 102.

Next, when the address data is transferred and an interrupt request is issued, this internal interrupt request is
Depending on RQ2, according to the procedure of step 5102,
If it is an RQI, the process goes to the LSTART routine, and if it is an I play, the process goes to the BSTART routine. This branch determines whether the above-mentioned block access or line access is used. That is, proceeding to the LSTART routine results in a line access, and proceeding to the BSTART routine results in a block access.

Incidentally, in this example, the setting of IRQI or IRQ2 is manually performed in advance by the switching means 520 disposed at an appropriate part of the display control device main body 50.

When the line access mode is set by the switching means 520 and an IRQI occurs, the L S T A
The RT routine is invoked and the program is executed. Here, the transferred address data is read from the data output unit 600, and this address is displayed in the valid display area 104.
(Step 51)
03 and 5104).

Here, when the line is not the final line, the program and Durham execution branches to the LL I N E routine.

Here, the Busy signal is turned "ON" and line writing for l scanning lines is performed based on the image data transferred next to the address data. Next, set the Busy signal to “OF
F'' and waits for an interrupt request -IRQI (step 5105). When nε is supplied, the LSTART routine is activated again.

If the address data is for the final line in step 5104, program execution branches to the FLLINE routine.

Here, the final line is written based on the transferred image data. Next, frame driving and temperature compensation data are updated, the Busy signal is turned OFF, and an interrupt request nB is waited for (step 5106).

Here, when the interrupt request IRQ is completed, LSTA is executed again.
The RT routine is activated. Display control in line access mode is performed through the steps described above.

On the other hand, when the block access mode is set by the switching means 520 described above, the BSTART routine is activated when IRQ2 occurs due to address data transfer. Here, the Busy signal is turned ON, the transferred address data is read, and it is determined whether the data is the first line of the block, the last line of the effective display area 104, or a line other than the above (step 5107 and 5108).Here, if the address data is the first line but not the last line, the process branches to the LIN E routine.Here, one line of line writing is performed based on the transferred image data.Next, , the Busy signal is turned OFF and waits for an interrupt request (step 5109).If there is an internal interrupt request IRQ2, the BSTART routine is activated again.

In step 3108, address data is valid display area 10.
4, execution branches to the FL I N E routine. Here, line writing for one line is performed. Next, frame drive and temperature compensation data are updated, and the Busy signal is set to “
OFF” and waits for an interrupt request (step 5il).
o). Here, when there is an interrupt request IRQ2, the BS
The TART routine is activated.

At step 8108, if the address data is the first line of the block, execution branches to the BLOCK routine. Here, all blocks to which the line specified by the address belongs are erased, and the area of the block is made "white" (step 5i
ll). Next, the process advances to the LINE routine (step 5109), and the same processing as described above is performed. Follow the steps described above to control the display in block access mode,
Write information.

Furthermore, when the word processor main body 1 sends a power down signal m to the control unit 500, this signal causes a non-maskable interrupt request NMI to be activated, and PWOFF is activated. Here, the Busy signal is turned "ON", the effective display area 104 is erased, and all the areas are made "white". Next, the power status signal and the Busy signal are turned OFF, which causes the word processor main unit to
The power is cut off (step 5112).

As is clear from the above, no matter which of the two forms of display control is implemented, block access and line access, address data is transmitted sequentially, periodically and over the entire effective display area. If the address data is transferred continuously, the refresh drive is used, and if address data of a certain predetermined portion is transferred intermittently, the partial rewrite drive is used.

Note that the details of the control procedure described below will be explained on the premise that address data and image data are transferred from the main body 1 side in refresh mode.

The signals or data between each part used in the above example are summarized as follows.

FIG. 7 shows optimal driving conditions for the FLC at a predetermined temperature used in the present invention. The optimum driving voltage and one horizontal scanning period detected by the temperature sensor 400 are controlled by the control unit 500.

In the present invention, flicker generation in the frame display area 106 can be suppressed by driving the frame display area 106 at a frequency of 20 Hz or higher. At this time, when the external temperature changes, the optimum driving conditions for one horizontal scanning period change as shown in FIG. 7, and when the external temperature becomes low, one horizontal scanning period becomes longer. Therefore, in the present invention, the frame display area 106
In order to maintain the driving frequency of 20 Hz or more, the driving period of the frame display area 106 is set based on the number of counted driving scanning lines, and the higher the temperature, the greater the number of counted scanning lines. Also, the count of this drive scanning line is
This is performed within the control unit 500.

FIG. 8 is an example of a drive waveform of the multi-interlace drive method (interlaced selection method of every two or more lines) used in the present invention.

Figure 8 shows (4M-3) fields F4M-3, (4M
-2) Field F 4M-2, (4M -1) field F4M-1 and 4M field F4M (here, ■
A field is one vertical scanning period. M=1.
Scan selection signal 54n-3 (n=1.2.3-) applied to the 4n-th scan electrode in 2.3...),
4n-scan selection signal 54n applied to the second scan electrode
-2,4n Scan selection signal 5 applied to the 1st scan electrode
A scan selection signal S4n applied to the 4n-1 and 4nth scan electrodes is shown. According to FIG. 8, the scan selection signal 9
3S4n-3 is (4M-3) field F 4M-3
and (4M-I) field F4M-1 (M=1.2.3
...) in the same phase (voltage polarity based on the voltage of the scan non-selection signal) are opposite to each other, and (4M-2) field F 4M-2 and 4M
Field F4M is not scanned, and the same applies to scan selection signal 54n-1. Furthermore, scan selection signals 54n-3 and 54 applied within the l field period
The voltage waveforms n-1 are different from each other, and the voltage polarities of the same phase are opposite to each other.

Similarly, the scan selection signal 54n-2 is such that the voltage polarities (voltage polarities based on the voltage of the scan non-selection signal) in the same phase of the (4M-2) field F4M-2 and the 4M field F4M are opposite to each other. and (4M-3
) field F 4M-3 and (4M-1) field F
In 4M-1, scanning is not performed, and the same applies to the scanning selection signal 5411. Furthermore, the scan selection signals 54n-2 and S4n applied within one field period have different voltage waveforms, and the voltage polarities of the same phase are opposite to each other.

In addition, in the example of the scanning drive waveform shown in Fig. 8, the screen pauses all at once (
For example, the third phase is provided to apply voltage 0 to all pixels constituting the screen at once), and the third phase of the scan selection signal is the voltage O (same level as the voltage of the scan non-selection signal). is set to .

Also, according to FIG. 8, the (4M-3)th field F
The information signal applied to the signal electrode in 4M-3 is a white signal for the scan selection signal 54n-3 (by combining with the scan selection signal 34M-3, the threshold voltage of the ferroelectric liquid crystal is By combining the hold signal (scanning selection signal 54n-3), a voltage ±vo smaller than the dark value voltage of the ferroelectric liquid crystal is applied to the pixel. ) is selectively applied to the scan selection signal 54n-1, and a black signal (scan selection signal 54n-1) is selectively applied.
By combining with 4n-1, a voltage -3Vo exceeding the threshold voltage of the ferroelectric liquid crystal is applied in the second phase to form a black pixel) and the holding signal (scanning selection signal 54n-1) Therefore, a voltage ±v0 smaller than that of ferroelectric liquid crystal is applied to the pixel.
is applied) is selectively applied. And (4
Since the scan non-selection signal is applied to the n-2)th and (4n)th scan electrodes, the information signal is applied as is.

Following the writing of the above-mentioned (4M-3) field F 4M-3, the scanning selection signal S 4n- is applied as the information signal to the signal electrode in the (4M-2) field F 4M-2.
For scanning selection signal S4n, the same black signal and holding signal as described above are selectively applied, and for scanning selection signal S4n, the same white signal and holding signal as described above are selectively applied. Since the scan non-selection signal is applied to the (4n-3)th and (4n-1)th scan electrodes, the information signal is applied as is.

Also, (4M-2) Field F Following 4M-2 <, (4
M-1) In field F 4M-1, as information signals applied to the signal electrodes, a black signal and a holding signal similar to those described above are selectively applied to the scanning selection signal 54n-3, and the scanning The same white signal and hold signal as described above are selectively applied to the selection signal 54n-+. And (4
Since the scan non-selection signal is applied to the n-2)th and 40th scan electrodes, the information signal is applied as is.

(4M-1) Continuing from field F4M-1, as the information signal applied to the signal electrode in 4M field F4M, the same black signal and hold signal as described above are selected for scanning selection signal 54n-z. scan selection signal S4n
, the same white signal and hold signal as described above are selectively applied. and (4n-3)th and (4n-
1) Since the scan non-selection signal is applied to the th scan electrode, the information signal is applied as is.

9A, 9B, and 9C show timing charts when the display state shown in FIG. 9D is written using the drive waveform shown in FIG. 8. Figure 9 (D)
Inside, ○ represents a white pixel, and . represents a black pixel. or,
1 in Figure 9(B). - 51 is a time series waveform of the voltage applied to the intersection of the scanning electrode S1 and the signal electrode 11.

I2-3. is a time-series waveform of the voltage applied to the intersection of the scanning electrode S and the signal electrode I2. Similarly, I, -52 is a time series waveform of the voltage applied to the intersection of the scanning electrode S2 and the signal electrode 11.

I2-82 is a time-series waveform of the voltage applied to the intersection of scanning electrode S2 and signal electrode I2.

Furthermore, the present invention is not limited to the above-mentioned drive waveform examples (for example, every four scanning lines, every fifth scanning line, every sixth scanning line,
It is possible to scan every 7 lines, preferably every 8 lines or more. Further, the scanning selection signal may have a waveform whose polarity is inverted for each field as shown in FIG. 8, or may have the same waveform for each field.

FIG. 10 schematically depicts an example of a ferroelectric liquid crystal cell. 141a and 141b are In2O3+SnO
A substrate (glass plate) coated with a transparent electrode such as 2 or ITO (indium tin oxide), between which a S m C zero-phase liquid crystal with a liquid crystal molecular layer 142 oriented perpendicular to the glass surface is used. It is enclosed. A thick line 143 represents a liquid crystal molecule, and this liquid crystal molecule 1
43 has a dipole moment (
P) has 144. When a voltage higher than a certain threshold is applied between the electrodes on the substrates 141a and 141b, the helical structure of the liquid crystal molecules 143 is unraveled, and the dipole moment (P
All of the liquid crystal molecules 144 are oriented in the direction of the electric field.
The orientation direction of 3 can be changed. The liquid crystal molecules 143 have an elongated shape and exhibit refractive index anisotropy in the major and minor axis directions. Therefore, for example, if polarizers are placed above and below the glass surface in a crossed nicol positional relationship, ,
It is easily understood that this is a liquid crystal optical modulation element whose optical characteristics change depending on the polarity of applied voltage. Furthermore, when the thickness of the liquid crystal cell is made sufficiently thin (for example, 1μ), the 11th
As shown in the figure, even when no electric field is applied, the helical structure of the liquid crystal molecules is unraveled, and the dipole moment Pa or pb is either upward (154a) or downward (154b). In such a cell, as shown in FIG.
is applied for a predetermined period of time, the dipole moment changes direction to upward direction 154a or downward direction 154b with respect to the electric field vector of electric field Ea or Eb, and accordingly, the liquid crystal molecules
stable state 153a or second stable state 153b
Orient in either direction.

There are two advantages to using such a ferroelectric liquid crystal as an optical modulation element. Firstly, the response speed is extremely fast, and secondly, the alignment of liquid crystal molecules has a bistable state. To explain the second point with reference to FIG. 11, for example, when the electric field Ea is applied, the liquid crystal molecules enter the first stable state 153a.
This state is stable even when the electric field is turned off.

Furthermore, when an electric field Eb in the opposite direction is applied, the liquid crystal molecules are oriented to a second stable state 153b and change their orientation, but they remain in this state even after the electric field is turned off. Further, as long as the applied electric field Ea does not exceed a certain darkness value, each orientation state is maintained. In order to effectively realize such fast response speed and bistability, it is preferable for the cell to be as thin as possible, and generally from 0.5μ to
20μ, especially 1μ to 5μ is suitable.

〔Effect of the invention〕

According to the present invention, the display quality was improved and it was possible to suppress the occurrence of flicker in the frame display area that occurred in response to changes in external temperature.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the apparatus of the present invention. Figure 2 shows
FIG. 2 is an exploded perspective view of a display used in the present invention. FIG. 3 is a sectional view of the display panel used in the present invention. FIG. 4 is a block diagram of the control section used in the present invention. Figures 1 and 2 are perspective views of the ferroelectric liquid crystal element used in the present invention. It is. FIG. 5 is a block diagram of the data output section used in the present invention. FIG. x is a flowchart of the display control procedure used in the present invention. Figure 1 is the centermost one? FIG. Diagram (D) shows an example of display of the matrix electrode used in the present invention. 10th side 11th figure/b4b(f'b) 5jb

Claims (1)

[Claims] (1) a. An image display section formed by arranging pixels formed at intersections of scanning electrodes and information electrodes in a plurality of rows and columns;
a liquid crystal panel having an image non-display section formed by a third electrode arranged outside the image display section and parallel to the scanning electrode; b. scanning line driving means for outputting a scanning signal to the scanning electrode; and an image display section. an information line driving means for outputting an information signal to the information electrode so that an image is formed; and a voltage is output to the third electrode so that the image non-display section produces either a bright state or a dark state. and (c) outputting a voltage to the third electrode every predetermined number of selected scanning electrodes, and the predetermined number increases in response to a change in external temperature toward a higher temperature side. A liquid crystal device comprising: control means for controlling the driving means so as to perform the following steps.