JPH0199351A - Carrier recovery circuit - Google Patents

Abstract

PURPOSE:To synchronize with a carrier even when a non-modulation signal is inputted by switching a voltage controlled oscillator means forming a phase locked loop in connection with a digital processing means into the connection with a DC voltage shift means in receiving the output synchronization detection signal from a clock recovery means. CONSTITUTION:In receiving a modulation signal subject to orthogonal modulation, a voltage control oscillation means 40 is connected to a digital processing means 30 to form a phase locked loop by using a frequency of four signal arranging points on a modulation phase plane as a lock signal. On the other hand, in receiving the non-modulation wave, clock recovery in the clock recovery means 70 is disabled and the output of synchronism detection signal is used and a changeover means 60 connects the output of a DC voltage shift means 50 to output the result to the voltage controlled oscillation means 40 to form a PLL loop of single phase synchronizing type coupled with one signal of two channels of the orthogonal detection means 10 and one of four signal arrangement points on the modulation wave phase plane is used as the lock frequency. Thus, the synchronizing processing is applied to the non-modulation wave.

Description

[Detailed Description of the Invention] [Summary] Regarding the carrier wave recovery circuit in the demodulation section of a digital multiplex radio device using a phase modulation method, a bypass circuit is added to the carrier wave recovery circuit, and when an unmodulated signal is detected, The frequency pull-in point is one of the four signal distribution points on the modulated wave phase plane.
The purpose of this study is to switch to a single-phase periodic PLL loop that is a point, and to be able to synchronize with the carrier wave even when an unmodulated signal is input.・Quadrature detection means for detecting the ■channel and Q channel of the input signal whose phase-modulated carrier wave is modulated to an intermediate frequency, and identification for identifying the outputs of the two channels from the quadrature detection means and regenerating them into digital signals. a reproducing means; a digital processing means for comparing the phases of digital signals corresponding to four signal distribution points on a modulated wave phase plane output from the discriminating and reproducing means and converting the average of the phase differences into a voltage; The detection output of one of the two channels detected by the voltage-controlled oscillation means, in which the frequency of the free-running oscillation signal is controlled by the output voltage from the processing means, and the orthogonal detection means, is detected in the input signal. DC voltage shifting means applies shift processing to the voltage controlled oscillation means in synchronization with the channel phase, and DC voltage shifting means regenerates a clock from the input signal and detects a state in which the clock cannot be regenerated. The voltage controlled oscillation means, which is connected to the clock regeneration means for detecting out-of-synchronization and the digital processing means to form a phase-locked loop, is connected to the DC voltage shift means when the out-of-synchronization detection signal is received from the clock regeneration means. and switching means for switching to.

[Industrial application field]

The present invention relates to a carrier wave regeneration circuit in a demodulator of a digital multiplex radio device using a phase modulation method.

In digital multiplex radio equipment, the “
Phase modulation (PSK) transmits 0" and "1" corresponding to the phase of the carrier wave, and amplitude/phase modulation (Q
A modulation method such as AM) is used.

The phase demodulator of a digital multiplex radio device that uses such a phase modulation method also has a demodulation function for a meeting line. A means of synchronizing the carrier wave to the carrier wave may be required.

[Conventional technology]

FIG. 3 is a block diagram illustrating a conventional example, FIG. 4 is a diagram illustrating the configuration of a receiver of a digital multiplex radio, and FIG. 5 is a diagram illustrating the state of orthogonal detection.

FIG. 4 shows the configuration of a receiver 200 of a digital multiplex radio device, which includes: a microwave amplifying section 210 that amplifies phase-modulated microwaves of several hundred MHz to several tens of GHz to a predetermined level; The output from the local oscillation unit 230 that generates microwaves from 100 MHz to several GHz, and the microwave amplification unit 210
A mixer 220 and a local oscillator 230 that generate an intermediate frequency from several tens of MHz to several hundred MHz by mixing the output of the mixer 220 and the output of )24
0, and a demodulation section 250 that demodulates the microwave (2) subjected to amplitude/phase modulation (hereinafter referred to as QAM) into digital data (2).

FIG. 3 shows a functional block diagram of the carrier recovery circuit 250a in the demodulator 250 shown in FIG. Corresponding to the ■channel and Q channel, quadrature detection circuits 253 and 255 perform orthogonal detection of the ■channel and Q channel, and an analog/digital conversion circuit (hereinafter referred to as A/
256 and 257 (referred to as a D conversion circuit), a clock regeneration circuit 258 that regenerates the clock included in the input signal ■ from the input signal ■, and a phase comparison function of a phase-locked loop configured for carrier wave regeneration. a digital processing circuit 259 that converts the phase comparison result into a voltage and supplies it to the voltage controlled oscillation circuit 261 via the LPF circuit 260; and an LI'F circuit that passes the output signal of the digital processing circuit 259 below a predetermined frequency band. 260 and LPF circuit 2
A voltage controlled oscillation circuit (hereinafter referred to as a VCO circuit) 261 oscillates a signal of a predetermined frequency using the output voltage of 60 and supplies it as a regenerated reference carrier wave to a quadrature detection circuit 253 and 255 via a branch circuit 254; Vessel 253.
Capacitor CI that cuts the DC component of the output of 255,
C2 and a resistor R1°R2 that supplies a bias voltage VllIA3 to the A/D conversion circuits 256 and 257.

Incidentally, the ■ channel and Q channel of the QAM modulated signal which is the input signal ■ are expressed in a phase space as shown in Fig. 5, and C
The signals of the four signal distribution points on the phase plane of the modulated wave modulated by AM (the space indicated by the diagonal line O) are detected by the quadrature detection circuits 253 and 255 to the level of the white O of the ■ channel and the Q channel, and this is set to "0". "level" and "1" level are taken out via capacitors C1 and C2 as signals that appear in accordance with the transmitted data.

A digital processing type carrier wave regeneration circuit 2 as shown in FIG.
50a, when the phase-modulated input signal ■ is detected, the digital processing circuit 259 → LPF circuit 260 → VCO circuit 261 - quadrature detection circuit 253, 255 A/D conversion circuit 256.257 → phase lock of the digital processing circuit 259 This circuit forms a droop (hereinafter referred to as a PLL loop) and extracts synchronously demodulated digital data (2).

The digital processing circuit 259 processes signals at four signal distribution points on the modulated wave phase plane shown in FIG.
PL at phase points (0', 90°, 180°, 270'')
When the frequency of the L loop is pulled in and the average value thereof is within the lock range, the free-running frequency signal of the PLL loop follows the pulled-in frequency signal.

The DC voltage input to the A/D conversion circuits 256 and 257 in the carrier wave regeneration circuit 250a is configured to remove drift due to temperature fluctuations, aging, etc., in order to prevent deterioration of the error rate of the main signal in the carrier liquid. ing.

Note that drift refers to extremely low frequency noise that appears at the output without an input signal.
This has the effect that S shifts from a predetermined position and the mark rate changes.

That is, in order to eliminate drift, the quadrature detection circuit 2 in the previous stage
53.255 is a capacitor CI that cuts the DC component,
Separate using C2, A/D conversion circuit 256°257
The DC offset of is determined by supplying the bias voltage V1^3 through the resistors R1 and R2 after cutting off the DC current, or by supplying the bias voltage V1^3 through the resistors R1 and R2, or by using the output of the drift control circuit (not shown) (for example, the output of the A/D conversion circuit 256, 257 as the reference). The bias voltage VIIAS is supplied based on the result of comparison with the voltage.

[Problem that the invention seeks to solve]

In the case of the configuration shown in FIG. 3, for example, if the input signal (2) is input without modulation, the signal outputted via the quadrature detection circuits 253, 255 will be a series of "0" or "1", and therefore the main Since the signal component is DC-cut by the capacitors CI and C2, a PLL loop is not formed, so there is a problem that the input signal (2) cannot be synchronized.

The present invention provides a single-phase periodic PLL in which a bypass circuit is added to the carrier wave regeneration circuit, and when an unmodulated signal is detected, the frequency pull-in point becomes one of four signal distribution points on the modulated wave phase plane. The purpose is to switch to a loop and enable synchronization to the carrier wave even if an unmodulated signal is input.

[Means for solving problems]

FIG. 1 shows a block diagram illustrating the invention in detail.

The principle block diagram of the present invention shown in FIG. 1 shows a functional block diagram of a carrier regeneration circuit 150 having the same function as that explained in FIG. orthogonal detection means 10 for detecting the ■channel and Q channel of the input signal modulated into {circle around (2)}; and identification and reproducing means 20 for identifying the outputs of the two channels detected by the quadrature detection means 10 and reproducing them into digital signals. , a digital processing means 30 that compares the phases of digital signals corresponding to four signal distribution points on the modulated wave phase plane outputted from the identification/reproduction means 20, converts the average of the phase differences into a voltage, and outputs the voltage; A voltage-controlled oscillation means 40 whose frequency of the free-running oscillation signal is controlled by the output voltage from the means 30, and a detection output of one of the two channels detected by the orthogonal detection means 10 as the input signal. a DC voltage shifting means 50 for applying shift processing to the voltage controlled oscillation means 40 in synchronization with the phase of the channel concerned; A clock reproducing means 70 for detecting synchronization of the input signal, and a digital processing means 3
0 to form a phase-locked loop, switching means 60 switches the voltage controlled oscillation means 40 connected to DC voltage shift means 50 to connect it to the DC voltage shift means 50 when receiving an out-of-synchronization detection signal from the clock regeneration means 70. It is composed of

[For production]

■When an orthogonally modulated modulation signal consisting of a channel and a Q channel is input, the voltage controlled oscillation means 40 is connected to the digital processing means 30 and the frequencies of the four signal distribution points on the modulated wave phase plane are input as signals. Forms a phase-locked loop.

On the other hand, when a non-modulated wave is input, clock recovery in the first stage of clock recovery 70 becomes impossible, and as a result, the out-of-synchronization detection means in the clock recovery means 70 detects out-of-synchronization.

In response to this out-of-synchronization detection signal, the switching means 60 connects the output of the DC voltage shift means 50 to the voltage controlled oscillation means 40 to output one signal (DC signal) of the two channels of the quadrature detection means 10. Single-phase synchronous type P combined with
An LL loop is formed and one of the four signal distribution points on the modulated wave phase plane is configured to be the pull-in frequency, making it possible to perform synchronization processing even for non-modulated waves.

〔Example〕

The gist of the present invention will be specifically explained below with reference to an embodiment shown in FIG.

FIG. 2 shows a block diagram illustrating the invention in detail. Note that the same reference numerals refer to the same objects throughout the plan.

The configuration of the embodiment of the present invention shown in FIG. 2 includes the branch circuits 251, 252, 254 explained in FIG. 3 and the orthogonal detection circuit 253 corresponding to the two channels as the orthogonal detection means 10 explained in FIG. Quadrature detection section 10a consisting of .255
.

The A/D conversion circuits 256 and 257 described in FIG. The explained digital processing circuit 259 and the LPF explained in FIG.
A voltage controlled oscillator 40a consisting of a circuit 260 and a vCO circuit 261 is used as a DC voltage shift means 50, for example, to synchronize the detection signal of the ■ channel (a DC signal having an "O" or "1" level) with the phase of the I channel. The DC voltage shift circuit 50a that performs the shift processing and the switching means 60 connect the output of the digital processing circuit 259 to the LPF circuit 260 when a modulated signal is detected, and connect the output of the digital processing circuit 259 to the LPF circuit 260 when a non-modulated signal is detected. Output to LPF circuit 260
A switching unit 60a that switches the connection to.

The clock reproducing means 70 includes a clock reproducing circuit 258 which, when a modulated signal is detected, regenerates a clock from the modulated signal and sends it as a conversion timing to the A/D converter circuits 256 and 257, and a clock reproducing circuit 258 which detects an unmodulated signal. In such a case, clock regeneration becomes impossible, and the clock regeneration unit 70a includes an out-of-synchronization detection circuit 71 that detects this situation as an out-of-synchronization signal and outputs an out-of-synchronization signal as a switching control signal for the switching unit 60a. This is an example.

In this embodiment, when the amplitude/phase modulated input signal ■ is input, the I channel component and the Q
The channel components were detected by quadrature detectors 253° and 255.
By alternately taking out DC signals having a level of 0" or 11 levels through capacitors C1 and C2, the identification and reproducing unit 20
The main signal of the carrier wave is transmitted to a.

On the other hand, the clock regenerated from the modulated signal by the clock regeneration unit 70a is sent to the identification and regeneration unit 20a, and at this timing, the ■ channel component and the Q channel component are each converted into digital data ■ and output, and are also sent to the digital processing circuit 259. Synchronous processing of the main signal is performed.

Next, when the unmodulated input signal (2) is input, the clock regeneration unit 70a cannot reproduce the clock because there is no clock to be synchronized. As a result, the out-of-sync detection circuit 71 outputs the out-of-sync signal as a switching control signal for the switching unit 60a, and switches the switching unit 60a to the DC voltage shift circuit 50a.
and the LPF circuit 260.

Note that when the switching unit 60a receives the “0” level from the out-of-sync detection circuit 71, the switching unit 60a switches the digital processing circuit 259 to the LPF.
The DC voltage shift circuit 50a is connected to the LPF circuit 260 when the level is "1".

On the other hand, the output of the quadrature detectors 253 and 255 is “0” or “
l'' level becomes a continuous signal, one of which is taken in by the DC voltage shift circuit 50a, and its output is corrected and sent to the LPF circuit 260 at the same timing as the output from the digital processing circuit 259 is sent to the LPF circuit 260. Send to.

As described above, by switching the PLL loop between when a modulated signal is input and when a non-modulated signal is input, carrier wave synchronization processing can be performed even when a non-modulated signal is input.

〔Effect of the invention〕

According to the present invention as described above, it is possible to perform synchronization processing even on non-modulated waves.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a block diagram explaining a conventional example, and FIG. 4 is a receiving digital multiplex radio. Figure 5 is a diagram explaining the configuration of the machine, and Figure 5 is a diagram explaining the quadrature detection situation. In the figure, 10 is a quadrature detection means, 10a is a quadrature detection section, 20
20a is an identification/reproduction unit; 30 is a digital processing unit; 40 is a voltage controlled oscillation unit; 40a is a voltage controlled oscillation unit; 50 is a DC voltage shift unit; 50a is a DC voltage shift circuit; 60 is a switching unit; 60a is a switching unit, 70 is a clock regeneration means, 70a is a clock regeneration unit, 71 is an out-of-synchronization detection circuit, 150, 150a, 250a are regeneration circuits, 210 is a micro castle amplification unit, 220 is a mixer, 240 is an AGC circuit,
250 is a demodulation section, 251, 252, 254 is a branch circuit, 253, 255 is a quadrature detection circuit, 256, 257 is an A/D conversion circuit, 258 is a clock regeneration circuit, 259 is a digital processing circuit, 260 is an LPF circuit, 261 is the VCO circuit, nuclear submarine Toro 1 cost source only F0 ground light 3 Brotzfu diagram 1 time

Claims (1)

[Claims] In a demodulator of a digital multiplex radio using a phase modulation method that reproduces carriers of four signal distribution points on a phase plane of orthogonal modulated waves displayed on an I channel and a Q channel, an input signal is orthogonal detection means (10) for detecting a modulated signal consisting of an I channel and a Q channel when modulated to an intermediate frequency; and identifying the outputs of the two channels from the orthogonal detection means (10) and converting them into digital signals. Comparing the phase of the digital signal corresponding to the four signal distribution points on the modulated wave phase plane outputted from the identification and reproduction means (20) to be reproduced, and converting the average of the phase differences into a voltage. a digital processing means (30) for outputting a free-running oscillation signal; a voltage-controlled oscillation means (40) in which the frequency of the free-running oscillation signal is controlled by the output voltage from the digital processing means (30); and the orthogonal detection means (10). A DC voltage shift process in which the detected output of one of the two channels detected by the output is shifted so as to be synchronized with the phase of the channel in the input signal, and applied to the voltage controlled oscillation means (40). means (50); clock regeneration means (70) for regenerating a clock from the input signal and detecting a state in which the clock cannot be regenerated to detect out-of-synchronization of the input signal; and the digital processing means ( 30) to form a phase-locked loop.
0) to the connection with the DC voltage shift means (50) when an out-of-synchronization detection signal is received from the clock regeneration means (70), and when an unmodulated input signal is input. , the clock regeneration means (70) detects out-of-synchronization, and based on the out-of-synchronization detection signal, the switching means (60) connects the DC voltage shift means (50) to the voltage controlled oscillation means (40). A carrier wave regeneration circuit characterized in that a phase-locked loop is formed by using a carrier wave.