JPH0199321A - Multi-stage counter circuit - Google Patents

Abstract

PURPOSE:To realize a multi-stage counter circuit with simple constitution by applying count of a prescribed digit, using a count means to count low-order digits and using a sequential means to count high-order digits and applying carryout decision to the result of count via a time division processing means. CONSTITUTION:In counting plural digits by a multi-stage counter circuit 2a, the low-order digits at a fast speed are counted by a counter means 10 comprising series connection of N-adic counters and high-order digits are counted by a sequential means 20, the result is subject to time division processing by a time division processing means 30 and carry-out decision is applied to the result of processing. Thus, the number of N-adic counters connected in series is reduced remarkably to reduce component cost and the multi-stage counter circuit smaller than the mount space is formed.

Description

[Detailed Description of the Invention] [Summary] Regarding a multi-stage counter circuit for dropping an input signal into multiple stages, a multi-stage counter circuit with a simple configuration is realized without increasing the number of parts or mounting space in proportion to the number of digits. The purpose is to calculate the current state by combining a counting means that performs counting by connecting multiple n-ary counters in series, adding the output from the counting means, and two inputs added via the inside. A sequential means that sequentially outputs the state that has transitioned from one to the next state according to the input, and a time-sharing process that performs time-sharing processing on the output state from the sequential means and the output from the counting means, and determines carry-out from the processing result. When counting a predetermined number of digits, the counting means counts the lower digits, the upper digits are counted by the ordering means, and the counting results are subjected to a carry-out determination via the time-sharing processing means. do.

[Industrial application field]

The present invention relates to a multistage counter circuit for dropping an input signal into multiple stages.

For example, when creating a synchronization signal used during data transfer in a digital data transmission system, a mask signal at a predetermined speed is slowed down to a predetermined speed using a counter circuit or the like.

In this case, counter circuits and the like are generally required to have low component costs and require a smaller mounting space.

[Conventional technology]

FIG. 4 shows a block diagram illustrating a conventional example.

FIG. 4 is a diagram showing a conventional example of an N''-digit multi-stage counter circuit 2, which is an N-ary counter 1 (1) to 1 (m) (
However, N=2.3. ...) are connected in series in m stages.

In the above example, the number of stages of N-ary counters 1 (1) to 1 (m) indicates the number of digits to be counted. For example, in the case of a 3-digit counter, 3 stages of N-ary counters 1 (1) to 1 (3) will be connected in series.

In addition, the input of the first stage N-ary counter 1 (1) is the input signal ■
The N-ary counter 1 (m) at the final stage becomes a carry-out CO■ indicating a count output of m digits.

That is, the input signal ■ is sequentially decreased by N-ary counters 1 (1) to 1 (m), and when it reaches the target value as m stages,
Output carryout CO■.

[Problem that the invention seeks to solve]

In the conventional example described above, the multi-stage counter circuit 2 is realized by connecting the N-ary counters 1 (1) to 1 (m) in series, so in this case, the number of counters connected in series depends on the number of digits to be counted. It will increase.

Therefore, there are problems such as a large mounting space (as well as an increase in the number of parts used, which increases costs).

An object of the present invention is to realize a multistage counter circuit with a simple configuration without increasing the number of components or mounting space in proportion to the number of digits.

[Means for solving problems]

FIG. 1 shows a block diagram illustrating the invention in detail.

The principle block diagram of the present invention shown in FIG. 1 shows a multi-stage counter circuit 2a having the same function as that explained in FIG. 20 is a counting means that adds the output from the counting means 10, and also sequentially calculates the state that has transitioned from the current state to the next state according to the input by a combination of two inputs that are applied via the inside of the counting means 10. It is an ordering means to output, and 3
0 is a time-sharing processing means that time-sharingly processes the output state from the ordering means 20 and the output from the counting means 10, and makes a carry-out judgment based on the processing result, and constitutes a multi-stage counter circuit 2a. This is a means to solve this problem.

[For production]

When counting multiple digits with the multi-stage counter circuit 2a of the present invention, the lower digits, which are faster, are counted by the counting means 10 in which N-ary counters are connected in series, the upper digits are counted by the sequential means 20, and these are time-divided. By configuring the processing means 30 to perform time division processing and carry out determination based on the processing result, it is possible to reduce the number of N-ary counters connected in series.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 and 3.

FIG. 2 is a block diagram illustrating the present invention in detail, and FIG. 3 is a diagram illustrating a time chart in an embodiment of the present invention. The same reference numerals indicate the same objects throughout the figures.

The present embodiment shown in FIG. 2 is a multi-stage counter circuit with N'' stages, and its configuration consists of the counting section explained in FIG. 1(
1) A counting unit 10a consisting of 1) to 1(i), a FIFO circuit with N' to N'' digits as a sequential means 20 (a circuit that first takes out the first thing that occurs or the first thing that arrives) 21
, an adder circuit 22 that adds two inputs, and a flip-flop circuit (hereinafter referred to as F) that performs count up and carry.
In this example, the sequential section 20a is composed of a sequential section 20a (referred to as F circuit) 23, and the time division processing section 30a is composed of a shift register 31 and an AND circuit 32 as a time division processing means 30.

The FIFO circuit 21 is composed of, for example, a plurality of stages of F and F circuits, each of which corresponds to an N-ary counter, and in this embodiment has a number of stages corresponding to N'-N''' digits.

Also, among the m digits that count the input signal ■, the lower digits from 1 to i are the same as those explained in Figure 4 after connecting N-ary counters 1 (1) to 1 (i) in series. (with the following functions). This counting situation is shown in Figure 3 (1).

The FIFO circuit 21 outputs one digit count value from the N-ary counters 1(1) to 1(i) as it is inputted, and the adder 22 adds the digits one by one to the next addition. At the time of doing this, carry processing is carried out in the F and F circuits 23, and m is sequentially processed from the 1st digit.
Count the upper digits up to the digit.

This counting situation is shown in Figure 3 (2), 'f, Figure 3 (3)
indicates a situation in which the final count value is determined by the lower digits and upper digits in the time division processing unit 30a, and when m digits are reached, a carry-out CO■ is output.

That is, the counting results in the sequential section 20a are sequentially shifted in the shift register 31, and the outputs of the N-ary counters 1(1) to 1(i) in each stage of the counting section 10a and the shift register 3 are processed.
Output Qi at each stage of 1 = (take logical product with 1m,
The logical product result is an m-digit count value carried out as an output (2).

Note that the number of stages of the N-ary counter of the counting section 10a is determined by the number of digits to be counted. Also, the same effect can be obtained by using a memory circuit instead of the FIFO circuit 21.

By configuring the circuit as described above, it is possible to significantly reduce the number of N-ary counters connected in series.

〔Effect of the invention〕

According to the present invention as described above, by significantly reducing the number of N-ary counters connected in series, it is possible to reduce component costs and provide a multi-stage counter circuit with a smaller mounting space. There is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a diagram explaining a time chart in an embodiment of the present invention, FIG. 1A and 1B respectively show program diagrams for explaining the conventional example. In the figure, 1(1) to 1(i) to 1(1) are N-ary counters, 2.2
a is a multistage counter circuit, 10 is a counting means, 10a is a counting section, 20 is a sequential means, 20a is a sequential section, 21 is a FIFO circuit,
22 is an adder circuit, 23 is an F, F circuit,
30 is a time division processing means; 30a is a time division processing unit; 3
1 is a shift register, and 32 is an AND circuit. Principle of Mismatch 1 Remei Maruburu J 7.7 II No. 11
wing

Claims (1)

[Claims] Counting means (10) that performs counting by connecting a plurality of n-ary counters in series; and two inputs that add the output from the counting means (10) and are added via the inside thereof. a sequential means (20) that sequentially outputs states that have transitioned from the current state to the next state according to the input; and an output state from the sequential means (20) and an output from the counting means (10); and time-sharing processing means (30) for time-sharing processing and determining carry-out from the processing results, and when counting a predetermined digit, the lower digits are counted by the counting means (30).
10) A multi-stage counter circuit characterized in that the higher digits are counted by the ordering means (20), and the count result is subjected to a carry-out determination via the time division processing means (30).