JPH0197661A - Control circuit for multi-head dot matrix printer - Google Patents

Abstract

PURPOSE:To prevent microprocessor operation from slowing down by reading dot-train information for driving a head from a dot memory at the intervals set by print timing control circuits. CONSTITUTION:Dot-train information for driving a head is read from dot memories 7-1-7-4 at intervals set by print timing control circuits 8-1-8-4, and no request about printing is sent to a microprocessor so as to prevent microprocessor operation from slowing down. The microprocessor 1 does not communicate with the control circuits during printing, and operates independent of the control circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a printer device used for outputting an OA device, and particularly to a serial multi-head dot matrix printer comprising a plurality of independent dot matrix print heads. This relates to control circuits.

[Conventional technology]

Conventionally, dot matrix printers perform dot matrix printing by using a head capable of printing several dots vertically and moving the head at a constant speed in the main scanning direction. An example is shown in FIG.

FIG. 7 is a diagram for explaining the operating principle of a serial dot matrix printer, and 21 indicates a head.

The method shown in FIG. 8 is generally adopted as a method of controlling such a printer. In the figure, 22 is a microprocessor, 23 is a memory, and 24 is an input/output interface.

Then, a print timing pulse is taken out from the motor moving in the main scanning direction and an interrupt is generated to the microprocessor 22, which causes the microprocessor 22 to take out the dot row information from the memory 23 and transfer it to the input/output interface 24. This drives the print head.

[Problem that the invention seeks to solve]

The conventional methods mentioned above require higher speed and higher density.

In order to satisfy needs such as colorization, it is necessary to arrange multiple heads in parallel or in a staggered pattern. For example, to perform 7-color printing, select Yellow (A).

Heads corresponding to each color of magenta (M), cyan (C), and black (B) are arranged in parallel. When a control circuit like the one shown in Figure 8 is used in a printer with a multi-head configuration like Jin, an interrupt is generated to the microprocessor for each head, and the microprocessor's bus occupancy rate is proportional to the number of heads. increase In addition, K, which prints at high speed, has the problem that the number of interrupts occurring per hour increases, and the microprocessor is unable to perform almost any other processing while printing, resulting in a decrease in the effective printing speed. was there.

Distributing the microprocessors would improve this to some extent, but as long as the printing process is performed by the firmware of the microprocessors, we cannot hope for a dramatic increase in printing speed.

[Means for solving problems]

A control circuit for a multi-head dot matrix printer according to the present invention is a control circuit for a serial multi-head dot matrix printer consisting of a plurality of independent dot matrix print heads, which is not directly connected to a microprocessor and a bus of this microprocessor. The printer is equipped with a dot memory that stores dot row information for each head, and a print timing control circuit that controls the print timing generated from the motor moving in the main scanning direction, and the dot memory is stored at the timing specified by the print timing control circuit during printing. By extracting dot row information from the printer and driving the print head, the print processing request to the microprocessor at each timing can be eliminated, and a reduction in the processing speed of the microprocessor can be avoided.

[For production]

In the present invention, by separating the memory for storing print dot information from the microprocessor bus, the print control and microprocessor operation can be made completely independent.

〔Example〕

Hereinafter, embodiments of the present invention will be explained in detail based on the drawings. ! aK Explain.

FIG. 1 is a block diagram showing an embodiment of a control circuit for a multi-head dot matrix printer according to the present invention, and shows an example in which the present invention is applied to a color printer having an 8 dot x 4 head configuration.

In the figure, 1 is a microprocessor, 2 is a data counter that receives the write partial WR from the microprocessor 1, 3 is a register decoder that receives the output of the data counter 2, and 4-1 and 4-2 are microprocessors, respectively. A register (DREG) inputs data DATA from the processor 1 to a terminal and inputs the output of the register decoder 3 to a terminal CP.

AREG), 5 is a dot row attribute control circuit, 6
-1, 6-2.6-3.6-4 are dot memory address counters, 7-1 (Y-MEN), 7-2 (M
-7-2(,7-3(7-3(C-,7-4C7-4C
B- is a dot memory 8 that stores dot row information for each head that is not directly connected to the bus of the microprocessor 1;
-1(Y8-1(Y-TI, 8-2(M-TI)
M8-2(, 8-3(C8-3(C-TI, 8-4(B
8-4 (B-TI is a print timing control circuit that controls the print timing generated from the motor moving in the main scanning direction, 9 is a motor (main scanning) timing generation circuit (SP-
8CAN). In addition, Y-DRY, M-DRV,
C-DRY.

B-DRY has Y head, M head, C head, respectively.
It is determined by the head drive output for driving the B head.

Then, during printing, print timing control circuits 8-1 to 8-
Dot memories 7-1 to 7-4 at the timing specified by 4.
By extracting dot row information from the print head and driving the head, the print processing request to the microprocessor 1 at each timing is eliminated, and a reduction in the processing speed of the microprocessor 1 is avoided.

Figure 2 is an explanatory diagram showing the relationship between the head and print data.
Figure a) shows the head, and the figure shows the correspondence between dots and bits. In (b), data 1 represents dot printing, and data 0 represents no dot printing.

FIG. 3 is a diagram for explaining the dot string attribute control circuit 5, where MOB and LSB indicate the most significant digit (bit) and the least significant digit (bit) of the attribute data.The attribute data (A input) 0000
0110. Dot data (D human power) 1010110
If 0, Y output...oooo oooo
Store M output...-101011oO,
C output...Stores 10101100.

B output...Stores oooo oooo.

FIG. 4 is an explanatory diagram showing a data stream from the microprocessor 1, that is, printed dot information, where D indicates dot data and A indicates attribute data.

FIG. 5 is an explanatory diagram showing the timing of data storage in the dot memories 7-1 to 7-4, where (&) indicates the write signal WR, (c) indicates the data DATA, and (c) indicates the register 4. -1 (DREG) output, (d) is register 4-
2 (AREG) output, (e) is R/W (memory read/write), (f:l is the output (Y, M, C, B) of the dot row attribute control circuit 5, Q) is the dot memory address This figure shows an aspect of the counter.

FIG. 6 is an explanatory diagram showing print timing, where (a) shows the 5P-8CAN signal of the motor (main scanning) timing generation circuit 9, and (b) and Cc) show the print timing control circuit 8. -20M-TI8-2O signal and C-TIMING signal of print timing control circuit 8-3,
θ) shows M dot printing, and (e) shows C-TIMING.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIGS. 2 to 6.

First, FIG. 2 shows the head configuration of a color printer having an 8-bit x 4-head configuration. As shown in Figure 4, the print head information consists of dot data D and attribute data.This dot data D is data corresponding to the dots of each head (see Figure 2), and the attribute data A is This is data related to color information.

This dot information is sent from the microprocessor 1 in FIG. Sent to 7-4. ' Dot memory address counters 6-1 to 6-4' are counters that provide addresses to be stored, and data counter 2 and register decoder 3 respectively store dot data and attribute data in register 4-1 (DRE).
G), 4-24-2 (counter and decoder for storing in AR. Timing of storing in dot memories ?-1 to 7-4 is shown in FIG. 5).

When performing the above operations, no characters are printed. This operation may be performed, for example, during the line feed time of the printer.

Next, the operation of the dot printing control circuit will be explained.

The print heads shown in Figure 2 are physically separated;
It is assumed that the distance corresponds to time T with respect to the period τ of the timing signal from Tanabata (motor (main scanning) timing generation circuit 9 (8P-8CAM) in FIG. 1) (see FIG. 6).

Then, SP of the motor (main scanning) timing generation circuit 9
-8CAM signal (see Figure 6 (#I)) and the M-TIMING signal of the print timing control circuit 8-2'' (see Figure 6 (#I)).
b)) and C- of the print timing control circuit 8-3.
The TIMING signals (see FIG. 6(c)) are mutually synchronized signals, and the timing (time t=
n ), prints an M (magenta) dot, and at the timing of ■ (time t = n + T), that is, when the C head comes to the position of the M head at time t, prints a C (cyan) dot. In particular, a mixture of magenta and cyan is printed.

Similarly, B (black) and Y (yellow) also generate print timing, but are not printed because they are masked by the dot row attribute control circuit 5 shown in FIGS. 1 and 3.

The microprocessor 1 is not concerned with the operation of the control circuit during this printing operation, and the microprocessor 1 and the control circuit operate independently.

In the above embodiments, the present invention is applied to a color printer having an 8-bit x 4-head configuration, but the present invention is not limited to this.
Essentially, it does not depend on the configuration of the unit.

〔Effect of the invention〕

As described above, the present invention allows printing control and microprocessor operation to be completely independent by separating the memory that stores print dot information from the microprocessor bus. In addition, this control circuit is entirely composed of hardware, and there is no intervening firmware E2. Therefore, the effect is that extremely high-speed operation can be expected.

Since the present invention does not essentially depend on the configuration of the head, it is extremely versatile and extremely effective in that it can improve the printing speed of high-speed, multifunctional printers.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the control circuit of a multi-head dot matrix printer according to the present invention, FIGS. 2 to 6 are diagrams for explaining the operation of FIG. 1, and FIG. 2 shows the head and printing Data relationships, Figure 3 shows attribute control, Figure 4 shows delta stream from microprocessor, Figure 5 shows data storage timing in dot memory, Figure 6 shows print timing, and Figure 7 shows serial dot matrix printer. FIG. 8 is a block diagram showing an example of a conventional printer control method. 1. Microprocessor, T-1 to 7-4...
・Dot memory, 8-1 to 8-4 ・Fist/φ print timing control circuit.

Claims (1)

[Claims] A control circuit for a serial multi-head dot matrix printer consisting of a plurality of independent dot matrix print heads includes a microprocessor, a dot memory that stores dot row information for each head that is not directly connected to the bus of the microprocessor; and a print timing control circuit that controls print timing generated from a motor moving in the main scanning direction, and extracts dot row information from the dot memory at the timing specified by the print timing control circuit during printing and drives the head. . A control circuit for a multi-head dot matrix printer, characterized in that a print processing request to the microprocessor at each timing is eliminated, thereby avoiding a reduction in the processing speed of the microprocessor.