JPH0197075A - Preamplifier circuit for solid-state image pickup device - Google Patents

Preamplifier circuit for solid-state image pickup device

Info

Publication number
JPH0197075A
JPH0197075A JP62253709A JP25370987A JPH0197075A JP H0197075 A JPH0197075 A JP H0197075A JP 62253709 A JP62253709 A JP 62253709A JP 25370987 A JP25370987 A JP 25370987A JP H0197075 A JPH0197075 A JP H0197075A
Authority
JP
Japan
Prior art keywords
circuit
amplifier circuit
signal
feedback
amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62253709A
Other languages
Japanese (ja)
Inventor
Akihito Nishizawa
明仁 西澤
Takuya Imaide
宅哉 今出
Tomoyuki Kurashige
知行 倉重
Hiroyuki Tarumi
垂水 浩幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Image Information Systems Inc
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Video Engineering Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Video Engineering Co Ltd filed Critical Hitachi Ltd
Priority to JP62253709A priority Critical patent/JPH0197075A/en
Publication of JPH0197075A publication Critical patent/JPH0197075A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To completely control clock noise without adjustment by sufficiently reducing the voltage gain of an inversion amplifier circuit only near a clock noise frequency through the use of a filter such as trap in the micro-current amplifier of a feedback type, which feeds back a signal amplified in the inversion amplifier circuit to an input. CONSTITUTION:A titled circuit consists of an image-pickup element 14, the inversion amplifier circuit 11, and feedback circuit 12. When a pulse is impressed on the gate 23 of a MOS transistor 22, the MOS transistor is conducted and a signal load which is photoelectrically converted in a photodiode 21 and the clock noise due to the leakage of the pulse impressed on the gate 23 are impressed on an input terminal 25 and amplified in an amplifier 30. A trap circuit consisting of an inductance 17 and a capacitor 18 removes clock noise components and only signal components are amplified in an amplifier 31 and outputted to an output terminal 24. At the same time, the feedback circuit 12 feeds back a current corresponding to an output signal to the input of the inversion amplifier circuit 11. Consequently, the microcurrent amplifier circuit operates so that it converts only the signal load into the voltage from the input terminal 25.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、テレビカメラ等に用いる固体撮像装置の信号
処理回路に係り、特に、クロックノイズの抑圧に好適な
前置増幅回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal processing circuit for a solid-state imaging device used in a television camera or the like, and particularly to a preamplifier circuit suitable for suppressing clock noise.

〔従来の技術〕[Conventional technology]

テレビカメラ等の倣像デバイスとしては、二次元的に配
置した複数個のホトダイオードに蓄積された信号電荷を
読み出す同体撮像素子が用いられている。!5図はその
一例を示したものである。
2. Description of the Related Art As a copying image device such as a television camera, a solid-state image sensor is used that reads out signal charges accumulated in a plurality of two-dimensionally arranged photodiodes. ! Figure 5 shows an example.

1.2はそれぞれ水平、垂直用の走査回路である。1.2 are horizontal and vertical scanning circuits, respectively.

該走査回路から出力されるパルスによりスイッチ用のM
OSトランジスタを一定の規則に従って導通させ、フォ
トダイオードに蓄積された電荷を順次読み出している。
M for the switch by the pulse output from the scanning circuit
The OS transistors are made conductive according to a certain rule, and the charges accumulated in the photodiodes are sequentially read out.

フォトダイオード3について説明すると、走査回路2か
ら信号林8に出力されたパルスにより、MOSトランジ
スタ4及び6が導通し、次に、走査回路1から信号源9
に出力されたパルスにより、MOSトランジスタ5が導
通し、フォトダイオード3に蓄積された信号電荷をビデ
オ出力軸7の上に取り出すように動作している。そのた
め、走査回路から出力されるパルスが撮像素子内の浮遊
容量やMOSトランジスターのゲート容量を介しビデオ
出力祿の上に偏成し、第4図に示すようなスパイク状の
クロックノイズか発生する。ビデオ出力−の上に取り出
した信号電荷を電圧に変換する前置増幅回路は、りaツ
クノイズに対しても光分なダイナミックレンジを有する
増幅回路でなければ、それに重畳された信号成分が歪ん
でしまう。しかし、該前置増幅回路のダイナミックレン
ジは電源電圧など九より上限が制限される。そこで、従
来は、りaツクノイズを抑圧するために、該りaツクノ
イズと類似な信号をつくりだし、極性を反転して加える
ことによって1浅底分だけを消去していた。
Regarding the photodiode 3, the pulse outputted from the scanning circuit 2 to the signal line 8 makes the MOS transistors 4 and 6 conductive, and then the signal source 9 from the scanning circuit 1 is turned on.
The MOS transistor 5 is turned on by the pulse outputted to the photodiode 3, and operates to take out the signal charge accumulated in the photodiode 3 onto the video output shaft 7. Therefore, the pulses output from the scanning circuit are unevenly distributed on the video output line via the stray capacitance within the image sensor and the gate capacitance of the MOS transistor, generating spike-like clock noise as shown in FIG. The preamplifier circuit that converts the signal charge taken out on the video output into a voltage must have a dynamic range that is light enough to withstand noise, otherwise the signal component superimposed on it will be distorted. Put it away. However, the upper limit of the dynamic range of the preamplifier circuit is limited by the power supply voltage. Therefore, conventionally, in order to suppress the a-thick noise, a signal similar to the a-thick noise was created and added with the polarity reversed, thereby erasing only one shallow part.

〔発明か解決しようとする問題点〕[The problem that the invention attempts to solve]

上記従来技術では、りaツクノイズと類似な信号を作り
出すために、また、その信号で漏洩成分を消去するため
に、必ず調整が必要となる点や、漏洩成分にバラツキが
ある場合、上記−贅を最適にしても漏洩成分を完全に消
去できない点については十分考慮されていなかった。
In the above-mentioned conventional technology, in order to create a signal similar to leakage noise and to eliminate the leakage component with that signal, adjustment is always required, and when there is variation in the leakage component, the above-mentioned The fact that the leakage components cannot be completely eliminated even if optimizing is not sufficiently considered.

本発明の目的は、漏洩成分にバラツキがあっても無調整
で、この漏洩成分をほぼ完全に消去可能な前置増幅回路
を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a preamplifier circuit that can almost completely eliminate leakage components without adjustment even if the leakage components vary.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的は、反転増幅回路と該反転増幅回路で増幅され
た信号を入力KNI還する帰還回路とから構成される帰
還形の微少′t1!L流増幅回路において、トラップ等
のフィルタを用いてりaツクノイズ周波数近傍のみ該反
転増幅回路の電圧利得を十分小さくすることによりて達
成される。
The above object is a feedback type minute 't1! which is composed of an inverting amplifier circuit and a feedback circuit which returns the signal amplified by the inverting amplifier circuit to the input KNI! This is achieved by using a filter such as a trap in the L-flow amplifier circuit and making the voltage gain of the inverting amplifier circuit sufficiently small only in the vicinity of the a noise frequency.

〔作用〕[Effect]

りaツクノイズ周波数近傍のみ反転増幅回路の電圧利得
を十分小さくした帰還形の微少電流増幅回路の伝達イン
ピーダンスは、第6図に示すようにビデオ出力練上の信
号成分に対して大きな伝達インピーダンスになり、クロ
ックノイズ成分に対しては十分小さい伝達インピーダン
スになる。その結果、ビデオ出力嶽上の信号成分のみを
電圧に変換するようになる。
The transfer impedance of a feedback type micro current amplifier circuit in which the voltage gain of the inverting amplifier circuit is sufficiently small only near the noise frequency becomes a large transfer impedance with respect to the signal component of the video output, as shown in Figure 6. , the transfer impedance is sufficiently small for clock noise components. As a result, only the signal component on the video output is converted to voltage.

これにより、トラップを押入した増幅段以降ではクロッ
クノイズが抑圧されるので該りaツクノイズによる反転
増幅回路の飽和を防止できる。
As a result, clock noise is suppressed after the amplification stage into which the trap is inserted, and saturation of the inverting amplification circuit due to such a clock noise can be prevented.

この方法は位相の急変により発振することがない。また
、該微少電流増幅回路を用いたビデオカメラにおいて画
質の上で何も問題がないことを発見した。次に第5図を
用いて位相の急変で発振しない理由を説明する。14は
撮像素子、11は反転増幅回路、12は帰還回路、10
は電圧制御形電流源、13は正相増幅器、21はフォト
ダイオードを表わしている。反転増幅回路11と殉還回
路12より構成される微少電流増幅回路のループ利得μ
βは図中の記号を用いて表わすと、 Cin″>>C1、1すωc6nRj中)’ct:@J
jとすると、(1)式は、 となる。さらに、このセ)式をmWすると、となる。こ
の(5)式の虚数部が0になる鉋件は、ω=0又は−C
CL−CJRIR)= 1のときである。ω=0のとき
は、tl)式よりループ利得μβがμβ−−Gこれも発
振を起さない。従りて、トラップを入れても発振するこ
とはない。
This method does not cause oscillation due to sudden changes in phase. We also discovered that there were no problems with image quality in a video camera using the microcurrent amplification circuit. Next, the reason why oscillation does not occur due to a sudden change in phase will be explained using FIG. 14 is an image sensor, 11 is an inverting amplifier circuit, 12 is a feedback circuit, 10
13 represents a voltage-controlled current source, 13 represents a positive phase amplifier, and 21 represents a photodiode. Loop gain μ of the minute current amplification circuit composed of the inverting amplification circuit 11 and the reduction circuit 12
When β is expressed using the symbols in the figure, Cin''>> C1, 1s ωc6nRj)'ct: @J
When j, equation (1) becomes. Furthermore, when this equation (C) is converted to mW, it becomes. The case where the imaginary part of equation (5) becomes 0 is ω=0 or −C
CL-CJRIR)=1. When ω=0, the loop gain μβ is μβ−−G from the equation (tl), which also does not cause oscillation. Therefore, even if a trap is inserted, oscillation will not occur.

また、−揮素子の出力端にトラップを設け、撮像素子の
出力でりaツクノイズを除去すると、トラップの共振周
tL数におけるトラップ挿入点から微少電流増幅回路出
力間の電圧、vll得が大きい為、該共振ノー波数で微
少−流増鳴回路出力に大きなノイズが発生してしまう。
In addition, if a trap is provided at the output end of the volatile element and a noise is removed from the output of the image sensor, the voltage between the trap insertion point and the minute current amplification circuit output at the resonant frequency tL of the trap, the vll gain, is large. , a large noise is generated in the output of the micro-current loudspeaker circuit at the resonance no wave number.

しかし、反転増幅回路の内部にトラップを入れることに
より、トラップの共氷周波数で大きなノイズを発生させ
ることな(クロックノイズの抑圧かでき、反転増幅回路
に必要とされるダイナミックレンジを小さくできる。
However, by inserting a trap inside the inverting amplifier circuit, it is possible to suppress clock noise without generating large noise at the common frequency of the trap, and it is possible to reduce the dynamic range required for the inverting amplifier circuit.

藁5図に示す微少電流N@回路の伝達インピーダンスZ
(ω)を第6図に示す。遮断周波数はムで、八で伝達イ
ンピーダンスが極端に小さくなる周数数特性となる。ま
た、ム及びhは(41(5)式で表わせる。
Transfer impedance Z of the minute current N@circuit shown in Figure 5
(ω) is shown in FIG. The cutoff frequency is m, and the frequency characteristic is such that the transfer impedance becomes extremely small at 8. Further, m and h can be expressed by equation (41(5)).

j・=2、面       °(51 このように、クロックノイズ@波数近傍のみ反転増幅回
路の電圧利得を十分小さくすることで、クロックノイズ
を抑圧し、該りaツクノイズによる反転増幅回路の飽和
を防止した微少tm増幅回路が実現できる。
j・=2, surface °(51) In this way, by making the voltage gain of the inverting amplifier circuit sufficiently small only in the vicinity of clock noise @ wave number, clock noise can be suppressed and saturation of the inverting amplifier circuit due to clock noise can be prevented. It is possible to realize a minute tm amplification circuit.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の褐1の実施例を纂1図により説明する。 Hereinafter, an embodiment of Brown 1 of the present invention will be explained with reference to Fig. 1.

第1の冥施汐りは、fR像素子14、反転増幅回路11
、鰭還回路12から構成されており、撮像素子14の出
力は反転増幅回路11の入力端子25と帰還回路12の
出力1c接続され、反転増幅回路11の出力は出力端子
24と帰還回路120入力に接続されている。反転増幅
回路11は、入力端子25に増幅器310入力を接続し
、誤増幅器30出力を抵抗52を介し増幅器51の入力
に接続する。幅増器310入力はインダクタンス17と
コンデンサ18の直列回路を介して基準電位に接続し、
該増幅器31出力は出力端子24に接続されている。帰
還回路12は、帰還抵抗20と帰還容量19の並列回路
の一万″を反転増幅回路110入力に、他方を反転増幅
回路の入力に接する。この実施例の動作を説明すると、
MOSトランジスタ22のゲート25にパルスが印加さ
れると該MOSトランジスタ22が導通し、フォトダイ
オード21で光電変換された信号電荷とゲート25に印
刀口したパルスの確れ込みによるクロックノイズとが入
力端子25に印加される。この2つの信号は、増幅器3
0で増幅された後、インダクタンス17とコンデンサ1
8から成るトラップ回路により、クロックノイズ成分を
除去し、信号成分のみが増幅回路31で増幅され出力端
子24に出力電圧を与えると同時圧、該出力信号に応じ
た電流を帰還回路12により反転増幅回路110入力に
帰還するように製作する。この動作は反転増幅回路11
と舟運回路12から構成される微少電流増幅回路の伝達
インピーダンスに着目して見ると、信号成分に対しては
該伝達インピーダンスが大きく、クロックノイズ成分に
対しては十分小さくなる。即ち、該微少電流増幅回路は
、入力端子25から信号電荷のみ電圧に変換するように
動作する。本実施例によれば、キャンセル回路を用いな
いので無liaでりaツクノイズを完全に抑圧でき、こ
の抑圧効果はりaツクノイズの波形が変化しても変わら
ない。
The first effect is the fR image element 14 and the inverting amplifier circuit 11.
, and a fin feedback circuit 12, the output of the image sensor 14 is connected to the input terminal 25 of the inverting amplifier circuit 11 and the output 1c of the feedback circuit 12, and the output of the inverting amplifier circuit 11 is connected to the output terminal 24 and the feedback circuit 120 input. It is connected to the. The inverting amplifier circuit 11 connects the input of the amplifier 310 to the input terminal 25 and connects the output of the error amplifier 30 to the input of the amplifier 51 via the resistor 52 . The width amplifier 310 input is connected to a reference potential through a series circuit of an inductance 17 and a capacitor 18,
The output of the amplifier 31 is connected to the output terminal 24. The feedback circuit 12 connects a parallel circuit of 10,000'' of a feedback resistor 20 and a feedback capacitor 19 to the input of the inverting amplifier circuit 110, and the other to the input of the inverting amplifier circuit.The operation of this embodiment will be explained as follows.
When a pulse is applied to the gate 25 of the MOS transistor 22, the MOS transistor 22 becomes conductive, and the signal charge photoelectrically converted by the photodiode 21 and the clock noise caused by the pulse impressed on the gate 25 are transferred to the input terminal. 25. These two signals are sent to the amplifier 3
After being amplified by 0, inductance 17 and capacitor 1
The trap circuit consisting of 8 removes the clock noise component, and only the signal component is amplified by the amplifier circuit 31. When an output voltage is applied to the output terminal 24, the current corresponding to the output signal is inverted and amplified by the feedback circuit 12. It is fabricated to feed back to the circuit 110 input. This operation is performed by the inverting amplifier circuit 11
Focusing on the transfer impedance of the minute current amplification circuit constituted by the circuit 12 and the navigation circuit 12, the transfer impedance is large for signal components and sufficiently small for clock noise components. That is, the minute current amplification circuit operates to convert only the signal charge from the input terminal 25 into a voltage. According to this embodiment, since no cancellation circuit is used, the non-alias noise can be completely suppressed, and this suppression effect does not change even if the waveform of the noise changes.

さらに、信号成分の数10倍もあるクロックノイズが増
幅器31の入力で抑圧されていることから増幅器31の
ダイナミックレンジを小さくすることが可能になる。
Furthermore, since clock noise, which is several ten times as large as the signal component, is suppressed at the input of the amplifier 31, it is possible to reduce the dynamic range of the amplifier 31.

本発明の第2の実施例を第2図を用いて説明する。第2
の実施例は、第1の実施例において、反転増幅回路11
を具体的な回路とし、さらに、帰還回路12に帰還容量
19を実効的に小さくするフィルタを設けたものである
。反転増幅回路は、ソース接地F E T 54のゲー
トを入力端子25に接続し、ソースを適当な電圧源36
に接続し、ドレインをベース接地トランジスタ37のエ
ミッタに接続するとともに抵抗35を介して適当な電圧
源49に接続する。ベース接地トランジスタ370ベー
スおよびコレクタは、それぞれ、適当な電圧源39、エ
ミッタ接地トランジスタ430ベースに接続する。さら
にベース接地トランジスタ57のコレクタは、抵抗59
を介して基準電圧に接続し、インダクタンス17とコン
デンサ18の直列回路を介して基準電位に接読スる。エ
ミッタ接地トランジスタ43のエミッタおよびコレクタ
は、それぞれ、抵抗42、抵抗44を介して基準電位と
適当な電圧源49に接続する。
A second embodiment of the present invention will be described using FIG. 2. Second
In the embodiment, in the first embodiment, the inverting amplifier circuit 11
is a specific circuit, and the feedback circuit 12 is further provided with a filter that effectively reduces the feedback capacitance 19. The inverting amplifier circuit connects the gate of the common source FET 54 to the input terminal 25, and connects the source to an appropriate voltage source 36.
, its drain is connected to the emitter of the common base transistor 37, and the resistor 35 is connected to a suitable voltage source 49. The base and collector of common base transistor 370 are connected to a suitable voltage source 39 and the base of common emitter transistor 430, respectively. Furthermore, the collector of the common base transistor 57 is connected to a resistor 59.
It is connected to the reference voltage via the inductor 17 and directly read to the reference potential via the series circuit of the inductance 17 and the capacitor 18. The emitter and collector of common emitter transistor 43 are connected to a reference potential and a suitable voltage source 49 via resistor 42 and resistor 44, respectively.

さらに該エミッタ抵抗トランジスタ43のコレクタは、
抵抗40とコンデンサ41の並列回路を介してベース抵
抗トランジスタ37のエミッタと増幅器45の入力に接
続し、該増幅器45の出力は出力端子24に接続する。
Furthermore, the collector of the emitter resistance transistor 43 is
The emitter of the base resistance transistor 37 is connected to the input of an amplifier 45 through a parallel circuit of a resistor 40 and a capacitor 41, and the output of the amplifier 45 is connected to the output terminal 24.

帰還回路12は、#還抵抗20と帰還容Ji19の並列
回路の一方を反転増幅回路11の入力に、他方を抵抗4
8を介して反転増幅回路11の出力に接続し、帰還抵抗
20と抵抗48の接続部より抵抗46とコンデンサ47
の直列回路を介して基準電位に接続する。該帰還回路1
2は、図中の記号を用いて CR1+へ)C冨=C1Ri となるようにR1すなわち抵抗48をvI4整すること
に並列回路と実効的に等しくなり、第1の実施例におけ
る帰還回路12と同じである。反転増幅回路11は、入
力端子25に印加された信号をソース接FET 54お
よびベース接地トランジスタ57で増幅した後、インダ
クタンス17とコンデンサ18から成るトラップ回路に
よりりaツクノイズ成分を除去し、信号成分を増幅器4
5で増幅している。尚、抵抗40とコンデンサ41によ
る帰還は、反転増幅回路11の位相補償のために設けた
ものであり、抵抗42と並列に容量を設けるか又は、増
幅器45を1次のa−パス特性としても良い。本実施例
は、纂1の実施例と等しく同一の効果が得られる。
The feedback circuit 12 has one of the parallel circuits of the feedback resistor 20 and the feedback capacitor Ji19 connected to the input of the inverting amplifier circuit 11, and the other connected to the resistor 4.
8 to the output of the inverting amplifier circuit 11, and a resistor 46 and a capacitor 47 from the connection between the feedback resistor 20 and the resistor 48.
connected to the reference potential through a series circuit of The feedback circuit 1
2 is effectively equivalent to a parallel circuit in which R1, that is, the resistor 48 is adjusted to vI4 so that (to CR1+ using the symbol in the figure) C value = C1Ri, and is equivalent to the parallel circuit in the feedback circuit 12 in the first embodiment. It's the same. The inverting amplifier circuit 11 amplifies the signal applied to the input terminal 25 using a source-common FET 54 and a base-common transistor 57, and then removes a noise component using a trap circuit consisting of an inductance 17 and a capacitor 18, and converts the signal component into a amplifier 4
It is amplified by 5. Note that the feedback by the resistor 40 and capacitor 41 is provided for phase compensation of the inverting amplifier circuit 11, and a capacitor may be provided in parallel with the resistor 42, or the amplifier 45 may be configured with a first-order a-path characteristic. good. This embodiment is the same as the embodiment of Series 1, and the same effects can be obtained.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、キャンセル回路を用いる必要がないの
で、無調整でりaツクノイズを完全く抑圧でき、生性性
が大幅に向上する。また、ククックノイズの波形がばら
ついた敵にも同一の効果が得られ、微少電流増幅回路に
必要とされるダイナミックレンジを小さくすることがで
きる効果がある。
According to the present invention, since there is no need to use a cancellation circuit, noise can be completely suppressed without adjustment, and the naturalness is greatly improved. Furthermore, the same effect can be obtained on enemies whose waveforms of crack noise vary, and the dynamic range required for the microcurrent amplification circuit can be reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1の実施例の回路図、第2(2)は
本発明の帛2の実施例の回路図、R3図は撮儂装置の回
路図、纂4囚は1洩クロツクノイズの波形図、w、5図
は前置増幅回路の等価回路図、第6図は伝達インピーダ
ンスを表わした特性図である。 11・・・反転増幅回路   12・・・帰還回路14
・・・撮像素子 閉1図 梵2図 粥づ図 (r Cy J’V Ye 44図 45図 葡6図 周jL&j
Figure 1 is a circuit diagram of the first embodiment of the present invention, Figure 2 (2) is a circuit diagram of the second embodiment of the present invention, Figure R3 is a circuit diagram of the photographing device, and Figure 4 is a circuit diagram of the second embodiment of the present invention. Figure 5 is an equivalent circuit diagram of the preamplifier circuit, and Figure 6 is a characteristic diagram showing transfer impedance. 11... Inverting amplifier circuit 12... Feedback circuit 14
...Image sensor closed Figure 1 Figure 2 Diagram porridge (r Cy J'V Ye 44 Figure 45 Figure 6 Figure 6 Circular jL&j

Claims (1)

【特許請求の範囲】[Claims] 1、二次元状に配列された複数の光電変換素子と該光電
変換素子の検出信号を伝達するスイッチ素子と該スイッ
チ素子に順次走査パルスを印加する走査回路とを有する
固体撮像素子から信号電荷を読み取り増幅する前置増幅
回路において、反転増幅回路と帰還回路とフィルタ手段
から成り、該フィルタ手段によって漏洩クロックノイズ
周波数近傍のみ、反転増幅回路の電圧利得を小さくした
ことを特徴とする固体撮像装置用の前置増幅回路。
1. Collecting signal charges from a solid-state imaging device that has a plurality of photoelectric conversion elements arranged in a two-dimensional manner, a switch element that transmits detection signals from the photoelectric conversion elements, and a scanning circuit that sequentially applies scanning pulses to the switch elements. For use in a solid-state imaging device, the preamplifier circuit for read amplification comprises an inverting amplifying circuit, a feedback circuit, and a filter means, and the filter means reduces the voltage gain of the inverting amplifying circuit only near the leakage clock noise frequency. preamplifier circuit.
JP62253709A 1987-10-09 1987-10-09 Preamplifier circuit for solid-state image pickup device Pending JPH0197075A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62253709A JPH0197075A (en) 1987-10-09 1987-10-09 Preamplifier circuit for solid-state image pickup device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62253709A JPH0197075A (en) 1987-10-09 1987-10-09 Preamplifier circuit for solid-state image pickup device

Publications (1)

Publication Number Publication Date
JPH0197075A true JPH0197075A (en) 1989-04-14

Family

ID=17255059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62253709A Pending JPH0197075A (en) 1987-10-09 1987-10-09 Preamplifier circuit for solid-state image pickup device

Country Status (1)

Country Link
JP (1) JPH0197075A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8525591B2 (en) 2010-10-27 2013-09-03 Seiko Epson Corporation Signal level conversion circuit, physical quantity detection device and electronic apparatus

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60137177A (en) * 1984-11-30 1985-07-20 Hitachi Ltd Solid-state image pickup device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60137177A (en) * 1984-11-30 1985-07-20 Hitachi Ltd Solid-state image pickup device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8525591B2 (en) 2010-10-27 2013-09-03 Seiko Epson Corporation Signal level conversion circuit, physical quantity detection device and electronic apparatus
US8829992B2 (en) 2010-10-27 2014-09-09 Seiko Epson Corporation Signal level conversion circuit, physical quantity detection device and electronic apparatus

Similar Documents

Publication Publication Date Title
TW506215B (en) Self compensating correlated double sampling circuit
US7352400B2 (en) Solid-state image pickup apparatus having a differential output
JP3413664B2 (en) Charge transfer device
US7557848B2 (en) Solid-state image pickup device including switched capacitor amplifier
JPH05207220A (en) Solid-state image pickup device and its driving system
EP1875743A2 (en) Illumination flicker detection
JPS6150365A (en) Ccd output signal processing circuit
US4719512A (en) Noise cancelling image sensor
JP3875461B2 (en) Solid-state imaging system
JP3069373B2 (en) Driving method of solid-state imaging device
JPH0197075A (en) Preamplifier circuit for solid-state image pickup device
JPS6337996B2 (en)
JP2000270267A (en) Noise elimination circuit for solid-state image pickup element
JPH0630186A (en) Driving method for image sensor and image sensor
JP2004356866A (en) Imaging apparatus
JPH10164442A (en) Correlated double sampling circuit
JPS605110B2 (en) solid-state imaging device
JPH0224069B2 (en)
US4036763A (en) Noise and drift correcting amplifier circuit for a live-scan imaging system
JP4078144B2 (en) Solid-state imaging device
JP3149126B2 (en) Solid-state imaging device
JPH08237557A (en) Correlator circuit
JP3433518B2 (en) Readout circuit
JPH05328230A (en) Noise reduction circuit
JPH10126698A (en) Output signal processing circuit for ccd image sensor