JPH0196655A - Glass mask - Google Patents

Glass mask

Info

Publication number
JPH0196655A
JPH0196655A JP62252526A JP25252687A JPH0196655A JP H0196655 A JPH0196655 A JP H0196655A JP 62252526 A JP62252526 A JP 62252526A JP 25252687 A JP25252687 A JP 25252687A JP H0196655 A JPH0196655 A JP H0196655A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
orientation flat
pattern
glass mask
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62252526A
Other languages
Japanese (ja)
Inventor
Masaki Kobayashi
正樹 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62252526A priority Critical patent/JPH0196655A/en
Publication of JPH0196655A publication Critical patent/JPH0196655A/en
Pending legal-status Critical Current

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  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To improve precision in aligment of a semiconductor substrate and a glass mask by an exposure and developing process by preparing a pattern for orientation flat besides a pattern necessary for forming a semiconductor element. CONSTITUTION:The pattern 2 with which the alignment with the orientation flat part 4, which is formed on the semiconductor substrate 5, can be precisely carried out is set on the glass mask 1 besides the pattern 3 necessary for the semiconductor element. Therefore, the alignment of the direction of the orientation flat part 4 of the semiconductor substrate 5 to be processed and the glass mask 1 can be precisely executed, so that the direction of a Scribing Line formed on the semiconductor substrate 5 to be processed can be made to precisely coincide with that of the orientation flat part. Thus, not only the occurrence of interdigital shape on a section but also the accident such as a break, etc., in the GaAs semiconductor substrate which is solid and fragile can be prevented and moreover the characteristic of the semiconductor element does not receive effects.

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は半導体素子の製造に不可欠なPEP工程におけ
る1stPEPに適用するガラスマスクの改良に関する
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an improvement of a glass mask applied to 1st PEP in a PEP process essential for manufacturing semiconductor devices.

(従来の技術) マイクロ波半導体素子ならびに集積回路素子等ではシリ
コンを材料とする素子に比べて電子移動度が大きくかつ
飽和ドリフト速度が高いGaAsからなる化合物半導体
装置の需要が年々高まってbする。
(Prior Art) For microwave semiconductor devices, integrated circuit devices, etc., the demand for compound semiconductor devices made of GaAs, which has higher electron mobility and higher saturation drift speed than devices made of silicon, is increasing year by year.

GaAs基板に造込んだFETやMMICttScri
bingにより素子分離するのにブレードダイサを利用
すると。
FET and MMICttScri built into GaAs substrate
A blade dicer is used to separate elements by bing.

硬くてもろいGaAs基板に歪みが入り素子特性に影響
が及ぶので1通常GaAs単結晶のへき関を利用するダ
イヤモンド針によるScribing方式が一般的であ
る。
Since the GaAs substrate, which is hard and brittle, is strained and the device characteristics are affected, a scribing method using a diamond needle that utilizes the gaps in the GaAs single crystal is generally used.

この場合には半導体基板のへき開方向とScrib−i
ng Lineの方向を最低1度以下の精度に保持する
ことによって切断面が鋸歯状に形成されるのを防止して
おり、この両者の方向をこの精度内に維持しない場合に
はGaAs基板が割れてしまう事故が発生する。
In this case, the cleavage direction of the semiconductor substrate and the Scrib-i
By maintaining the direction of the ng line to an accuracy of at least 1 degree, the cut surface is prevented from forming a sawtooth shape, and if both directions are not maintained within this accuracy, the GaAs substrate may crack. Accidents may occur.

一方シリコンやGaAs等からなる半導体基板にはオリ
エンテーション フラット(以後オリフラ部と略称する
)を設置してその結晶のへき開方向を表示しており、最
近ではこのオリフラ部を複数箇所に形成することもある
On the other hand, orientation flats (hereinafter referred to as orientation flats) are installed on semiconductor substrates made of silicon, GaAs, etc. to indicate the cleavage direction of the crystal, and recently these orientation flats are sometimes formed in multiple locations. .

ところで半導体基板に所望の素子を造込むにはいわゆる
PEP (Photo Engraving Proc
ess)工程を数回施し、素子の構造によっては中口以
上に及ぶ。
By the way, so-called PEP (Photo Engraving Proc.
ess) process is performed several times, and depending on the structure of the element, the process may extend to the middle part or more.

このPEP工程には露光及び現像工程が必要であり、そ
の実施にはマスクアライナが使用され、付属するウェー
ハチャックによって処理対象半導体基板のオリフラ部を
検知して自動的に位置合せする方法が採用されている。
This PEP process requires an exposure and development process, and a mask aligner is used to perform this process, and a method is adopted in which the attached wafer chuck detects the orientation flat part of the semiconductor substrate to be processed and automatically aligns it. ing.

(発明が解決しようとする問題点) ところで前記マスクアライナによる半導体基板オリフラ
部の位置合せには機械的手段が利用されるが、場合によ
っては数度の範囲で方向がずれることが避けられなかっ
た。このように位置合せが十分でないまま製造工程を進
めていくと、半導体基板のへき開方向とScribin
g Line方向が不一致となって支障をきたしてしま
う。
(Problems to be Solved by the Invention) By the way, mechanical means are used to align the orientation flat portion of the semiconductor substrate using the mask aligner, but in some cases, it is inevitable that the direction deviates within a range of several degrees. . If the manufacturing process is continued without sufficient alignment, the cleavage direction of the semiconductor substrate and the Scribin
g The line directions will not match, causing problems.

本発明は上記難点を除去する新規なガラスマスクを提供
し、特に半導体基板に設置するオリフラ部の方向とこの
基板に形成するScribing Lineの方向を一
致するように配慮するものである。
The present invention provides a novel glass mask that eliminates the above-mentioned drawbacks, and takes particular care to ensure that the direction of the orientation flat part installed on the semiconductor substrate matches the direction of the scribing line formed on this substrate.

〔発明の構成〕[Structure of the invention]

(問題点を解決するための手段) この目的を達成するのに本発明に係るガラスマスクでは
半導体素子に必要なパターンの他に、半導体基板に形成
するオリフラ部との位置合せを正確に実施できるような
パターンを設置する手段を提供する。。
(Means for solving the problem) In order to achieve this object, the glass mask according to the present invention can accurately align with the orientation flat part formed on the semiconductor substrate in addition to the pattern necessary for the semiconductor element. Provides a means to install such patterns. .

(作 用) これによって被処理半導体基板のオリフラ部の方向とガ
ラスマスクの位置合せが正確に行なえるために、被処理
半導体基板に形成するScribingLineの方向
とオリフラ部の方向を正確に一致させることができるの
で切断面には鋸歯形状が発生しないばかりか、硬くても
ろいGaAs半導体基板でも割れ等の事故が起こらず更
に半導体素子の特性にも影響を与えない効果も発揮でき
る。
(Function) This allows the direction of the orientation flat portion of the semiconductor substrate to be processed to be accurately aligned with the glass mask, so that the direction of the scribing line formed on the semiconductor substrate to be processed and the direction of the orientation flat portion can be accurately matched. As a result, not only a sawtooth shape does not occur on the cut surface, but also accidents such as cracking do not occur even in hard and brittle GaAs semiconductor substrates, and furthermore, the characteristics of the semiconductor element are not affected.

(実施例) 第1図乃至第5図により本発明を詳述する。(Example) The present invention will be explained in detail with reference to FIGS. 1 to 5.

第1図は本発明に関するガラスマスク1の上面図であり
、  Scribing Line用のパターン3・・
・の他にオリフラ部用パターン2を設置し、図中白色部
は光が透過する部分である。次に第2図乃至第5図によ
りガラスマスク1を用いて半導体基板にオリフラ部方向
に合せたScribing Lineを形成する方法を
説明するa GaAs基板5にフォトレジスト層6を被
覆後マスクアライナ−に搬送し、ここに設置するウェー
ハチャックにより半導体基板5に形成したオリフラ部を
検知し更にガラスマスクに対して位置合せを行う。
FIG. 1 is a top view of a glass mask 1 related to the present invention, and includes patterns 3 for scribing lines.
- In addition, a pattern 2 for the orientation flat part is installed, and the white part in the figure is the part through which light passes. Next, a method of forming a scribing line aligned in the direction of the orientation flat part on a semiconductor substrate using the glass mask 1 will be explained with reference to FIGS. 2 to 5. The wafer is transported, and the orientation flat portion formed on the semiconductor substrate 5 is detected by a wafer chuck installed here, and further aligned with the glass mask.

第2図は位置合せ時半導体基板5とガラスマスク1の積
層状態の断面図、第3図はその上面図である。
FIG. 2 is a sectional view of the laminated state of the semiconductor substrate 5 and the glass mask 1 during alignment, and FIG. 3 is a top view thereof.

この時半導体基板5に形成したオリフラ部4とガラスマ
スク1のオリフラ用パターン2の合せが正確に行なわれ
ているか否かを検査し1合せがずれていた場合は再度位
置合せを行う。正確な位置合せを終えてから露光、現像
を実施する。
At this time, it is inspected whether or not the orientation flat portion 4 formed on the semiconductor substrate 5 and the orientation flat pattern 2 of the glass mask 1 are accurately aligned, and if the alignment is deviated, the alignment is performed again. After accurate positioning, exposure and development are performed.

更に前記フォトレジスト層6をマスクとして前記半導体
基板5には食刻工程を施してからこのフォトレジスト層
6を除去して前記Scribing Line用のパタ
ーン3・・・が得られる。(第5図)ところでこの転写
されたScribing Line用のパターン3・・
・の間隔(2aと2bの間隔)は1a11とし。
Further, the semiconductor substrate 5 is subjected to an etching process using the photoresist layer 6 as a mask, and then the photoresist layer 6 is removed to obtain the scribing line pattern 3 . (Fig. 5) By the way, this transferred Scribing Line pattern 3...
The interval between ・ (the interval between 2a and 2b) is 1a11.

前記ガラスマスク1に形成するオリフラ用パターン2の
位置合せ工程で発生する合せずれが±5μm程度の時、
 オリフラ部2との合せずれは3.4秒であった0以上
の工程を終えた半導体基板5はそのへき開方向に沿って
Scribing Lineが形成されるのでダイヤモ
ンド針を利用するScribing工程を実施してもそ
の切断面に鋸歯形状が発生せず、従って半導体素子の特
性にも何等影響を与えずに完成できる。
When the misalignment that occurs in the alignment process of the orientation flat pattern 2 formed on the glass mask 1 is about ±5 μm,
The misalignment with the orientation flat part 2 was 3.4 seconds.0 The semiconductor substrate 5 that has completed the process has a scribing line formed along its cleavage direction, so a scribing process using a diamond needle is performed. However, no sawtooth shape is generated on the cut surface, and therefore the semiconductor device can be completed without affecting its characteristics in any way.

本実施例で使用したガラスマスク1には半導体基板に設
置するオリフラ用パターンとScribingLine
用パターンを同じマスク白パターンているが、夫々別の
マスクに設置しても差支えなく、この場合にはマスク合
せ用パターンは前記オリフラ部用パターンと一諸のマス
クに形成する。
The glass mask 1 used in this example includes an orientation flat pattern and a scribing line to be installed on a semiconductor substrate.
Although the patterns for mask matching are the same mask white pattern, they may be placed on separate masks, and in this case, the pattern for mask matching is formed on the same mask as the pattern for the orientation flat portion.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明に係るガラスマスクは半導体素
子の形成に必要なパターンの他にオリフラ用パターンを
も設け、露光現像工程による半導体基板とガラスマスク
の位置合せ精度を従来のそれより1710程度の数秒に
向上することができた。
As described above, the glass mask according to the present invention is provided with an orientation flat pattern in addition to the patterns necessary for forming semiconductor elements, and the alignment accuracy of the semiconductor substrate and glass mask during the exposure and development process is improved by about 1710 degrees compared to that of the conventional one. I was able to improve it in a few seconds.

従ってScribing工程において半導体基板のへき
開方向に沿って正確にScribingができるので、
その切断面は平坦な形状に形成できるうえにこの半導体
基板に設置する素子特性にも影響を与えずに完了できる
Therefore, in the scribing process, scribing can be performed accurately along the cleavage direction of the semiconductor substrate.
The cut surface can be formed into a flat shape and can be completed without affecting the characteristics of the elements installed on this semiconductor substrate.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係るガラスマスクの上面図、第2図は
このガラスマスクに半導体基板を位置合せした状態を示
す断面図、第3図は同じくこのガラスマスクに半導体基
板を位置合せした状態を示す上面図、第4図は半導体基
板に現像工程を施した様子を示す断面図、第5図は一連
の工程中で半導体基板にエツチングを行ってScrib
ing Lineを形成した状態を示す断面図である。 1・・・ガラスマスク 2・・・オリフラ部用パターン 3−3cribing Line用パターン4・・・オ
リフラ   5・・・半導体基板6・・・フォトレジス
ト 代理人 弁理士  井 上 −男 系  1  図 第2図 第35A 第  4  図 第  5  図
FIG. 1 is a top view of a glass mask according to the present invention, FIG. 2 is a cross-sectional view showing a semiconductor substrate aligned with this glass mask, and FIG. 3 is a top view of a semiconductor substrate aligned with this glass mask. FIG. 4 is a cross-sectional view showing the semiconductor substrate subjected to a development process, and FIG.
FIG. 3 is a cross-sectional view showing a state in which the ing line is formed. 1... Glass mask 2... Orientation flat pattern 3-3 Cribbing line pattern 4... Orientation flat 5... Semiconductor substrate 6... Photoresist agent Patent attorney Inoue - Male lineage 1 Figure 2 Figure 35A Figure 4 Figure 5

Claims (1)

【特許請求の範囲】[Claims]  半導体基板に形成するオリエンテーシヨンフラットと
の位置合せ用パターンを設置することを特徴とするガラ
スマスク。
A glass mask characterized by having a pattern for alignment with an orientation flat formed on a semiconductor substrate.
JP62252526A 1987-10-08 1987-10-08 Glass mask Pending JPH0196655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62252526A JPH0196655A (en) 1987-10-08 1987-10-08 Glass mask

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62252526A JPH0196655A (en) 1987-10-08 1987-10-08 Glass mask

Publications (1)

Publication Number Publication Date
JPH0196655A true JPH0196655A (en) 1989-04-14

Family

ID=17238597

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62252526A Pending JPH0196655A (en) 1987-10-08 1987-10-08 Glass mask

Country Status (1)

Country Link
JP (1) JPH0196655A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007043323A1 (en) * 2005-10-07 2007-04-19 V Technology Co., Ltd. Photomask and exposure method using same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007043323A1 (en) * 2005-10-07 2007-04-19 V Technology Co., Ltd. Photomask and exposure method using same

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