JPS61112322A - Axial aligning method of pattern - Google Patents
Axial aligning method of patternInfo
- Publication number
- JPS61112322A JPS61112322A JP59234551A JP23455184A JPS61112322A JP S61112322 A JPS61112322 A JP S61112322A JP 59234551 A JP59234551 A JP 59234551A JP 23455184 A JP23455184 A JP 23455184A JP S61112322 A JPS61112322 A JP S61112322A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- semiconductor wafer
- axial
- aligning
- photomask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 34
- 239000013078 crystal Substances 0.000 claims description 11
- 238000000206 photolithography Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 7
- 238000003776 cleavage reaction Methods 0.000 abstract 1
- 230000007017 scission Effects 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 18
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明にパターン軸合わせ法に関し、特に半導体装置の
製造工程に於けるホトマスク上のパターンのＸ−Ｙ座標
軸方位と半導体ウェーハの所定の結晶軸方位とのパター
ン軸合わせ法に関する。Detailed Description of the Invention (Industrial Application Field) The present invention relates to a method for aligning pattern axes, and in particular to a method for aligning the X-Y coordinate axes of a pattern on a photomask and a predetermined crystal axis of a semiconductor wafer in the manufacturing process of semiconductor devices. Concerning pattern axis alignment method with orientation.
（従来技術とその問題点）
一般に、半導体装置の製造においては、各製造工程毎の
半導体装置のパターンが光学露光法等により半導体ウェ
ーハ上に形成される。これら各製造工程で用いられるホ
トマスク上のパターンＩｃばＸ−Ｙ座標があり、そのチ
ップ化工程ではこのＸ−Ｙ座標に平行なスクライブ線に
添って半導体ウェーハの切断、チップ化が行なわれる。(Prior Art and its Problems) Generally, in the manufacture of semiconductor devices, a pattern of a semiconductor device for each manufacturing process is formed on a semiconductor wafer by an optical exposure method or the like. A pattern Ic on a photomask used in each of these manufacturing steps has an X-Y coordinate, and in the chip forming process, the semiconductor wafer is cut and chipped along scribe lines parallel to the X-Y coordinate.
このスクライブ線の方位と半導体ウェーハの結晶軸方位
との相対関係Ｖ工、最初の７］Ｅ トＩＪングラフィエ
俣ＶＣ３ｊける半導体装置のパターンと半導体ウェーハ
の軸合わせによって決まる。この半導体ウェーハには通
常結晶軸方位を示すためのオリエンテーション・フラッ
ト（以下ＯＦと略称する）がおるので、従来最初の工程
では目視によりホトマスク上の半導体装置のパターンあ
るいはホトマスクの縁等とＯＦとを軸合わせしていた。The relative relationship between the orientation of the scribe line and the crystal axis orientation of the semiconductor wafer is determined by the axis alignment of the semiconductor device pattern and the semiconductor wafer in the first 7]Et graphitem. This semiconductor wafer usually has an orientation flat (hereinafter abbreviated as OF) to indicate the crystal axis orientation, so conventionally, in the first process, the pattern of the semiconductor device on the photomask or the edge of the photomask, etc. and the OF are visually checked. It was aligned.
しかしながら、こめ様に専用の軸合わせパターンがない
場合、スクライブ線のパターンの方位と半導体ウェーハ
の結晶軸方位とを精度よく合わせることは困難であり、
±３３度程の角度誤差を生じてしまう。このような角度
誤差は最終工程で半導体ウェーハを見開によりチップ化
する場合に重大な間頓を生ずる。即ち％骨間性の結晶軸
方位とスクライプ線のパターンが３度程度ずれた状態で
スクライプ線パターンに添りてスフライプルし、半導体
ウェーハｆｔＪ開すると、チップ周辺に欠けを生じ、チ
ップ歩留りを低下させてしまうという欠点があった。However, if there is no dedicated axis alignment pattern, it is difficult to precisely match the orientation of the scribe line pattern and the crystal axis orientation of the semiconductor wafer.
This results in an angular error of about ±33 degrees. Such an angular error causes a serious interruption when semiconductor wafers are turned into chips by facing each other in the final process. In other words, when the semiconductor wafer is opened by performing a swivel pull along the scribe line pattern with the crystal axis direction of the % interosseous and the scribe line pattern being deviated by about 3 degrees, chipping occurs around the chips, which reduces the chip yield. There was a drawback that
（発明の目的）
本発明の目的は、このような欠点を除去し、半導体ウェ
ーハの結晶軸方位とマスク上のパターンのＸ−Ｙ座標軸
方位を精度よく一致せしめるパターン軸合わせ法を提供
することにある。(Object of the Invention) An object of the present invention is to provide a pattern axis alignment method that eliminates such drawbacks and allows the crystal axis orientation of a semiconductor wafer to accurately match the X-Y coordinate axis orientation of a pattern on a mask. be.
（発明の構成）
本発明の構成は、半導体装置の最初のホトリングラフィ
工程で行なわれるホトマスク上のパターンのＸ−Ｙ座標
軸方位と半導体ウェーハの所定の結晶軸方位とのパター
ン軸合わせ法において、前記ホトマスク上に具備された
パターン軸合わせ用のパターンを用いてこのパターンの
Ｘ−Ｙ座標軸方位と前記半導体ウェーハの所定の結晶軸
方位とを整合せしめることを特徴とする。(Structure of the Invention) The structure of the present invention is a method of aligning the X-Y coordinate axes of a pattern on a photomask with a predetermined crystal axis direction of a semiconductor wafer, which is performed in the first photolithography process of a semiconductor device. The present invention is characterized in that a pattern for pattern axis alignment provided on the photomask is used to align the X-Y coordinate axis direction of this pattern with a predetermined crystal axis direction of the semiconductor wafer.
（実施例） 以下図面を用いて本発明の実施例について説明する。(Example) Embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例を説明するためのホトマスク
の平面図であり、半導体装置の最初の製造工程で用いら
れるホトマスクを示す。図において、１０はマスク基板
、２１はこのマスク基板１０上に形成された半導体装置
のためのパターン、２２はマスク基板１０上に形成され
た軸合わせのためのパターンである。この軸合わせのた
めのパターン２２としては、例えば透明なマスク基板１
０上に幅０．ｌ＋ｍ、長さ４０ｍｍの遮光性のパターン
が０．１１間隔で平行に形成されたものである。
１１、この軸合わせパターン２２と半導体
ウェーハの０Ｆｔｌ−重ね合わせ、半導体ウェーハをホ
トマスクに対して回転して軸合わせを行なうことにより
、例えば１００倍の倍率の拡大Ｋｔｆ用いると、±００
１度以内の角度謬差で軸合わせをすることができた。FIG. 1 is a plan view of a photomask for explaining one embodiment of the present invention, and shows a photomask used in the first manufacturing process of a semiconductor device. In the figure, 10 is a mask substrate, 21 is a pattern for a semiconductor device formed on this mask substrate 10, and 22 is a pattern for axis alignment formed on the mask substrate 10. As the pattern 22 for this axis alignment, for example, a transparent mask substrate 1
Width 0 on 0. Light-shielding patterns with a length of 1+m and a length of 40 mm are formed in parallel at intervals of 0.11.
11. By superimposing the axis alignment pattern 22 and the semiconductor wafer at 0Ftl and aligning the axis by rotating the semiconductor wafer with respect to the photomask, for example, if magnification Ktf of 100 times is used, ±00
It was possible to align the axes with an angle error of less than 1 degree.
例えば、半導体ウェーハが（１００）ｆｔ主面とするＧ
ａＡｓであり、ＯＦ、が（１１０）面の場合、本発明［
よるパターン軸合わせ方法により、見開によるチップ化
工程におけるチップ周辺の欠けのｒＡ頂が解決さ机、チ
ップ歩留シが著しく向上した。For example, if a semiconductor wafer has a (100) ft principal surface,
aAs, and when OF is a (110) plane, the present invention [
By using the pattern axis alignment method described above, the rA peak of chipping around the chip in the spread-based chip production process was solved, and the chip yield was significantly improved.
（発明の効果）
以上説明した如く、本発明によれば、半導体ウェーハの
所定の結晶軸方位とホトマスク上のパターンのＸ−Ｙ座
標軸方位とを極めて正確に軸合わせすることが可能とな
り、臂開によるチップ化工程におけるチップ歩留りを向
上せしめることができる。(Effects of the Invention) As explained above, according to the present invention, it is possible to extremely accurately align a predetermined crystal axis direction of a semiconductor wafer with the X-Y coordinate axis direction of a pattern on a photomask. It is possible to improve the chip yield in the chip forming process.
尚５本実施例においては軸合わせの対象が半導体ウェー
ハのＯＦの場合について述べたが、予めウェーハの一部
を臂開して形成した併開面を軸合わせの対象としてもよ
い。In this embodiment, the case where the object of axis alignment is the OF of a semiconductor wafer has been described, but the object of axis alignment may be a parallel open plane formed by opening a part of the wafer in advance.
第１図は本発明の詳細な説明するためのホトマスクの平
面図である。図において、１０はホトマスク基板、２１
は半導体装置のパターン、２２は軸合わせパターンをそ
れぞれ示す。FIG. 1 is a plan view of a photomask for explaining the present invention in detail. In the figure, 10 is a photomask substrate, 21
2 shows a pattern of a semiconductor device, and 22 shows an axis alignment pattern.
Claims (1)
るホトマスク上のパターンのＸ−Ｙ座標軸方位と半導体
ウェーハの所定の結晶軸方位とのパターン軸合わせ法に
おいて、前記ホトマスク上に具備されたパターン軸合わ
せ用のパターンを用いてこのパターンのＸ−Ｙ座標軸方
位と前記半導体ウェーハの所定の結晶軸方位とを整合せ
しめることを特徴とするパターン軸合わせ法。In a pattern alignment method for aligning the X-Y coordinate axis direction of a pattern on a photomask with a predetermined crystal axis direction of a semiconductor wafer, which is performed in the first photolithography process of a semiconductor device, a pattern alignment device provided on the photomask is used. A pattern axis alignment method characterized in that the X-Y coordinate axis direction of the pattern is aligned with a predetermined crystal axis direction of the semiconductor wafer using a pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59234551A JPS61112322A (en) | 1984-11-07 | 1984-11-07 | Axial aligning method of pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59234551A JPS61112322A (en) | 1984-11-07 | 1984-11-07 | Axial aligning method of pattern |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61112322A true JPS61112322A (en) | 1986-05-30 |
Family
ID=16972792
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59234551A Pending JPS61112322A (en) | 1984-11-07 | 1984-11-07 | Axial aligning method of pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61112322A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7148529B2 (en) * | 2001-03-30 | 2006-12-12 | Kabushiki Kaisha Toshiba | Semiconductor package |
-
1984
- 1984-11-07 JP JP59234551A patent/JPS61112322A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7148529B2 (en) * | 2001-03-30 | 2006-12-12 | Kabushiki Kaisha Toshiba | Semiconductor package |
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