JPH0194677A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0194677A JPH0194677A JP62251801A JP25180187A JPH0194677A JP H0194677 A JPH0194677 A JP H0194677A JP 62251801 A JP62251801 A JP 62251801A JP 25180187 A JP25180187 A JP 25180187A JP H0194677 A JPH0194677 A JP H0194677A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductors
- layer
- semiconductor
- gaas
- types
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 88
- 239000000872 buffer Substances 0.000 claims abstract description 30
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 21
- 150000001875 compounds Chemical class 0.000 claims description 4
- 230000006866 deterioration Effects 0.000 abstract 1
- 239000013078 crystal Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Photovoltaic Devices (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
Description
【発明の詳細な説明】
技術分野
本発明は、格子不整合を緩和するためのバッファ層を挟
んで２種類の半導体が積層されているとともに、それ等
の半導体間で電流が流れるようにして使用される半導体
素子の改良に関するものである。[Detailed Description of the Invention] Technical Field The present invention is a semiconductor device in which two types of semiconductors are stacked with a buffer layer sandwiched between them to alleviate lattice mismatch, and a current is allowed to flow between the semiconductors. This invention relates to improvements in semiconductor devices.
従来技術
バンドギャップが異なる２種類の半導体を積層するに際
して、それ等の半導体間に、格子不整合を緩和するため
のバッファ層を介在させるようにしたものがある。例え
ば、Ｓｉ基板上にＧａＡｓ半導体を結晶成長させる際に
は、それ等の間には約４％の格子不整合が存在するため
、ＧａＡｓを結晶成長させるのに先立って、ＧａＰ層と
ＧａＰ “／ＧａＡｓ＋−ｘ ＰＸ （０〈Ｘ＜
１）歪超格子層とＧａＡＳ＋−ｘ ＰＸ （０＜ｘ＜
１）／ＧａＡｓ歪超格子層とから成るバッファ層をＳｉ
基板上に形成し、その上にＧａＡｓを結晶成長させるよ
うにしたものがある。BACKGROUND ART When two types of semiconductors having different band gaps are stacked, a buffer layer is interposed between the two semiconductors to alleviate lattice mismatch. For example, when growing a GaAs semiconductor crystal on a Si substrate, there is a lattice mismatch of about 4% between them. GaAs+-x PX (0<X<
1) Strained superlattice layer and GaAS+-x PX (0<x<
1) A buffer layer consisting of a strained superlattice layer of Si/GaAs
There is one that is formed on a substrate and on which GaAs crystals are grown.
発明が解決しようとする問題点
ところで、このようなバッファ層を有する半導体素子の
うちには、例えば２種類の半導体太陽電池をバッファ層
を介して積層したタンデム型太陽電池のように、２種類
の半導体間で電流が流れるようにして使用されるものが
あるが、従来は、バッファ層をそのまま電流導通部とし
て利用していたため、その電気抵抗により半導体素子と
しての性能が損なわれるという問題があった。Problems to be Solved by the Invention By the way, among semiconductor devices having such a buffer layer, there are two types of semiconductor devices, such as a tandem solar cell in which two types of semiconductor solar cells are stacked with a buffer layer interposed in between. Some semiconductors are used to allow current to flow between them, but in the past, the buffer layer was used as it is as a current conducting part, which caused the problem that its electrical resistance impairs the performance of the semiconductor element. .
問題点を解決するための手段
本発明は以上の事情を背景として為されたものであり、
その目的は、バッファ層の存在に起因する電気的な性能
低下を防止することである。Means for Solving the Problems The present invention has been made against the background of the above circumstances.
The purpose is to prevent electrical performance degradation due to the presence of the buffer layer.
そして、かかる目的を達成するため、本発明は、バンド
ギャップが異なる２種類の半導体が、格子不整合を緩和
するためのバッファ層を挟んで積層されているとともに
、それ等２種類の半導体間で電流が流れるようにして使
用される半導体素子において、前記２種類の半導体を短
絡する短絡電極を設けたことを特徴とする。In order to achieve this object, the present invention has two types of semiconductors with different band gaps stacked with a buffer layer sandwiched therebetween to alleviate lattice mismatch, and a A semiconductor element used to allow current to flow is characterized in that a short-circuiting electrode is provided to short-circuit the two types of semiconductors.
作用および発明の効果
このようにすれば、２種類の半導体が短絡電極によって
結ばれるため、電気的にはバッファ層が存在しないのと
同じになり、半導体素子としての電気的な性能が向上す
る。Operation and Effects of the Invention In this way, since two types of semiconductors are connected by the short-circuit electrode, it is electrically the same as if no buffer layer existed, and the electrical performance as a semiconductor element is improved.
実施例
以下、本発明の一実施例を図面に基づいて詳細に説明す
る。EXAMPLE Hereinafter, an example of the present invention will be described in detail based on the drawings.
図は、本発明の一実施例である半導体素子としてのタン
デム型太陽電池１０の構造図である。このタンデム型太
陽電池１０は、バンドギャップが異なる２種類の半導体
太陽電池１２および１４を直列に備えており、単一バン
ドギャップの太陽電池に比較して優れたエネルギー変換
効率が得られるようになっている。一方の半導体太陽電
池１２はｎ−３ｉｉｉとＰ” −３ｉ層とによってｐｎ
接合が形成されており、他方の半導体太陽電池１４はｎ
−ＧａＡｓ層とｐ” −ＧａＡｓ層とによってｐｎ接合
が形成されているが、それ等の間には、格子不整合を緩
和するためのバッファ層１６が設けられている。The figure is a structural diagram of a tandem solar cell 10 as a semiconductor element, which is an embodiment of the present invention. This tandem solar cell 10 is equipped with two types of semiconductor solar cells 12 and 14 having different band gaps in series, and can obtain superior energy conversion efficiency compared to a single band gap solar cell. ing. One semiconductor solar cell 12 has pn
A junction is formed, and the other semiconductor solar cell 14 is n
A pn junction is formed by the -GaAs layer and the p''-GaAs layer, and a buffer layer 16 is provided between them to alleviate lattice mismatch.
これは、Ｓｉ半導体の格子定数は５．４３１人であるの
に対し、ＧａＡｓの格子定数は５．６５３人であるため
、それ等の間には約４％の格子不整合が存在し、半導体
太陽電池１２の上に半導体太陽電池１４を直接エピタキ
シャル成長させると、格子欠陥等を生じて結晶性が損な
われるからである。前記バッファ層１６は、歪超格子を
含んでＳｉ半導体とＧａＡｓとの格子不整合を緩和する
もので、前記半導体太陽電池１２のｐ“−３ｉ層上に、
ＧａＰ層、ＧａＰ／ＧａＡｓ＋−ｘＰｘ（０＜ｘ＜１）
歪超格子層、およびＧａＡＳ＋−ｘＰｘ （０＜ｘ＜
１）／ Ｇ ａ Ａ ｓ歪超格子層を順次エピタキシャ
ル成長させたものである。半導体太陽電池１２および１
４は、かかるバッファ層１６を挟んで直列に接続されて
いる。This is because the lattice constant of Si semiconductor is 5.431, while the lattice constant of GaAs is 5.653, so there is a 4% lattice mismatch between them, and the semiconductor This is because if the semiconductor solar cell 14 is directly epitaxially grown on the solar cell 12, lattice defects and the like will occur and the crystallinity will be impaired. The buffer layer 16 includes a strained superlattice to alleviate lattice mismatch between the Si semiconductor and GaAs, and is formed on the p"-3i layer of the semiconductor solar cell 12.
GaP layer, GaP/GaAs+-xPx (0<x<1)
strained superlattice layer, and GaAS+−xPx (0<x<
1)/GaAs strained superlattice layers are epitaxially grown in sequence. Semiconductor solar cells 12 and 1
4 are connected in series with the buffer layer 16 in between.
上記半導体太陽電池１４のｐ” −ＧａＡｓ層の上には
、ｐ” Ａｊ２ｏ、ｓ Ｇａｏ、ｚ Ａｓから成る半
導体層１８がエピタキシャル成長させられており、その
半導体Ｊｉｉ１８の上には更に５ｉＮＸの反射防止膜２
０が設けられている。そして、半導体太陽電池１２のｎ
−３ｉ層にＡｇ製の電極２２が取り付けられるとともに
、上記半導体層１８にＡｕ−Ｚｎ製の電極２４が取り付
けられることにより、これ等の電極２２．２４間に、バ
ッファ層１６を挟んで直列に接続された半導体太陽電池
１２，１４による出力が取り出される。On the p''-GaAs layer of the semiconductor solar cell 14, a semiconductor layer 18 made of p'' Aj2o, s Gao, z As is epitaxially grown, and an antireflection film of 5iNX is further formed on the semiconductor Jii 18. 2
0 is set. Then, n of the semiconductor solar cell 12
An electrode 22 made of Ag is attached to the -3i layer, and an electrode 24 made of Au-Zn is attached to the semiconductor layer 18, so that these electrodes 22 and 24 are connected in series with the buffer layer 16 in between. The output from the connected semiconductor solar cells 12 and 14 is taken out.
なお、上記バッファ層１６．半導体太陽電池１４．およ
び半導体層１８は、例えば有機金属化学気相成長（ＭＯ
ＣＶＤＨＭｅｔａｌ Ｏｒｇａｎｉｃ Ｃｈｅｍｉｃａ
ｌ ＶａｐｏｒＤｅｐｏｓｉｔｉｏｎ）法や分子線エピ
タキシー（ＭＢＥＨＭｏｌｅｃｕｔｅｒ Ｂｅａｍ ｔ
ｉｐｉｔａｘｙ）法等によるエピタキシャル成長装置に
よって形成される。Note that the buffer layer 16. Semiconductor solar cell 14. And the semiconductor layer 18 is formed by, for example, metal organic chemical vapor deposition (MO).
CVDHMetal Organic Chemica
l Vapor Deposition) method and molecular beam epitaxy (MBEHMolecutter Beam t).
It is formed using an epitaxial growth apparatus using the ipitaxy method or the like.
一方、かかる本実施例のタンデム型太陽電池１０の上面
には、底部が半導体太陽電池１２のｐ゛−３ｉ層に達す
る断面四角形の溝２６が縦横に複数（図では１つの横断
面のみが示されている）形成されているとともに、その
溝２６の開口部には、それぞれその：ａ２６よりも幅寸
法が大きく且つ底部が半導体太陽電池１４のｎ−ＧａＡ
ｓＪｉに達する溝２８が形成されている。これ等の溝２
６，２８は、例えばエツチング等によって半４体の一部
を除去したり、前記結晶成長させる際にマスキング等を
行ったりすることにより、形成することができる。そし
て、上記溝２６の内壁面および溝２８の底面には、Ａｕ
製の短絡電極３０が真空蒸着等によって設けられ、半導
体太陽電池１２のｐ゛−３ｉ層と半導体太陽電池１４の
ｎ−ＧａＡｓ層とが短絡されている。On the other hand, on the upper surface of the tandem solar cell 10 of this embodiment, there are a plurality of grooves 26 having a rectangular cross section, the bottom of which reaches the p-3i layer of the semiconductor solar cell 12 (only one cross section is shown in the figure). ), and the opening of the groove 26 has a width larger than that of the groove 26 and a bottom portion of the n-GaA of the semiconductor solar cell 14.
A groove 28 reaching sJi is formed. These grooves 2
6 and 28 can be formed, for example, by removing a part of the half body by etching or the like, or by performing masking or the like during the crystal growth. The inner wall surface of the groove 26 and the bottom surface of the groove 28 are coated with Au.
A short-circuiting electrode 30 made of a semiconductor material is provided by vacuum evaporation or the like, and the p-3i layer of the semiconductor solar cell 12 and the n-GaAs layer of the semiconductor solar cell 14 are short-circuited.
したがって、かかる本実施例のタンデム型太陽電池１０
においては、２種類の半導体太陽電池１２と１４とが短
絡電極３０を介して直列に接続されることとなり、バッ
ファ層１６の電気抵抗による影響がなくなって、太陽電
池としての電気的性能が向上する。Therefore, the tandem solar cell 10 of this embodiment
In this case, the two types of semiconductor solar cells 12 and 14 are connected in series via the shorting electrode 30, and the influence of the electrical resistance of the buffer layer 16 is eliminated, improving the electrical performance of the solar cell. .
また、本実施例では、短絡電極３０を設けるためにタン
デム型太陽電池ＩＯの表面に複数の溝２６が縦横に形成
され、それ等の溝２６によって上部側の半導体太陽電池
１４が分断されているため、その半導体太陽電池１４と
下部の半導体太陽電池１２との熱膨張係数の相違に起因
する変形や歪の発生が軽減され、太陽電池としての特性
や寿命が向上する。In addition, in this embodiment, a plurality of grooves 26 are formed vertically and horizontally on the surface of the tandem solar cell IO in order to provide the shorting electrode 30, and the semiconductor solar cell 14 on the upper side is divided by these grooves 26. Therefore, the occurrence of deformation and distortion due to the difference in thermal expansion coefficient between the semiconductor solar cell 14 and the lower semiconductor solar cell 12 is reduced, and the characteristics and life of the solar cell are improved.
因に、上記実施例における溝２６の幅寸法を５０ｐｍｓ
溝２８が溝２６から両側へはみ出す部分の幅寸法をそれ
ぞれ３０ｐとして短絡電極３０を設けたタンデム型太陽
電池１０と、かかる溝２６゜２８および短絡電極３０が
設けられていないこと以外は全く同じ構造の従来のタン
デム型太陽電池とを用いて、そのフィルファクター（Ｆ
Ｆ）を求めるとともに、前記半導体の熱膨張係数差によ
って生じる変形や歪を反りの曲率半径として測定したと
ころ、第１表に示す結果が得られた。Incidentally, the width dimension of the groove 26 in the above embodiment is 50 pms.
A tandem solar cell 10 in which a shorting electrode 30 is provided with the width of the portion where the groove 28 protrudes from the groove 26 on both sides is 30p, and the structure is exactly the same except that the groove 26° 28 and the shorting electrode 30 are not provided. The fill factor (F
F) was determined, and the deformation and strain caused by the difference in the thermal expansion coefficients of the semiconductors were measured as the radius of curvature of warp, and the results shown in Table 1 were obtained.
第１表
ここで、上記フィルファクター（Ｆ Ｆ）は次式（１）
で表され、光照射時に最大出力が得られる時の電流、電
圧をそれぞれＩ ｍ＋ａｘ ＋ Ｖ＋＋＋ａｘとした
時、それ等の積を開放電圧Ｖ０゜と短絡電流Ｉｓｃとの
積で割算したもので、その値が１に近い程太陽電池とし
ての性能は優れているのであり、本発明品の方が従来品
をかなり上回っている。また、変形や歪についても、本
発明品は殆ど変形していないことが判る。Table 1: Here, the above fill factor (F F) is expressed by the following formula (1)
When the current and voltage when the maximum output is obtained during light irradiation are respectively I m + ax + V + + + ax, the product of these is divided by the product of the open circuit voltage V0° and the short circuit current Isc, The closer the value is to 1, the better the performance as a solar cell, and the product of the present invention considerably outperforms the conventional product. Furthermore, it can be seen that the product of the present invention is hardly deformed or distorted.
以上、本発明の一実施例を図面に基づいて詳細に説明し
たが、本発明は他の態様で実施することもできる。Although one embodiment of the present invention has been described above in detail based on the drawings, the present invention can also be implemented in other embodiments.
例えば、前記実施例では本発明がタンデム型太陽電池１
０に適用された場合について説明したが、半導体太陽電
池１２の部分が単なるｎ型またはｐ型のＳｉ半導体のみ
から成るＳｔ基板で構成されている太陽電池や、格子不
整合を緩和するためのバッファ層を有するとともにその
バッファ層を介して電流が流される他の半導体素子にも
本発明は同様に適用され得る。For example, in the above embodiment, the present invention is applied to the tandem solar cell 1
Although the case where the semiconductor solar cell 12 is applied to a solar cell made of a St substrate consisting of only an n-type or p-type Si semiconductor, or a buffer for mitigating lattice mismatch has been described, The present invention can be similarly applied to other semiconductor devices having a buffer layer and through which current flows.
また、前記実施例のバッファ層１６はＧａＰ層とＧａＰ
／ＧａＡｓ＋−ｘＰｘ （０＜ｘ＜１）歪超格子層とＧ
ａ Ａ ｓ ＋ −ｘ Ｐ ｘ （０＜ ｘ ＜ １
） ／ Ｇ ａ Ａ ｓ歪超格子層とから構成されて
いるが、これは、その格子不整合を緩和すべき上下に位
置する２種類の半導体の組成や格子定数等に応じて適宜
定められるものである。なお、前記タンデム型太陽電池
１０のバッファ層１６についても、Ｇｅや多結晶ＧａＡ
ｓを利用したものなど、当業者の知識に基づいて適宜変
更することが可能である。Further, the buffer layer 16 of the above embodiment is a GaP layer and a GaP layer.
/GaAs+-xPx (0<x<1) strained superlattice layer and G
a As + −x P x (0< x < 1
) / Ga As strained superlattice layer, which is determined as appropriate depending on the composition and lattice constant of the two types of semiconductors located above and below whose lattice mismatch is to be alleviated. It is. Note that the buffer layer 16 of the tandem solar cell 10 is also made of Ge or polycrystalline GaA.
It is possible to make appropriate changes based on the knowledge of those skilled in the art, such as using s.
また、前記実施例ではＳｉ半導体から成る半導体太陽電
池１２およびＧａＡｓ半導体から成る半導体太陽電池１
４によってタンデム型太陽電池１０が構成されているが
、他の半導体、例えばＧａＡｓ以外のｍ−ｖ族化合物半
導体、更にはｍ−ｖ族化合物半導体以外の半導体を備え
た太陽電池等にも本発明は適用され得る。Further, in the above embodiment, a semiconductor solar cell 12 made of a Si semiconductor and a semiconductor solar cell 1 made of a GaAs semiconductor.
4 constitutes the tandem solar cell 10, but the present invention can also be applied to other semiconductors, such as m-v group compound semiconductors other than GaAs, and solar cells equipped with semiconductors other than m-v group compound semiconductors. may be applied.
また、前記実施例では縦横に複数の溝２６．２８を形成
して短絡電極３０が設けられているが、表面から半導体
太陽電池１２のｐ” −３ｉ層に達する複数の穴を形成
して、その中に、そのｐ”−３ｉ層と半導体太陽電池１
４のｎ−ＧａＡｓ層とを短絡する短絡電極をそれぞれ設
けるようにしても差支えない。なお、短絡電極３０の材
質については、その電気伝導性がバッファ層よりも優れ
たものであれば、本発明の効果が得られるのであり、短
絡の仕方については、例えば前記溝２６内を短絡すべき
材料で埋設してしまうなど、種々の手法を採用できる。Further, in the above embodiment, the shorting electrode 30 is provided by forming a plurality of grooves 26 and 28 in the vertical and horizontal directions, but a plurality of holes reaching the p''-3i layer of the semiconductor solar cell 12 from the surface are formed. Therein, the p''-3i layer and the semiconductor solar cell 1
It is also possible to provide short-circuiting electrodes for short-circuiting the n-GaAs layers of No. 4 and 4, respectively. As for the material of the short-circuiting electrode 30, the effect of the present invention can be obtained as long as its electrical conductivity is superior to that of the buffer layer. Various methods can be used, such as burying it in suitable material.
また、前記実施例の溝２６．２８は横断面が四角形であ
るが、その形状をＶ字形など他の種々の形に変更できる
ことは勿論である。Further, although the grooves 26 and 28 in the above embodiment have a rectangular cross section, it is of course possible to change the shape to various other shapes such as a V-shape.
また、前記実施例では２種類の半導体太陽電池１２およ
び１４を備えているが、３種類以上の半導体太陽電池を
それぞれバッファ層を介して積層するとともに、それ等
のバッファ層をそれぞれ短絡電極によって短絡するよう
に構成することも可能である。太陽電池以外の半導体素
子についても同様である。In addition, although the above embodiment includes two types of semiconductor solar cells 12 and 14, three or more types of semiconductor solar cells are stacked via buffer layers, and the buffer layers are short-circuited by short-circuit electrodes. It is also possible to configure it to do so. The same applies to semiconductor devices other than solar cells.
その他−々例示はしないが、本発明は当業者の知識に基
づいて種々の変更、改良を加えた態様で実施することが
できる。Although other examples are not provided, the present invention can be implemented with various modifications and improvements based on the knowledge of those skilled in the art.
図は本発明の一実施例であるタンデム型太陽電池の一例
を説明する構造図である。The figure is a structural diagram illustrating an example of a tandem solar cell that is an embodiment of the present invention.
Claims (6)
不整合を緩和するためのバッファ層を挟んで積層されて
いるとともに、該２種類の半導体間で電流が流れるよう
にして使用される半導体素子において、 前記２種類の半導体を短絡する短絡電極を設けたことを
特徴とする半導体素子。(1) A semiconductor device in which two types of semiconductors with different band gaps are stacked with a buffer layer sandwiched between them to alleviate lattice mismatch, and a current is allowed to flow between the two types of semiconductors. A semiconductor device according to the present invention, further comprising a short-circuiting electrode that short-circuits the two types of semiconductors.
とが接合されて成るｐｎ接合を有する太陽電池であり、
前記短絡電極は該太陽電池を直列に接続するものである
特許請求の範囲第１項に記載の半導体素子。(2) The two types of semiconductors are solar cells each having a pn junction formed by joining a p-type layer and an n-type layer,
2. The semiconductor device according to claim 1, wherein the shorting electrode connects the solar cells in series.
半導体上に前記バッファ層を介してエピタキシャル成長
させられたIII−Ｖ族化合物半導体である特許請求の範
囲第１項または第２項に記載の半導体素子。(3) The two types of semiconductors are a Si semiconductor and a Si semiconductor.
3. The semiconductor device according to claim 1, which is a III-V compound semiconductor epitaxially grown on a semiconductor via the buffer layer.
請求の範囲第３項に記載の半導体素子。(4) The semiconductor device according to claim 3, wherein the buffer layer includes a strained superlattice.
前記バッファ層はＧａＰ層とＧａＰ／ＧａＡｓ＿１＿−
＿ｘＰ＿ｘ（０＜ｘ＜１）歪超格子層とＧａＡｓ＿１＿
−＿ｘＰ＿ｘ（０＜ｘ＜１）／ＧａＡｓ歪超格子層とか
ら成るものである特許請求の範囲第４項に記載の半導体
素子。(5) the III-V compound semiconductor is GaAs;
The buffer layer is a GaP layer and GaP/GaAs_1_-
_xP_x (0<x<1) strained superlattice layer and GaAs_1_
-_xP_x (0<x<1)/GaAs strained superlattice layer.
他方に達するように形成された溝の内壁に設けられてい
るものである特許請求の範囲第１項乃至第５項の何れか
に記載の半導体素子。(6) The short-circuiting electrode is provided on the inner wall of a groove formed to reach from one of the two types of semiconductors to the other. The semiconductor device described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62251801A JPH0194677A (en) | 1987-10-06 | 1987-10-06 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62251801A JPH0194677A (en) | 1987-10-06 | 1987-10-06 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0194677A true JPH0194677A (en) | 1989-04-13 |
Family
ID=17228128
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62251801A Pending JPH0194677A (en) | 1987-10-06 | 1987-10-06 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0194677A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008124381A (en) * | 2006-11-15 | 2008-05-29 | Sharp Corp | Solar battery |
| WO2010140371A1 (en) * | 2009-06-05 | 2010-12-09 | 住友化学株式会社 | Semiconductor substrate, photoelectric conversion device, method for manufacturing semiconductor substrate, and method for manufacturing photoelectric conversion device |
| WO2012127545A1 (en) * | 2011-03-24 | 2012-09-27 | パナソニック株式会社 | Method for generating electricity using solar cell |
| US10741714B2 (en) | 2018-07-05 | 2020-08-11 | Fujitsu Limited | Infrared detection device, infrared detection apparatus, and manufacturing method of infrared detection device |
-
1987
- 1987-10-06 JP JP62251801A patent/JPH0194677A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008124381A (en) * | 2006-11-15 | 2008-05-29 | Sharp Corp | Solar battery |
| WO2010140371A1 (en) * | 2009-06-05 | 2010-12-09 | 住友化学株式会社 | Semiconductor substrate, photoelectric conversion device, method for manufacturing semiconductor substrate, and method for manufacturing photoelectric conversion device |
| US8835980B2 (en) | 2009-06-05 | 2014-09-16 | National Institute Of Advanced Industrial Science And Technology | Semiconductor wafer, photoelectric conversion device, method of producing semiconductor wafer, and method of producing photoelectric conversion device |
| WO2012127545A1 (en) * | 2011-03-24 | 2012-09-27 | パナソニック株式会社 | Method for generating electricity using solar cell |
| JP5158291B2 (en) * | 2011-03-24 | 2013-03-06 | パナソニック株式会社 | Method for generating power using solar cells |
| US8604338B2 (en) | 2011-03-24 | 2013-12-10 | Panasonic Corporation | Solar cell |
| US10741714B2 (en) | 2018-07-05 | 2020-08-11 | Fujitsu Limited | Infrared detection device, infrared detection apparatus, and manufacturing method of infrared detection device |
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