JPH0194671A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide both VDMOS and other semiconductor elements with optimal characteristics, respectively and to provide Zener diodes with excellent reproducibility of Zener characteristics by monolithically forming both heavily doped substrate and lightly doped substrate by a direct bonding or like means to accurately control the thickness difference in both lightly doped regions in a first region and a second region. CONSTITUTION:A semiconductor device comprises a first conductivity type heavily doped substrate 1; a first conductive type lightly doped region 2 arranged thereupon by direct bonding; a vertical MOSFET 10 in which a first region in the lightly doped region 2 is formed to be a drain region, a first conductive type source region 6 being arranged in a second conductive channel region 5 arranged in such drain region, a gate electrode 8 being arranged on such channel region 5 while interposing a gate insulating film 7; a first conductive type heavily doped Zener region 3 in which a Zener diode 4 serving to determine a drain breakdown strength for the vertical MOSFET 10 is so arranged that it is in contact with the substrate 1 in the first region of the lightly doped region 2 and is bonded to the channel region 5 and which is formed by such junction; other semiconductor elements 20, 30 which consist of peripheral circuits, etc. of the vertical MOSFET 10 arranged in the second region of the lightly doped region 2.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) This invention relates to a vertical MOSFET (hereinafter referred to as VDM) for power use.
The present invention relates to a semiconductor device in which a semiconductor device (referred to as O8) and other semiconductor elements constituting a peripheral circuit such as OMO8 are integrated on one chip.

(Prior art) In recent years, VDMO3 for power, which is used as a switching element for various in-vehicle power loads, and its peripheral circuits,
A semiconductor device (hereinafter also referred to as a power IC) in which other semiconductor elements constituting the MO8 and the like are integrated on one chip has been proposed.

The above-mentioned on-vehicle power loads are often inductive loads such as motors and solenoids, and these power loads generate high voltage surges when the load current is interrupted. This high voltage surge is applied between the drain and source of the switching element VDMO8, so the VDM used for this
O8 is required to have high resistance to high voltage surges. On the other hand, the VDMO 3 is required to have a low on-resistance during operation so that it can draw sufficient current for a low output voltage power source such as a vehicle battery.

Now, such a conventional semiconductor device will be explained using FIG. 3, starting with an example of a VDMO 8 used therein. In the figure, 31 is a highly doped n+ substrate, and a lightly doped n- region 32 is formed on the n1 substrate 31 by an epitaxial method. The n-region 32 essentially acts as a drain, and is formed to have a relatively thin thickness for the purpose of lowering the on-resistance.
It is said to be on the order of μm. In the required part of the n-region 32, n
A p-type channel region 5 is formed that reaches the + substrate 31, and a pn junction between the p-type channel region 5 and the n+ substrate 31 forms a Zener diode 33 for regulating drain breakdown voltage. The Zener voltage of the Zener diode 33 is VD
It is set lower than the drain-source breakdown voltage of MO8 by a required value.

An n+ source region 6 is formed in the p-type channel region 5, and a surface layer of the p-type channel region 5 is formed on the p-type channel region 5 between the n+ source region 6 and the n- region [32]. A gate electrode 8 for inducing a channel 5a is provided with a gate insulating film 7 interposed therebetween. 9 is an intermediate insulating film, 11 is a source electrode, and the source electrode 11 is n+
It is connected to source region 6 and to p-type channel region 5 via p + channel contact region 12 . Reference numeral 13 denotes a drain electrode, which is provided on the back surface of the n4' substrate 31.

In addition, in the VDMO8 with a built-in Zener diode, high voltage surges from the load etc. are absorbed by the Zener diode 33, so the element itself can have a structure that can withstand the power supply voltage, and has a high surge withstand capacity. The on-resistance is sufficiently low.

VDM with built-in Zener diode has these advantages.
If O8 and its peripheral circuits such as drive circuits and control circuits are integrated on a single chip as a power IC, device size can be reduced, mounting costs can be reduced, and intermediate wiring can be omitted to reduce costs and improve performance. Many benefits can be expected, such as the realization of new functions, and the range of applications is thought to be wide.

Figure 4 shows such a VDMO with a built-in Zener diode.
8 and other semiconductor elements constituting its peripheral circuit are integrated on one chip.

In addition, in FIG. 4, regarding the VDMO810, the third
Since the structure is almost the same as that shown in the figure, in FIG. 4, the same or equivalent members or parts, etc. in FIG.

In FIG. 4, 34 is an n+ substrate, and an n- region 35 of a required thickness is formed on the n1 substrate 34 by an epitaxial method. A high concentration n+ buried layer 36 is formed between the n- region 35 and the n4'' substrate 34 in the first region where the VDMO 310 is formed. In the area 35, only the first area is
As mentioned above, it is formed thin for the purpose of lowering the on-resistance. The p-type channel region 5 is formed to reach this n4' buried layer 36, and the pn junction between the p-type channel region 5 and the n+ buried layer 36 forms a Zener diode 33 for regulating drain breakdown voltage. There is.

Formation of the n+ buried layer 36 and control of the thickness of the n- region 35 in the first region are performed as follows. That is, as the n-carvings of the n'' substrate 34, for example, antimony (Sb), which has a small diffusion constant, is used.
The buried layer 36 is made of, for example, phosphorus (P), which has a large diffusion constant.
A large amount of phosphorus (P) impurity is doped. mote n
After the n- region 35 is epitaxially grown on the + substrate 34 to a required thickness, the required heat treatment is applied to form phosphorus (
P) The impurity is largely re-diffused into the n- region 35 from the antimony (Sb) impurity which is the dopant of the n1 substrate 34, forming the n: buried layer 36, and the n- region 35 in the first region. The thickness is controlled to be as thin as required.

On the other hand, the n-region 35 on the side of the VDMO 310 is used as a second region, and in this second region, the p-channel MOSFET (hereinafter referred to as DMO 8) 20 and nMo 830 that constitute the 0MO8, which is the peripheral circuit of the VDMO 810, are installed. It is formed as follows.

That is, the p+ source region 14 and p+ drain region 15 formed on the surface side of the n- region 35, and the gate oxide film 16
The gate electrode 17, source electrode 18, drain electrode 19°, etc. formed above constitute an 0MO820. Further, a p-well 21 is formed on the surface side of the n- region 35, and an n+ source region 22 formed in this p-well 21
The nMo 830 is composed of the n1 drain region 23, the gate electrode 25 formed on the gate oxide film 24, the source electrode 26, the drain electrode 27, and the like.

The n-region 35 in the second region is kept as thick as it was during epitaxial growth, so that the n-region 35 has a thickness of 0MO82
The breakdown voltage characteristics of nMo830 and nMo830 are improved.

In this way, VDMO810 with high surge withstand capability and low on-resistance, and 0M with improved withstand voltage characteristics.
O820 and nMo830 are integrated on one chip.

Then, the potential of the n- region 35 is fixed to the power supply voltage applied from the drain electrode 13, and VDM○810 and nMo
820 and 0MO8 consisting of nMo830 are electrically separated, and VDMO 810 is driven by a peripheral circuit composed of 0MO8 and the like to perform switching operations and the like.

(Problems to be Solved by the Invention) In a conventional semiconductor device, a large amount of phosphorus (P), which has a large diffusion constant, is preliminarily placed in the required portions of the N1 substrate 34 doped with antimony (Sb), which has a small diffusion constant. After epitaxially growing the n- region 35, heat treatment is applied to form an n- region of phosphorus (P) and antimony (Sb).
Since the difference in the degree of re-diffusion into the region 35 was used to create a difference in thickness between the n-region 35 in the first region and the n-region 35 in the second region, Antimony (Sb) is re-diffused from the n+ substrate 34 into the n- region 35 in the second region, and
There is a problem in that it is difficult to create a required difference in thickness between the n″″ region and the n″″ region 35, and it is difficult to provide optimal characteristics to each of the VDMO$10, pMoS20, and nMo530. Ta. Further, the n+ buried layer 36, which is the formation region of the Zener diode 33, is made of phosphorus (P).
) is difficult to reproduce after re-diffusion, so the reproducibility of the Zener characteristics of the Zener diode 33 is not good or good, and furthermore, the n+ substrate 34 contains phosphorus (
P) Since a large amount of impurities are doped in advance, there is a problem in that abnormalities such as lattice defects are likely to occur in the semiconductor.

This invention has been made with attention to such problems, and it is possible to accurately control the difference in thickness between both the low concentration regions of the first conductivity type in the first region and the second region. hand,
The characteristics of VDMO8 and other semiconductor elements such as pMO8 and nMO8 can be optimized, and in general, the reproducibility of the Zener characteristics of the Zener diode is good, and the occurrence of lattice defects in the semiconductor is reduced. The purpose of this invention is to provide a semiconductor device that can

[Structure 1 of the Invention (Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention includes a highly concentrated substrate of a first conductivity type, and a structure in which a high concentration substrate is directly connected to the high concentration substrate on the high concentration substrate. a first conductivity type low temperature region formed by bonding;
A first region in the low concentration region is a substantial drain region, a source region of a first conductivity type is formed in a channel region of a second conductivity type formed in the first region, and a source region of a first conductivity type is formed in a channel region of a second conductivity type formed in the first region. A vertical MOSFET in which a gate electrode is formed on the channel region between regions via a gate insulating film, and a gate electrode is formed in a first region in the low concentration region in contact with the high concentration substrate and connected to the channel region. a first conductivity type high-concentration Zener region formed in such a manner that a Zener diode for regulating the drain breakdown voltage of the vertical MOSFET is formed by the junction;
The gist of the present invention is to include other semiconductor elements constituting peripheral circuits of the SFET and the like.

(Function) Since the high concentration substrate of the first conductivity type and the low concentration region of the first conductivity type are integrally formed by direct bonding, the high concentration Zener region of the first conductivity type for forming the Zener diode is The impurity of the first conductivity type can be diffused in advance to a desired thickness in a continuous supply state to a desired portion of the substrate that will be a low concentration region.

Therefore, the thickness of each low-concentration region in the first region and the second region can be precisely formed to a desired thickness, and a built-in Zener diode having a sufficiently high surge mm and low on-resistance can be used. VDMO8 and other semiconductor elements having desired breakdown voltage characteristics are manufactured on one chip with good reproducibility. Further, during the diffusion of the first conductivity type impurity for forming the high concentration Zener region, the occurrence of abnormalities such as lattice defects in the semiconductor is suppressed, and characteristic deterioration is prevented.

(Example) Hereinafter, an example of the present invention will be described based on FIGS. 1 and 2. In FIGS. 1 and 2, parts that are the same as or equivalent to those in FIG. 4 are designated by the same reference numerals and redundant explanations will be omitted.

First, to explain the structure of the semiconductor device, in FIG. 1, 1 is a high concentration n+ substrate, and on the n+ substrate 1,
The low concentration n-region 2 has a thickness of 10μ due to direct bonding with the substrate 1.
The layers are laminated to a required thickness of about m. VDMO810
An n+ Zener region 3 whose bottom surface is in contact with the n+ substrate 1 and whose top surface is in contact with the p-type channel region 5 is formed in the n- region 2 in the first region where the n-type transistor is formed. By forming this n+ Zener region 3, the thickness of the n- region 2 in the first region is reduced to a required thickness of about 3 μm. A pn junction between the n+ zener region 3 and the p-type channel region 5 forms a zener diode 4 that defines the drain breakdown voltage of VDMosio.

The n-region 2 in each of the first and second regions is formed with high precision to a thickness of about 3 μm and 10 μm, respectively, and the VDMO 810 is formed in the first region, and the
Other semiconductor elements for forming peripheral circuits, etc., including a pMO 820 and an nMO 830, are formed in the region.

Next, the structure will be explained in further detail by outlining an example of the manufacturing process using FIGS. 2(a) to (e).

2. Diffusion of H carvings to a desired depth in a desired portion of the substrate that will become the n- region 2 to form an n+ zener region 3. Diffusion for forming the n''' Zener region 3 can be performed to a required depth while continuously supplying n carved parts from the surface.

A first substrate body is formed by diffusing and forming an n1 zener region 3 on the substrate that will become the n- region 2.

(b) Prepare a second substrate body that will become n+ substrate 1, and after subjecting this second substrate body and the first substrate body prepared in step (a) above to a hydrophilic treatment, their surfaces are brought into close contact with each other. The rain cloud plate body is directly bonded by 7-nealing at an appropriate temperature. Due to this direct bonding, the bottom surface of the n+ Zener region 3 becomes n+
It is bonded so as to be in contact with the substrate 1. Note that the direct bonding of silicon substrates is a well-known technology (Japanese Patent Publication No. 1986-5).
1700).

(C) Grind the n-region 2 until it reaches a predetermined thickness. Through this step, the thickness of the n-region 2 in the first and second regions is set to a predetermined thickness.

(d) Formation of each gate oxide film by thermal oxidation of the surface of n- region 2, depositing polycrystalline silicon and patterning to form each electrode 8, 17, 25, these electrodes 8
．． P-type channel region 5, p-well 21, p-type channel region 5, p-well 21, by diffusion of p-carvings and n-carvings using 17.25 etc. as a mask.
Each source region 6.14.22, each drain region 15.2
3, etc., a required region for the 70MO810 with built-in Zener diode 4 is formed in the first region, and a required region for other semiconductor elements such as pMO820 and nMO830 is formed in the second region. .

(e) After forming the intermediate insulation m9 using PSG, contact holes are formed at desired positions by photoetching,
After depositing A11ll, it is photo-etched to form each electrode 11, 18, 19, 26, 27. Also n+
On the back side of the substrate 1, an anode electrode 13 of 70MO810 is provided.
form.

Next, the operation of the semiconductor device configured as described above will be explained.

The n+ zener region 3 is diffused and formed to a desired depth at a desired portion of the substrate that will become the n- region 2 by continuously supplying the n carved material. In this way, the substrate of the n- region 2 in which the n+ Zener region 3 is formed in advance and the n+ substrate 1 are directly bonded.

Therefore, as in the conventional example shown in FIG.
A large amount of phosphorus (P) impurity with a large diffusion constant is doped in advance into the required parts of the substrate, and after the n- region is epitaxially grown, the phosphorus (P) is removed by the required heat treatment.
Since the impurities are not re-diffused into the n- region to form an n+ buried layer, the n-artifacts from the n+ substrate are also prevented from re-diffusing into the n- region during this heat treatment. The thickness of each n-region 2 in the first and second regions is precisely formed to a desired thickness, and the 70MO81 has a built-in Zener diode 4 having sufficiently high surge resistance and low on-resistance.
0 and pMO820 with desired voltage resistance characteristics and n
Other semiconductor devices such as MO830 can be fabricated on one chip with good reproducibility.

Further, even during the diffusion of the n carved part to form the n+ Zener region 3, the occurrence of abnormalities such as lattice defects in the semiconductor is suppressed; deterioration of characteristics is prevented.

Then, the potential of n-region 2 is fixed to the power supply voltage applied from drain electrode 13, and VDMO810 and pMO8
20 and 0MO8 consisting of nMO830 are electrically separated and operate independently, and 70MO810 is
It is driven by a peripheral circuit composed of 0MO8 and the like to perform switching operations and the like.

[Effects of the Invention] As explained above, according to the present invention, the high concentration substrate of the first conductivity type and the low concentration region of the first conductivity type are integrally formed by direct bonding. The conductivity type high concentration Zener region can be expanded in advance to a desired depth at a desired portion of the substrate that will become the low concentration region while continuously supplying impurities of the first conductivity type. Therefore, the thickness of each low concentration region in the first region and the second region can be precisely formed to a desired thickness, and the vertical type with a built-in Zener diode has sufficiently high surge resistance and low on-resistance. MOSFETs and semiconductor elements with desired breakdown voltage characteristics can be manufactured on one chip with good reproducibility,
Further, there is an advantage that the occurrence of abnormalities such as lattice defects in the semiconductor during diffusion of the first conductivity type impurity for forming the high concentration Zener region is suppressed, and characteristic deterioration is prevented.

[Brief explanation of the drawing]

FIG. 1 is a longitudinal sectional view showing an embodiment of a semiconductor device according to the present invention, FIG. 2 is a process diagram showing an example of the manufacturing process of the same embodiment, and FIG. 3 is a vertical MOS used in a conventional semiconductor device.
FIG. 4 is a vertical cross-sectional view showing a conventional semiconductor device. 1: n+ substrate (high concentration substrate), 2: n- region (low concentration region), 3: n+ Zener region, 4: Zener diode, 5: p
Shape 1? 6: n+ source region, 7: gate insulating film, 8: gate electrode, 13 dorain electrode,
10: Vertical MOSFET. 20: pMO3 (other semiconductor element), 30; n
MO8 (other semiconductor elements). Agent Patent Attorney Yasuo Miyoshi Figure 3

Claims (1)

[Claims] A high concentration substrate of a first conductivity type, a low concentration region of a first conductivity type formed on the high concentration substrate by direct bonding with the high concentration substrate, and a first conductivity type low concentration region in the low concentration region. a source region of a first conductivity type is formed in a channel region of a second conductivity type formed in the first region, and the channel region is between the source region and the drain region; a vertical MOSFET on which a gate electrode is formed via a gate insulating film; A high concentration Zener region of a first conductivity type whose junction forms a Zener diode for regulating the drain breakdown voltage of the vertical MOSFET; and a second region of the low concentration region forming a peripheral circuit of the vertical MOSFET. A semiconductor device characterized by having another semiconductor element.