JPH0194661A - Gate turn-off thyristor - Google Patents

Abstract

PURPOSE:To optimize trigger sensitivity and turn-off losses by providing a layer resistance for a low resistance buffer layer to be formed on a first emitter layer so that a certain relation is satisfied between such layer resistance and a gap of a shortcircuit section. CONSTITUTION:A gate turn-off thyristor (GTO) comprises a high resistance first base layer 2 of the second conductivity type and a second base layer 3 of the first conductivity type on a first emitter layer 1 of the first conductive type while interposing a low resistance buffer layer 8 of the second conductivity type therebetween: a plurality of divided second emitter layers 4 of the second conductivity type on said base layers to form first and second main electrodes 6, 5 which are in contact with the first emitter layer 1 and the second emitter layer 4, respectively, and a gate electrode 7 which is in contact with the second base layer 3; and a shortcircuit section 9 which is in contact with the first main electrode 5 at a region where a part of the buffer layer 8 is made to expose to the surface of the first emitter layer 1. In such a GTO, parameters are so preset that a relation, rhos=K1/d<2>, where 10<-2=K<=10<6>, is satisfied with the gap for the shortcircuit section 9 being equal to d cm, and the layer resistance of the buffer layer 8 to rhos OMEGA/square.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) This invention relates to a gate turn-off thyristor with an anode short structure.

(Prior Art) A gate turn-off thyristor, so-called GTO, is a thyristor that can be turned off by applying a negative voltage to the gate electrode when an anode current is flowing, thereby sucking out part of the anode current from the gate electrode. The time required to turn off the GTO, ie, the gate turn-off time, is an extremely important characteristic because it determines the usable frequency limit of equipment using the GTO. In recent years, this gate turn-off time has tended to become longer due to the increase in the diameter and thickness of the silicon wafers used as well as the increase in the power capacity of GTOs.

In order to solve this problem, an anode short structure has been proposed in which a part of the n-base layer is brought into direct contact with the anode electrode (for example, Japanese Patent Publication No. 10143/1983). The structure is shown in FIGS. 22(a), (b), and (c). FIG. 22 (a) is a plan view seen from the cathode side, and (b) and (c) are the AA' line and B-
FIG. 3 is a cross-sectional view taken along line B'. This GTO has p10 emitter layer (first emitter layer) 51, n″″″ base layer 1
base layer) 52, n base layer (second base layer) 53,
p r consisting of n10 emitter layers (second emitter layers) 54
It is based on the lpn structure, and has an n0 emitter layer 54.
is divided into multiple pieces in an elongated pattern. soil, record p.
An anode electrode (first main electrode) 56 is provided on the surface of the ten emitter layer 51, a cathode electrode (second main electrode) 55 is provided on the surface of the n ten emitter layer 54, and a cathode electrode (second main electrode) 55 is provided on the surface of the n ten emitter layer 54.
A gate electrode 57 is formed on each surface of the semiconductor device 3. The n″″ base layer 52 has a portion under the cathode electrode
The anode electrode 5 is exposed at the surface of the emitter layer 51.
6, and this portion serves as a short-circuit portion 58. By providing such a short-circuit portion 58, carriers in the 1-base layer 52 can be effectively discharged to the anode electrode 5B during turn-off, thereby making it possible to shorten the turn-off time. Become.

Figure 23 (a), (b), and (c) are GTOs as described above.
In contrast, this is an example in which the thickness of the n- base layer 52 is reduced by adding a low-resistance n+ buffer layer 59 (Japanese Unexamined Patent Publication No. 56-6790). Here, FIG. 23(a) is a plan view seen from the cathode side, and FIGS. 23(b) and 23(c) are sectional views taken along line AA' and line BB' in FIG. 23(a), respectively. . By providing such a low-resistance n+8777 layer 59, the thickness of the high-resistance n-base layer 52 can be made thinner, which provides the advantage that the on-voltage can be lowered. And this low resistance n+877
The turn-off characteristics are further improved by the combination of the seven layer 59 structure and the anode fist short structure.

However, an anode having an n+8777 layer as shown in FIG. 23 and a GTO having a short structure have a problem in that the gate trigger sensitivity deteriorates. This is because the short resistance value, which is equimetrically inserted between the base and emitter of the parasitic pnp transistor constituted by the p emitter, n base, and p base, becomes too small due to the presence of the low resistance n+8777 layer 59.

Further, in the conventional GTO, the p base layer 53 and the p+ emitter layer 51 are formed simultaneously by diffusion, and the diffusion depth xj is, for example, 70 μm to 90 μm. The reason is as follows. The depth of the p base layer 53 and the p base layer 53 is an important factor that determines the characteristics of the GTO. The diffusion depth of the emitter layer 51 needs to be deep to a certain extent. The reason why the p-mitter layer 51 is thick is that it is conventionally made of silicon 9 pellets as a thermal buffer plate.
.

This is because it is made of alloy plates and W plates. At this time, the alloy layer has a thickness of 20 μm to 30 μm, and sometimes aluminum spikes can penetrate as much as 60 μm into the silicon pellet. Therefore, the p-mitter layer 51 also has a thickness of 75 μm.
It is desirable to have a thickness of ~90 μm.

However, in the GTO shown in FIG.
If the thickness of the short-circuit portion 58 is increased, the short-circuit portion 58 will spread laterally when it is formed by diffusion, and there is a problem that the dimensions of the short-circuit portion 58 cannot be reduced.

In addition, as shown in FIG. 23, a low resistance n+8777 layer 59
If the thickness of the p-mitter layer 51 is increased using GTO added with p-type, it is virtually impossible to form the n+8777 layer 59 by diffusion. Therefore, in this case, the n+8777 layer 59 must be formed by epitaxial growth, but a reduction in breakdown voltage yield due to defects during growth is unavoidable.

(Problems to be Solved by the Invention) As described above, in the GTO with the anode short-circuit structure provided with n+8777 layers, the larger the short-circuit ratio of the anode, the shorter the turn-off time becomes, and the reactive power consumed during turn-off decreases. Although it is possible to reduce the so-called turn-off loss, it has the disadvantage that the trigger sensitivity is reduced.

This invention was made in consideration of the above circumstances, and its purpose is to improve trigger sensitivity and turn-off loss by optimizing the impurity concentration of the n+8777 layer according to the pattern of the anode short structure. An object of the present invention is to provide a gate turn-off thyristor that can be optimized.

[Structure of the Invention] (Means for Solving the Problems) The gate turn-off thyristor of the present invention has a second conductivity type emitter layer formed on a first conductivity type first emitter layer through a second conductivity type low resistance buffer layer. A high-resistance first base layer and a first conductivity type second base layer are laminated in this order, and a plurality of second conductivity type second emitter layers are formed on the second base layer. A first main electrode and a second main electrode are formed in contact with the first emitter layer and the second emitter layer, respectively, a gate electrode is formed in contact with the second base layer, and a part of the low resistance buffer layer is formed. is exposed on the surface of the first emitter layer and has a short circuit portion in contact with the first main electrode, wherein the short circuit portion is limited to a part of the second emitter layer in the length direction. and the distance between the short circuit parts is d (cm).
, the layer resistance in the low resistance buffer layer is ρs (Ω/
A feature (effect) characterized in that the value of ps is set so as to satisfy the relationship ρs=K(1/d2) (however, 10-2≦K≦106). By optimizing the layer resistance of the low resistance buffer layer according to the pattern of the anode short structure,
A gate turn-off thyristor with small turn-off loss and sufficiently high gate trigger sensitivity can be obtained.

(Example) This invention will be explained below with reference to Examples.

1(a), (b), and (c) show the configuration of a GTO according to an embodiment of the present invention, in which (a) is a plan view seen from the cathode side, and (b), (c). ) are respectively (
It is a sectional view along the AA' line and the BB' line of a).

This GTO has a p-type emitter layer (first emitter layer) 1,
It is based on a pnpn structure consisting of a high-resistance n-base layer (first base layer) 2, p-base layer (second base layer) 3, and n-type emitter layer (second emitter layer) 4. The transmitter layer 4 is divided into a plurality of pieces in an elongated pattern.

Furthermore, a low resistance n+8777 layer 8 is provided between the n- base layer 2 and the p-type emitter layer 1.

Further, an anode electrode (first
A cathode electrode (second main electrode) 5 is formed on the surface of the n-type emitter layer 4, and a gate electrode 7 is formed on the surface of the p-base layer 3. And the above n
A portion of the +8177 layer 8 under the cathode electrode is exposed to the surface of the p-mitter layer 1 and is in contact with the anode electrode 6, and this portion serves as a short circuit portion 9. This short-circuit portion 9 is provided in a limited portion in the length direction of the n-mitter layer 4, each having a circular shape as shown in the figure, and a diameter of, for example, the n-mitter layer. 4 is limited to 1/10 or less of the length in the length direction. In the case of this embodiment, the pattern shape of the short-circuit portion 9 is circular, but it may be square, rectangular, or elliptical. In addition, for each cathode electrode 5, GTO
One element is configured.

In such a configuration, the distance between the short circuit parts 9 is set to d(c
m), the layer resistance in the low resistance buffer layer 8 is ρs
(Ω/mouth), ρs = K <1/d2)
The value of ρs is set to satisfy the following relationship: '-1 (10-2≦K≦106).

Note that the above-mentioned layer resistance ρs refers to the average specific resistance of the diffusion layer as ρ(
Ω・Cm), and the thickness is t (am), ρs −ρ/l ・・・ 2
This is the quantity expressed as . This layer resistance can be easily determined using a four-probe method in which the p-mitter layer 1 is etched and removed from the anode side of the GTO, and four probes are brought into contact with the exposed surface of the n+8777 layer 8. can.

FIG. 2 is a perspective view showing the p-mitter layer 1 and the n+8777 layer 8 extracted from the GTO of the above embodiment. Now, the current density per unit area flowing through the n+8777 layer 8 is 11, the distance between the short circuits is d, the radius of the short circuit 9 is a, and the pn diode formed by the mitter layer 1 and the n+8777 layer 8 is The threshold voltage of , that is, the voltage required to cause injection from the p emitter layer 1 to the n+8777 layer 8, is VjSp, and the width of the emitter layer 1 is W7, then the voltage Vj is calculated by the following formula. Given.

However, R is the lateral resistance in the n+8777 layer 8 from the region where the current i flows to the short circuit part 9, and this R is given by the following equation.

R-(ρsy)/W... 4 Therefore, by substituting equation 4 into equation 3 above, the following equation 5 is obtained.

-itρs/21 ((d2/4)-a21...
5 Here, assuming Vj-0.5V, ρs is given by the following formula.

ρs = 14/il 11/ (d2-4 a2)
)” (4/1)(1/d2) −6 In the above six equations, if 4/imK is set, the following seven equations are obtained.

ρs=K(1/d21...7 where, G
For example, the area per element of TO is 0.27x4
00xlO-4-1,l
When configured with elements, the allowable current iar per element is ia T-200/24 g'; 0. 8 (A)...
・It becomes 8. Therefore, the maximum value of l in the above 6 formulas iMAx
is given by the following equation.

iMAX ”0.8 (A)/1.IXl 0' (c
m2)! =i72.7 (A/cm2)...9 Therefore, in this case, the above value 4/i is approximately 0.
It becomes 06.

On the other hand, the limit of ρs in actually manufacturing devices is 104
(Ω/mouth), and if ρs is higher than this, bunch-through will occur and the withstand voltage will decrease. At this time, the diameter is 1001
00 (GTO) with only one short-circuit section, it becomes 104-K (1/102) ... 10. Therefore, the range of K is from 0.06 to 106, and a margin is taken. Therefore, the range of K is from 10-2 to 106.

By the way, under normal GTO usage conditions, IGT is 50 (
A) below, in which case the range of K is 0.2≦K≦
It becomes 106. Regarding the upper limit of K, considering that the current unit element size is 1 cm or less and one short circuit is provided per element, the range of K is 0.
．． 2≦K≦104.

FIGS. 3 and 4 are diagrams for explaining the distance d between the short-circuit portions, respectively. Generally, when a plurality of short-circuit parts 9 are provided in the length direction of the n+ emitter layer 4, d is a distance from the center of one short-circuit part to the next short-circuit part as shown in FIG. is the distance to the center of

On the other hand, the pattern of the n-mitter layer 4 is changed to the pattern of the p-mitter layer 1.
When projected to the side, d is the short circuit part 9 as shown in FIG.
It is the maximum value of the distance di, d2°d3 from the center of the projected n-mitter layer pattern to the edge 10.

Next, a specific example of the above-mentioned interval d will be explained.

In FIG. 5(a), a plurality of short circuit parts 9 are provided in the length direction of the n00m emitter layer 4, and p÷emitter layer 1
is surrounded by n ten layers, and in this case, the distance d is the distance d1°d2 . d3. ... is the maximum value of dn.

FIG. 5(b) shows the case where n÷emitter layer 4 is provided with an elliptical short-circuit part 9 in the length direction, and p÷emitter layer 1 is surrounded by n0 layers. , at this time the above d
The distances are the illustrated distances d1°d2. d3. This is the maximum value of d4.

In FIG. 5(C), a plurality of short-circuit parts 9 are provided in the length direction of the n-mitter layer 4, and the p-mitter layer 1 is provided with a plurality of short circuit parts 9.
is surrounded by a p+ or p- layer, and in this case, the distance d is the illustrated distance 2dl, 2d2 . d3.
, dn-1, -...2dn.

In FIG. 5(d), an elliptical short-circuit portion 9 is provided in the length direction of the n÷emitter layer 4, and the p-layer emitter layer 1 is a p- layer, a p-layer or an insulating film. (OXIDE)
etc., and in this case, the distance d is the illustrated distance di, d2°d3 . 2 of the maximum value of d4
The value will be doubled.

6(a), (b), and (c) show the configuration of a GTO according to a second embodiment of the present invention, where (a) is a plan view seen from the cathode side, and (b), (c) is a sectional view taken along line AA' and line BB' in (a), respectively. In this GTO, short circuit portions 9 are provided at four locations in the length direction of the n+ emitter layer 4, respectively.

The distance d between the short circuit parts 9 in this embodiment and the embodiment shown in FIG. 1 above corresponds to the case shown in FIG. 5(c) above.

FIGS. 7(a), (b), and (c) show the configuration of a GTO according to a third embodiment of the present invention, in which (a) is a four-dimensional plan view seen from the cathode side, and (b) , (c) are cross-sectional views taken along line AA' and line BB' in (a), respectively. In this GTO, the p-type emitter layer 1 is divided into a plurality of parts corresponding to the n+ emitter layer 4, and the separated parts 11 are covered with an insulating film 12. Like this p
By dividing the transmitter layer 1, the spread of carriers in the on-state of the GTO can be suppressed, and the turn-off speed can be increased. Further, the distance d between the short circuit portions 9 in this embodiment corresponds to the case shown in FIG. 5(C) above.

FIGS. 8(a), (b), and (c) show the configuration of a GTO according to a fourth embodiment of the present invention, in which (a) is a plan view seen from the cathode side, (b), (c) is a sectional view taken along line AA' and line BB' in (a), respectively. In this GTO, the p-type transmitter layer 1 is divided into a low-resistance portion IA consisting of a p medium type with a relatively high impurity concentration of 1×1016/cm3, and a low-resistance portion IA with an impurity concentration of 4×1013.
It is constructed of a high resistance part IB made of p-type and having a relatively low resistance of /cm3. In each element, a low resistance part IA is provided to surround the short circuit part 9, and a high resistance part IB is further provided to surround this low resistance part IA, and is the main current path in the on state. A certain low resistance portion IA is separated from other elements by a high resistance portion IB. The distance d between the short circuit parts 9 in this embodiment corresponds to the case shown in FIG. 5(c) above.

FIG. 9 is a diagram summarizing the results of manufacturing and manufacturing the GTOs of each of the above embodiments by varying the value of K and confirming their operation. The GTO actually manufactured here has a diameter of 33 mm and has an anode short structure provided with 043777 layers. Note that d in the figure is the interval between the short circuit parts 9, and ρs is the layer resistance of the 043777 layer 8. In addition, ρs is set to two types, 228 (Ω/mouth) and 975 (Ω/mouth), and d is 0.28 (Cm) and 0.
．． 18 (cm), 0.11 (cm), 0.016
(Cm). Here, the distance between the short circuit parts d
is 0.28 (cm), which means that the GT of the embodiment shown in FIG. 1 has one short circuit for each element.
Corresponds to O. Also, the spacing d is 0.18 (cm) when two short-circuit parts are provided for each element, and the spacing d is 0.11 (cm) when three short-circuit parts are provided for each element. Furthermore, when d is 0.016 (cm), it is the case that one elliptical short-circuit portion is provided for each element.

Here, K is 16, 6.7.4.2.7.71.1.3
It was confirmed that it operated as a GTO when K was 1.6 and 11.4, and it did not operate as a GTO when K was 0.06.

Further, when K is 0.3, the gate trigger current 6T increases, but it was confirmed that the device operates as a GTO.

Therefore, when determining the value of K experimentally, it is 0.3<K<7
If it is designed within the range of 1.1+α, it will operate as a GTO.

FIG. 10 is a characteristic diagram showing the relationship between the short circuit distance d (mm) and the gate trigger current IGT (mA) when the layer resistance ρs of the n+ buffer layer 8 is changed. Normally, in Cyrisk with 043777 layers, that 0
The layer resistance ρs of the 43777 layers is designed to be 228 (Ω/hole) or more. Further, the interval d between the short circuit parts of the normal anode short structure is designed to be 0.16 (mm). In the figure,
The upper shaded area has a large value of gate trigger current IGT and does not operate as a GTO under normal gate conditions, and the lower shaded area is where bunch-through occurs and voltage resistance design is difficult. This is a difficult area. In the case of conventional thyristors, the value of gate trigger current IGT is 104 (mA) or more, and under normal gate conditions G
It does not work as a TO. On the other hand, if the value of K is set within the area without diagonal lines, 043777
Even if a layer is provided, it will operate as a GTO.

By designing the value of K in this way, 04377
The gate trigger current (gate sensitivity) of the GTO with seven layers was almost equal to that of the conventional one without the n+8977 layer, and the turn-off loss could be reduced by more than 30%.

By the way, as shown in FIG. 8, the p+ emitter layer 1 is divided into a low resistance part IA made of p+ type with a relatively high impurity concentration and a p- type with a relatively low impurity concentration.
The GT consists of a high resistance part IB consisting of a mold.
O also has the following effects:

In other words, since the low resistance part IA, which is the main current path in the on state, is separated from other elements by the high resistance part IB, n in each element is
+The value of the lateral resistance of the buffer layer 8 becomes large. This increases the gate sensitivity, suppresses the spread of the on-current in the lateral direction during the on-state, reduces the Tilmi flow during turn-off, and further reduces turn-off loss. In addition, in this way, p÷emitter layer 1 is composed of a low resistance part IA and a high resistance part IB,
The first part is provided with only one short-circuit part for each element.
It can also be implemented in a GTO as shown in the figure.

Figure 11 shows the turn-on voltage VT in the GTO with the same diameter and pattern but no short circuit (A), one short circuit (B), and four short circuits (C).
M (V) and turn-off loss Eof'f' (J/
FIG. In other words, this characteristic diagram shows the change in turn-off loss when the lifetime is controlled by electron beam irradiation and the turn-on voltage is changed. You can see that the loss is decreasing.

On the other hand, FIG. 12 is a characteristic diagram showing the relationship between the number of short circuit parts per element and the gate trigger current 1c T (mA). It can be seen from this characteristic that the gate trigger current increases as the anode short ratio increases.

As can be seen from FIGS. 11 and 12 above, the p-type transmitter layer 1 is composed of a low resistance part IA and a high resistance part IB, and the low resistance part IA is separated from other elements by the high resistance part IB. By doing so, it is possible to suppress the spread of carriers in the on state without increasing the area of the short-circuit portion 9, that is, without increasing the trigger sensitivity, and it is possible to reduce the Tilmi flow at the time of turn-off. Incidentally, when the low-resistance portion IA was separated by the high-resistance portion IB, the Tilmi flow was reduced to 2/3 compared to when it was not separated. This further reduces turn-off loss.

FIG. 13 shows the turn-on voltage VTM (V) in the GTO (A) of the embodiment shown in FIG. 8 and the conventional GTO (B).
FIG. 3 is a characteristic diagram showing the relationship between Eoff (J/PULSE) and turn-off loss Eoff (J/PULSE). As shown, the embodiment of FIG. 8 has less turn-off loss. Furthermore, when turn-off loss is not considered, the gate trigger sensitivity (gate trigger current IGT) is about 20 (A) in the conventional example, but in the case of Fig. 8 it is 0.5 (A) to 1 ( A)
It has been confirmed that this decreases to a certain extent.

The present invention can be implemented in various devices other than the above-mentioned GTO as long as the device is based on a pnpn structure, such as a 1-FET as shown in the cross-sectional view of FIG. P-channel MOS-GT as shown in the cross-sectional view
O, N-channel MOS as shown in the cross-sectional view of Figure 16
- GTO, MOS thyristor as shown in the cross-sectional view in Figure 17, MOS thyristor with turn-off gate as shown in the cross-sectional view in Figure 18, GTO with amplification gate structure as shown in the cross-sectional view in Figure 19, etc. can do. Na・
In FIGS. 14 to 19, parts corresponding to those in FIG. 1 are given the same reference numerals, and their explanations will be omitted.

In the B1-FET shown in FIG. 14, 21 is a gate oxide film, and the gate electrode 7 is provided on this gate oxide film 21.

In the MOS-GTO shown in FIG.
A p-type medium layer 22 is provided which serves as the source or drain of the channel MOS transistor. Further, 21 is a gate insulating film.

In the MOS-GTO shown in FIG. 16, an n medium layer 23 is provided in the p base layer 3 to serve as the source or drain of the N channel MOS transistor.

In the MOS transistor shown in FIG. 17, a gate electrode 7 is provided on a gate insulating film 21.

In the MOS thyristor with a turn-off gate shown in FIG. 18, a turn-off gate electrode 24 is provided on the p base layer 3.

In the amplification gate structure GTO of FIG. 19, a gate electrode 25 is provided on the p base layer 3 in the amplification section. In this case, it is necessary to either not provide the shorting section 9 in the amplification section, or to provide the shorting section 9 as shown in the figure, and to make the diameter of the shorting section smaller than that of the main body GTO to reduce the short circuit ratio.

By the way, it has been found that the characteristics of the GTO p-type emitter layer actually change depending on the total amount of charge rather than its concentration profile. For this reason, the p-mitter layer 1 and the n+
In order not to reduce the implantation efficiency between the p+ emitter layer 1 and the 8977 layer 8, the p+ emitter layer 1 is formed by boron ion implantation in the elements of each of the above embodiments. In addition, the p-mitter layer 1
The anode electrode 6 is formed by sintering the aluminum layer, and the anode electrode 6 is formed by sintering the aluminum layer, and the anode electrode 6 is formed by making the thickness of the aluminum layer 30 μm or less, without alloying the silicon pellet with an MO plate, W plate, etc. as a thermal buffer plate as in the conventional method. The electrodes are formed by pressure contact.

FIG. 20 shows the injection efficiency between the p+ emitter layer 1 and the n+ 3777 layer 8, and the total amount of impurities in the p+ emitter layer 1 (c
It is a characteristic diagram which shows the relationship with m-2). As is clear from the figure, in order to bring the injection efficiency close to 1, the total amount of impurities in the p-type emitter layer 1 should be about 10@15 (cm@-2) or more.

FIG. 21 shows the injection efficiency between p÷emitter layer 1 and n+3777 layer 8, and the total amount of impurities in n+3777 layer 8 (c
FIG. 3 is a characteristic diagram showing the relationship between As is clear from the figure, to bring the injection efficiency close to 1, n+3777
The total amount of impurities in layer 8 may be about 1014 (cm-2) or less. At this time, the layer resistance ρs of the n+3777 layer 8
The value is about 200 (Ω/mouth).

By making the p-mitter layer 1 thinner in this way, the n
The +3777 layer 8 can now be formed by a diffusion method, resulting in improved reliability and simplification and rationalization of the process. Furthermore, since the p-mitter layer 1 is thin, the lateral spread during diffusion formation of the short-circuit portion 9 is suppressed, making it possible to form a fine anode short pattern.
It is possible to make high trade-offs in gate sensitivity, switching loss, etc.

In addition, since the formation of the thin p-type emitter layer 1 can be performed after the base diffusion, it requires the longest time in the GTO diffusion process. can be standardized, and final products can be made separately in later processes. As a result, a wide variety of products can be manufactured rationally and without waste. Also, GTO
The characteristics of can be optimized not only by lifetime control but also by short patterns on the anode side if necessary after base diffusion, making it possible to manufacture products with various characteristics.

[Effects of the Invention] As explained above, according to the gate turn-off thyristor of the present invention, the impurity concentration of the n+8777 layer is optimized according to the pattern of the anode short structure, which improves trigger sensitivity and turn-off loss. Optimization can be achieved.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of a GTO according to an embodiment of the present invention, in which (a) is a plan view, (b) and (c) are sectional views, and FIG. 2 is a diagram of a GTO according to the above embodiment. The perspective view, FIG. 3, and FIG. 4 show the above-mentioned GT.
5 is a diagram for explaining a specific example of the above-mentioned interval, and FIG. 6 is a diagram showing the configuration of a GTO according to a second embodiment of the present invention. , (a
) is a plan view, (b) and (c) are sectional views, respectively, FIG. b) and (C) are sectional views, respectively, and FIG. 8 is a GT according to a fourth embodiment of the present invention.
It shows the configuration of O, (a) is a plan view, (b)
(c) is a sectional view, FIG. 9 is a diagram showing numerical values under various conditions for each of the above embodiments, FIGS. 10 to 13 are characteristic diagrams for explaining each of the above embodiments, and FIG. 14 to 19 are cross-sectional views showing the configurations of various other elements to which the present invention is applicable, FIGS. 20 and 21 are characteristic diagrams for explaining each of the above embodiments, and FIG. 22 and FIG. 23 are cross-sectional views showing the configuration of a conventional GTO. 1...p emitter layer (first emitter layer), IA...
・Low resistance part, 1B... High resistance part, 2... High resistance n-base layer (first baize layer), 3... P base layer (second base layer), 4... n Juko emitter layer (second emitter layer), 5... cathode electrode (second main electrode), 6
. . . Anode electrode (first main electrode), 7. Gate electrode, 8. Low resistance n+3177 layer, 9. Short circuit portion, 11. Separation portion, 12. Insulating film. . Applicant's representative Patent attorney Takehiko Suzue Figure 2, 3rd, 4th, Yago Shitona P comparison (I1, Figure 14, Figure 15, 1, Showing the case) -252113 No. 2, Name of the invention Gate turn-off thyristor 3, Relationship with the person making the amendment Patent applicant (307) Toshiba Corporation 4, Agent UBE Building 7, 3-7-2 Kasumigaseki, Chiyoda-ku, Tokyo;
Contents of amendment (1) The scope of claims is corrected as shown in the attached sheet. (2) On page 8, line 12, replace “75μm” with “75μm”.
0 μm”. (3) Add the following sentence between page 13, line 13 and line 14. In addition, the impurity concentration distribution of the n+ buffer layer 8 is expressed as N (x) by the position function X in the depth direction, and the electron mobility is expressed as μ (X).
, if the unit charge is 8, then ps = 1/[qJ'
It can be expressed as tt (x)N (x)dxl^...2'. Here, A and B indicate the range in the thickness direction of the n+ buffer layer 8. (4) On page 14, line 5, replace the phrase “current i flows” with “
The current i W dy flows in.'' (5) From page 15, line 4 to page 16, line 10, the sentence "wherein, GTO...is 50(A) or less" is corrected as follows. Here, the value of K is calculated as follows when the GTO has a structure having an amplification gate or when the gate trigger current is inputted in a pulse form by an external circuit. Now, for example, the area per element of GTO is 0.2
7 x 400 iaT is taT-1200'/248ζ4.8 (A)...
It becomes 8. Therefore, the maximum value of i in the above 6 formulas iMAX
is given by the following equation. iMAX-4,8(A)/1.1 x 10' (cm2)! q436.4 (A/Cm2
)...9 Therefore, in this case, the above value 4/i is approximately 0.
It becomes 01. On the other hand, the limit of ρs in actually manufacturing devices is 104
(Ω/mouth), and if ρs is higher than this, punch-through will occur and the withstand voltage will decrease. At this time, when the element length is 100100 (GTO) and only one short-circuit part is provided per element, it becomes 10' - K (1/102) ... 10. Therefore, the range of K is 0. The value is from 01 to 106. By the way, under the conditions of use of GTO without inputting the gate trigger current in a pulsed state or without an amplification gate, IGT is 50 (A) or less, and (6) Page 17, 2
In lines 1 to 12, the sentence ``On the other hand, ... becomes the maximum value.'' is corrected as follows. On the other hand, when the distance between the short-circuit parts is smaller than the length from the center of the short-circuit part to the end 10 when the pattern of the n-type mitter layer 4 is projected onto the p-mitter layer 1 side, d is the fourth As shown in the figure, the distance from the center of the short circuit 9 to the end 10 of the projected n+ emitter layer pattern is 2dl, 2d2.2d.
This is the maximum value among 3. FIG. 5(a) shows a case in which the p-mitter layer 1 is surrounded by the n-mitter layer 8, and a plurality of short-circuit parts 9 are provided in the longitudinal direction of the n-mitter layer 4. In this case, the distance d becomes the width of the p emitter, that is, 2d2 in the figure. In addition, the p-layer 1 is surrounded by the n-layer 8,
Even when the short circuit portion 9 is not provided in the n-type emitter layer 4, the distance d is the width of the p-emitter. (7) Add the following sentence after the third line of page 18. Note where n is an integer and di, d2 . dn is short circuit part 9
It is the distance from the center of d3 to the edge of the pattern obtained by projecting the n0 emitter layer pattern onto the p emitter layer, and d3
．． . . . dn-1 each represents the interval between the short circuit parts 9. (8) Add ``ni'' between ``Example'' and ``Okeru'' on page 20, line 9. (9) On page 22, lines 4 to 18, “Usually...
It will work. '' is corrected as follows. In the diagram, the shaded area is the area where punch-through occurs and it is difficult to design the voltage resistance. (10) Delete the sentences "source or" from lines 19 and 20 on page 26 and lines 3 and 4 on page 27, respectively. (11) Add the following sentence after page 27, line 15. A GT having an amplification gate structure as shown in Fig. 19 of this note.
The effects obtained when this invention is implemented in O are described below. As mentioned above, it is also possible to significantly reduce the anode short resistance in the GTOs shown in FIGS. 1 and 2, for example. In that case, the gate trigger sensitivity is reduced, but at the same time the turn-off loss is significantly reduced. By compensating for this decrease in gate trigger sensitivity by employing an amplification gate structure, it is possible to significantly reduce turn-off loss while keeping gate trigger sensitivity the same as before. In the conventional amplification gate structure GTO, it is possible to reduce the turn-on loss, but it is not possible to reduce the turn-off loss without increasing the on-voltage.In contrast, in the case of this embodiment, the amplification gate section has a gate sensitivity and It can be used to significantly reduce turn-off loss while keeping the on-voltage the same as before. Further, according to this embodiment, the anode short-circuit ratios of the main GTO section and the amplification gate section can be varied independently and over a wider range in accordance with the intended characteristics of the element than in the conventional case. (12) Figure 10 of the drawings will be corrected as shown in the attached sheet. (13) Figure 16 of the drawings will be corrected as shown in the attached sheet. 2. Claims (1) A high resistance first base layer of a second conductivity type and a high resistance first base layer of a first conductivity type are formed on a first emitter layer of a first conductivity type via a low resistance buffer layer of a second conductivity type. Two base layers are formed in this order,
A second emitter layer of a second conductivity type divided into a plurality of parts is formed on the second base layer, and a first main electrode and a second emitter layer are formed in contact with the first emitter layer and the second emitter layer, respectively.
A main electrode is formed, a gate electrode is formed in contact with the second base layer, and a portion of the low resistance buffer layer is exposed on the surface of the first emitter layer and is in contact with the first main electrode. In a gate turn-off thyristor having a short-circuit portion, where the interval between the short-circuit portions is d (cm), and the layer resistance in the low-resistance buffer layer is ρs (Ω/hole), ρs −K (1/d2) ( A gate turn-off thyristor characterized in that the value of ρs is set to satisfy the following relationship: 10-2≦K≦106). (2) According to claim 1, the distance d between the short circuit parts is twice the distance to the end of the pattern of the second emitter layer when projected onto the first emitter layer. Main gate turn-off thyristor. (3) The main gate turn-off thyristor according to claim 1, wherein the value of K is set to satisfy 0.2≦K≦106. (4) The main gate turn-off thyristor according to claim 1, wherein the value of is set to satisfy 0.2≦K≦104. (5) The main gate turn-off thyristor according to claim 1, wherein a plurality of the short circuit portions are provided in the length direction of the second emitter layer. (6) The first emitter layer includes a low-resistance portion into which impurities of a first conductivity type are introduced at a high concentration, and a low-resistance portion surrounded by the low-resistance portion into which impurities of a first conductivity type are introduced at a low concentration. A main gate turn-off thyristor according to any one of claims 1 and 5, comprising a high resistance portion. (7) The main gate turn-off thyristor according to claim 6, wherein the impurity concentration in the high resistance portion of the first emitter layer is set to about 1/2 or less of that in the low resistance portion. (8) A main gate turn-off thyristor according to any one of claims 1 to 7, wherein the first emitter layer has a thickness of 30 μm or less. (9) A main gate turn-off thyristor according to any one of claims 1 to 8, wherein the gate turn-off thyristor is comprised of a main gate turn-off thyristor section and an amplification gate section. (10) The main gate turn-off thyristor according to claim 9, wherein the amplification gate section is provided with the short circuit section. (11) The main gate turn-off thyristor according to claim 10, wherein the value of said in the amplification gate section is smaller than that in the main gate turn-off thyristor section. (12) The main gate turn-off thyristor according to claim 9, wherein the amplification gate section is not provided with the short circuit section. Applicant's agent Patent attorney Takehiko Suzue Figure 16

Claims (1)

[Scope of Claims] (1) A high-resistance first base layer of a second conductivity type and a high-resistance first base layer of a first conductivity type are formed on a first emitter layer of a first conductivity type via a low-resistance buffer layer of a second conductivity type. two base layers are stacked in this order, a second emitter layer of a second conductivity type divided into a plurality of parts is formed on the second base layer, and a second emitter layer is formed in contact with the first emitter layer and the second emitter layer, respectively. A first main electrode and a second main electrode are formed, a gate electrode is formed in contact with the second base layer, and a part of the low-resistance buffer layer is exposed on the surface of the first emitter layer, and the above-mentioned In a gate turn-off thyristor having a short-circuit portion with which the first main electrode comes into contact, the short-circuit portion is provided only in a part of the second emitter layer in the length direction, and the distance between the short-circuit portions is set to d( cm), and when the layer resistance in the above low-resistance buffer layer is ρs (Ω/mouth), the relationship ρs=K(1/d^2) (however, 10^-^2≦K≦10^6) A gate turn-off thyristor characterized in that the value of ρs is set so as to satisfy the following. (2) According to claim 1, the distance d between the short-circuit parts is twice the distance to the end of the pattern of the second emitter layer when projected onto the first emitter layer. Gate turn-off thyristor as described. (3) The gate turn-off thyristor according to claim 1, wherein the value of K is set to satisfy 0.2≦K≦10^6. (4) The gate turn-off thyristor according to claim 1, wherein the value of K is set to satisfy 0.2≦K≦10^4. (5) The gate turn-off thyristor according to claim 1, wherein a plurality of the short circuit portions are provided in the length direction of the second emitter layer. (6) The first emitter layer includes a low-resistance portion into which impurities of a first conductivity type are introduced at a high concentration, and a low-resistance portion surrounded by the low-resistance portion into which impurities of a first conductivity type are introduced at a low concentration. A gate turn-off thyristor according to any one of claims 1 and 5, comprising a high resistance portion. (7) The gate turn-off thyristor according to claim 6, wherein the impurity concentration in the high resistance portion is set to about 1/2 or less of that in the low resistance portion. (8) The gate turn-off thyristor according to any one of claims 1 to 7, wherein the first emitter layer has a thickness of 30 μm or less. (9) The gate turn-off thyristor according to any one of claims 1 to 8, wherein the gate turn-off thyristor includes a main gate turn-off thyristor section and an amplification gate section. (10) The gate turn-off thyristor according to claim 9, wherein the amplification gate section is provided with a short circuit section. (11) The gate turn-off thyristor according to claim 10, wherein the value of K in the amplification gate section is smaller than that in the main gate turn-off thyristor section. (12) The gate turn-off thyristor according to claim 9, wherein the amplification gate section is not provided with a short circuit section.