JPH0194452A - Method for supervising central processing unit - Google Patents

Abstract

PURPOSE:To prevent the destruction of a control object due to a reckless operation by providing a supervising circuit to confirm that the signal of a CPU is outputless and to generate an output, resetting the CPU by means of the output, simultaneously, calculating the prescribed number of output numbers, and giving a caution. CONSTITUTION:A supervising circuit 12 is connected to the output terminal of a CPU 11, it is confirmed that the signal of the output terminal of a within- reference time is outputless and the output is generated, and the CPU 11 is automatically reset. Since a calculating means 13 is reset or preset by the output of a timer circuit 14 to be started by means of the prescribed output value of a calculating means 13 to calculate the output of the supervising circuit 12 or by means of the initial output of the supervising circuit 12, it is confirmed that the signal of a prescribed frequency from the supervising circuit 12 within the setting time of the timer circuit 14 is executed and the calculating means 13 executes the output, and thereby, the caution can be given. Thus, the CPU 11 is automatically reset to a disturbance for a short period, the caution is given to the external part to the disturbance for a long period, and the destruction of the control object can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for monitoring a central processing unit that controls electric appliances such as a facsimile machine, a washing machine, and a video camera, as well as various other control devices.

[Conventional technology]

In recent years, microcomputers have been increasingly used to control electrical products, and control by such microcomputers is performed by a control program stored in a preprogrammed read-only memory ROM.

In such devices, the control means may be disturbed by external noise or power supply voltage fluctuations, and in such cases, the central processing unit of the microcomputer (
A reset operation for resetting the CPU (hereinafter also referred to as CPU) to an initial state and starting control operations again is performed manually or automatically using an incomplete method.

[Problems to be Solved by the Invention] However, if the circuit is configured to automatically reset the CPU by giving a reset signal, the CPU always tries to be reset, so Nm line noise, static electricity noise, high frequency If the disturbance such as noise is short, the CPU can return to normal operating state without any problem, but if the above disturbance continues for a long time, the uncontrollable time will become longer, and Hiiragi will not be able to control the target. There was a problem in that it could be destroyed.

The present invention was made in view of the above circumstances, and the CPU is automatically restored in response to a relatively short disturbance, but in the event of a long-term disturbance, an alarm is issued to the outside and the CPU is The purpose of the present invention is to provide a method for monitoring a central processing unit that prohibits the activation of a central processing unit.

[Means to solve problems]

A monitoring method for a central processing unit according to the present invention in accordance with the above object is provided by a monitoring circuit that is connected to an output terminal of the central processing unit and generates an output after confirming that the signal at the output terminal is not output during a reference time. , a counting means for counting the output of the monitoring circuit, and a timer whose output is started by a predetermined output value of the counting means or an initial output of the monitoring circuit, and whose output is connected to the glue set or Bricent manual power of the counting means. the central processing unit is reset by each output of the monitoring circuit, and the counting means counts a predetermined number of outputs of the monitoring circuit within a set time of the timer circuit to issue an alarm. It is configured to emit.

Here, when the count value of the counting means becomes equal to a predetermined output value, the above-mentioned alarm is outputted, and the alarm output is monitored by the central processing unit connected to the gate that prohibits the setting of the central processing unit. The present invention also applies to methods.

[Effect]

In the method for monitoring a central processing unit according to the present invention, a monitoring circuit (hereinafter referred to as a WDT circuit) is connected to an output terminal of the central processing unit, and it is confirmed that the signal at the output terminal is not output during a reference time. This signal automatically resets the CPU.

The output of the WDT circuit is counted by a counting means, and the counting means is reset or preset by the output of a timer circuit that is started by a predetermined output value of the counting means or the initial output of the monitoring circuit.
After confirming that the signal from the monitoring circuit has been received a predetermined number of times within the set time of the timer circuit, the counting means or matching circuit outputs an output, thereby making it possible to issue an alarm.

[Example] Next, an example embodying the present invention will be described with reference to the attached drawings to provide an understanding of the present invention.

Here, FIG. 1 is a schematic configuration diagram of a control device to which a central processing unit monitoring method according to an embodiment of the present invention is applied, and FIG. 2 is a timing diagram thereof.

As shown in FIG. 1, a control device IO to which a central processing unit monitoring method according to an embodiment of the present invention is applied is a CPU
A WDT circuit 12 connected to the output terminal of the WDT circuit 12, a counter circuit 13 which is an example of a counting means for counting output pulses of the WDT circuit 12, a timer circuit 14 connected to the WDT circuit 12, and the above counter circuit]3 It has a count value cenoting circuit 15 for resetting or presetting the count value of , and an alarm circuit 16 connected to the output of the counter circuit 13 Vε. These will be explained in detail below.

As is well known, the CPU 1 is connected to a ROM 18 in which a program for controlling the CPU II and necessary data is stored, and a RAM 17 which is a volatile memory to store data as necessary when the power is turned on, and transmits and receives signals. The WDT circuit 12 is connected to one of the CPU IIs (single or multiple is possible; however, in the case of multiple, a gate circuit etc. 12 is connected.
Reset (R
ESI) and is configured by a timer (or counter) set to a time longer than the one standard time of the CPUI 1, and when the CPU II is performing normal operation and emitting a predetermined signal from the output terminal, the WDT There is no output from the circuit 12, but if the CPU II goes out of control and no longer generates a signal at the output terminal, the set timer (or counter) will time out or stop counting.
It is designed to generate a predetermined signal pulse that maintains the H level for the time required to reset the CPU II (R 32). In addition, when the control program is started by an interrupt, the above output is connected to the interrupt terminal (NMI terminal).
It may be done manually.

When this WDT circuit 12 generates a signal pulse, the signal passes through the delay circuit 19 and the Nant gate 20 of the open collector output when the other input (ALM) is at H level.
It is connected to the reset terminal of PUII, and the CPUI 1 is reset (RES2).

Here, the reason why the delay circuit 19 is provided is that there is a propagation delay time of the counter circuit 13 (or coincidence circuit), which will be described later, and when the counter circuit finishes counting, the Kr■ signal This is to prevent Rr7 from appearing by applying it to the input terminal of the gate 20 first, and it is also possible to add time to take into consideration noise disappearance.
Alternatively, the number may be determined by considering the number of output bits (maximum count number) of the counter circuit 13.

, the counter circuit 13 which receives the output signal of the WDTI circuit 12 has a common range when its value is set by the count value setting circuit 15, and the output value of the subtracter 30 and the counter circuit 13 An output value matching circuit 21 is provided, and when subtracting 1 with the subtracter 30,
The next value of the counter circuit 13 is detected and the timer circuit 14 is triggered. As a result, when the WDT circuit 12 generates the first signal pulse, the output value of the counter circuit 13 becomes the next value, and the timer circuit 14 is triggered to newly count time.

In the above embodiment, the timer circuit 14 is triggered by a change to the next value, but in the case of a timer circuit with a recovery time, the count value of the counter circuit 13 is triggered by a change to the next value. It is also possible to apply a trigger to the timer circuit 14, and furthermore, it is also possible to configure the above-mentioned timer circuit 14 by directly triggering from the WDT circuit 12 without re-triggering, and in this case as well, the recovery time is shortened. It is preferable not to have any.

The time-up time of this timer circuit 14 is determined by the characteristics of the controlled object, noise environmental conditions, etc.
1 is intermittently runaway due to an extremely large disturbance, within a sufficiently short time that the controlled object will not be destroyed, and moreover, the WDT circuit 12 repeatedly generates signal pulses due to the runaway of the CPU 11, and the counter circuit 13 outputs a predetermined output value. The output of this timer circuit 14 is set to be longer than the time required to fully finish counting up to Connected. Note that the output of the timer circuit 14 remains at H level for a period of time during which the counter circuit 13 can be reset or preset after the set time. Therefore, the operation here is such that the CPU II goes out of control and the WDT circuit 12 generates a pulse signal. Then, the timer circuit 14 starts counting time based on the next value that is input to the counter circuit 13 and is a predetermined output value of the counter circuit 13. However, before the counter circuit 13 has counted the predetermined number of times, the CPU 1 The rampage stopped,
When the signal pulse of the WDT circuit 12 disappears, the counter circuit 13 is reset or preset by the output signal of the timer circuit 14, and the count value becomes a predetermined set value.

On the other hand, if the CPU 1.1 goes out of control and the WDT circuit 12 outputs intermittently, the counter circuit 13 will finish counting before the timer circuit 14 outputs an output, and an alarm signal will be issued.

This situation is shown in FIG. 2, where a is the output signal of the WDT circuit 12, b is the output signal of the timer circuit 14, and C is the CP
d indicates the output signal of the counter circuit 13 (K-M), and the count value setting circuit 15 is set to 3 in the figure.

The self-holding circuit 31 is for holding the output of the counter circuit 13 or the output of the matching circuit with its own signal, and when there is an input to the rπ input, its output (ALM) becomes H level.

The output from the counter circuit 13 (or the output from the minus number circuit) is input to the alarm circuit 16, which can turn off, for example, a buzzer, a warning lamp, or a controlled object that is dangerous if left unattended. circuit, the power-on command (prTJ) of the standby control device (which has the same configuration as the control device 10, and is not shown), and its activation (■π
1) and a circuit for making an interrupt request (7'lgo), and is designed to protect the controlled object if the CPU 14 goes out of control intermittently within a certain period of time.

In FIG. 1, sensor outputs, response signals, etc. from the controlled object 28 are applied to the CPU 1. Also CP
The control output from the UII is sent to the controlled object 28 via a plurality of multiplexer groups 27 (or bus switches, etc.) which are switched by the m signal. At this time, ALM is at H level. When the TV becomes L level, a preset input for making the controlled object 28 safe is applied, or a control output from a standby control device (not shown) is applied.

Further, in FIG. 1, an initial reset circuit 29 is provided, one of which is provided to the Nant gate 23,
On the other hand, cpuz is reset (τ clove 7) via buffers 25 (open collector output) and 26, but this is done to prevent the counter circuit 13 from being reset or preset by m from the Nantes gate 20. It sends a signal in only one direction.

It should be noted that, to further explain here, when ALM occurs due to permanent failure or long-term runaway noise, in the case of everyday electrical appliances, the main power supply can be turned off to ensure safety. However, at that time, the alarm display will also stop, so in order to improve maintenance, etc., it is possible to turn off the main power after displaying the alarm for a certain period of time. Send appropriate control inputs to the controlled object to prevent destruction. Here, it is preferable to keep the power on at all times by backing up the alarm display with a battery.

Systems that require high confidence orbits are equipped with a standby control device as described above, which transfers control when an ALM occurs. When the operator notices the alarm display, press the manual glue switch, etc. and check. 6. If the condition does not recover, perform maintenance as follows. Switch SW shown in Figure 1.
A is turned on, switch SWD is turned off, and the control device 10 is disconnected for repair or testing. If it is normal, the control device 10 is installed, the switch SWD is turned on, and the switch SWA is turned off, and then the control device 10 resumes normal control operation.

Note that it is possible to add several stages of standby control devices in a loop, and it is preferable to leave the standby control devices on standby with the power turned on. ) After resetting the standby control device, it is also possible to issue an interrupt and execute the control program.Furthermore, it is preferable to output an alarm even in the case of - times a runaway.In this case, the output of the WDT circuit 12 is Holding circuit, display output driver, alarm indicator,
A display reset switch, etc. will be added.

In the embodiment, a down counter was used as the counter circuit 13, but an amplifier counter may also be used. In that case, a matching circuit is required between the output of the counter circuit 13 and the counter value setting circuit 15. Then L
The M signal is now output, and an adder is inserted in place of the subtracter 30. In the case of an up counter, the carry signal may be ALM.

Incidentally, even when a down counter is used, a matching circuit can be provided between the counter circuit 13 and the count value setting circuit 15, and the output thereof can be used as the XτV signal.Furthermore, a comparison circuit can be used instead of the matching circuit. It is also possible.

Further, a delay circuit may be provided on the output side of the Nant gate 20, but in that case, the setting time of the timer circuit 14 is made longer.

〔Effect of the invention〕

As is clear from the above description, the method for monitoring a central processing unit according to the present invention is capable of c p
If 'u goes out of control, it is automatically reset so that it can return to normal operation, and an alarm is also set up to prevent the CPU from going out of control and destroying the controlled object due to disturbances that last longer than a specified period. You will be able to produce.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of a central processing unit monitoring method according to an embodiment of the present invention, and FIG. 2 is an operational state diagram thereof. [Explanation of symbols]

Claims (4)

[Claims] (1) A monitoring circuit that is connected to an output terminal of the central processing unit and generates an output after confirming that the signal at the output terminal is not output during the standard time, and a counting means that counts the output of the monitoring circuit. , a timer circuit starting from a predetermined output value of said counting means or an initial output of said monitoring circuit, the output of which is connected to a reset or preset input of said counting means, said individual output of said monitoring circuit A method for monitoring a central processing unit, characterized in that the central processing unit is reset by the above, and the counting means counts a predetermined number of outputs from the monitoring circuit within a set time of the timer circuit to issue an alarm. (2) The method for monitoring a central processing unit according to claim 1, wherein the alarm output is connected to a gate that prohibits resetting the central processing unit. (3) A method for monitoring a central processing unit according to claim 1, wherein the central processing unit is reset by the output of the monitoring circuit via a delay circuit. (4) The method for monitoring a central processing unit according to claim 1, wherein the @NMI@ terminal is used instead of the reset terminal.