JPH0194393A - Electronic musical instrument - Google Patents

Abstract

PURPOSE: To obtain effective performance conditions by applying an address signal and other control signals to a RAM constituting a data register and shortening data writing execution time. CONSTITUTION: A RAM 11 is used for attaining the function of a shift register and data are read out/written from/in an optional storage address. When an optimum address signal ADDRESS and other control signals WCK, WRT are applied to a RAM 11 or the like in an waveform information processing means in accordance with the sort of data and processing time, data are written in an optional time-divided channel and data writing execution time is shortened. Consequently response time to performance in the electronic musical instrument is shortened and effective performance conditions are obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electronic musical instrument with improved data writing processing for time-division channels.

[Conventional technology]

Conventionally, electronic musical instruments having time-division waveform information processing means have used shift registers as data registers.

FIG. 6 is a block diagram showing the basic configuration of an address generation circuit for reading waveform information from the waveform memory of such a conventional electronic musical instrument.

In the figure, the address generation circuit has a current address register 1, a pitch data register 2, and a reproduction flag register 3 in which a current address, pitch data, and reproduction flag are stored, respectively.

In order to write predetermined data into these registers 1, 2, and 3 to the time division channels, start address data, pitch data, and set/set data are sent from a control section (not shown).
Data WB such as reset, selection signals WCA, WPT, and set/reset control signal FSR are provided. Pitch data given from a control section (not shown) and the output of the pitch data register 2 are input to a selector 4, and a selection signal W
Selected by PT and input to pitch data register 2. The selector 4 selects A when the selection signal WPT is "0".
When input is "1", select 8-person power.

The set/reset data and the output of the flag register 3 are given to the set/reset circuit 5, and input to the reproduction flag register 3 after being controlled by the set/reset control signal FSR. The set/reset circuit 5 sets or resets a designated bit only when the set/reset control signal FSR is "1". The outputs of the pitch data register 2 and the reproduction flag register 3 are input to an AND gate 6, and the output of the AND gate 6 and the output of the current address register I are added by a full adder 7. Data WB such as a start address given from a control section (not shown) and the output of the full adder 7 are input to a selector 8,
It is selected by the selection signal WCA and input to the current address register 1.

The selector 8 receives an A input when the selection signal WCA is “0”;
When it is "1", B input is selected. The output of current address register 1 is read address data CA.
It is output to a waveform memory (not shown).

In such a conventional address generation circuit of an electronic musical instrument, when data WB is not written, the output of the current address register 1 is sent to the AND gate 6 which is opened at a predetermined timing in the playback flag register 3 by the full adder 7. After being added to the pitch data from the pitch data register 2 outputted from the pitch data register 2, the normal selection signal WCA is input to the current address register 1 through the selector 8 whose A input is selected when the selection signal WCA is "0". Therefore, when the output of the AND gate 6 is not "0", the current address is incremented by the output value (pinch data) of the AND gate 6.

On the other hand, when writing a new current address, after preparing the data WB, select the B input of the selector 8 by setting the selection signal WCA to "1" at the timing of the desired time division channel. Data WB is input to current address register 1. In addition, the output of the pitch data register 2 is that the normal selection signal WPT is "0".
A manual input is input to the pitch data register 2 through the selected selector 4, and the pitch data value is held. If you want to write new pitch data, after preparing the data WB (pitch data), select the B input of the selector 4 by setting the selection signal WPT to "1" at the timing of the desired time division channel. , the prepared data WB is input to the pitch data register 2. Furthermore, the output of the reproduction flag register 3 is input to a set/reset circuit 5, and normally this set/reset circuit 5 is input to the reproduction flag register 3. The set/reset circuit 5 sets a certain bit (for example, bit 0) of the data WB as a reset designation bit and another bit (for example, bit 1) as a cent designation bit,
Only when the set/reset control signal FSR becomes "1", the set designation bit and the reset designation bit are referenced to cent or reset the input playback flag data. If you want to set or reset the playback flag stored in the playback flag register 3, specify cents or reset using the cent designation bit and reset designation bit of the data WB, and set/reset at the timing of the desired time division channel. By setting the reset control signal FSR to "1", the reproduction flag is set or reset.

[Problem that the invention seeks to solve]

In the conventional address generation circuit for reading waveform information of an electronic musical instrument as described above, the current address register 1,
When writing new data to the pitch data register 2 or setting/resetting the playback flag in the playback flag register 3, it is necessary to wait for the timing of the desired time division channel, which increases the time required to execute the instruction. .

For this reason, it takes a long time for the current address to start the desired operation, resulting in a problem with the response time of the musical instrument.

An object of the present invention is to shorten the response time to performance in an electronic musical instrument and to provide good performance conditions.

[Means for solving problems]

The means of the present invention provides an electronic musical instrument equipped with a waveform information processing means that operates on a plurality of time-division channels, in which the waveform information processing means is a data register for storing data, such as a RAM, which can be read and written to any storage location. It has a storage means, sets at least one writing period and one reading period in this storage means within one time-division channel, and accesses the RAM by optimal address control according to the content of data processing. be.

[For production]

The operation of the means of the invention is as follows. By giving the optimum address signal and other control signals according to the data type and processing time to the storage means such as RAM of the waveform information processing means, data can be written to any time division channel, and the data can be written to any time division channel. Write execution time is reduced.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a waveform information processing section of an electronic musical instrument that implements the function of a shift register using a RAM. In the same figure, RAM (RandomAccess
Memory) 11 is used to realize the function of a shift register, and is a storage means that can read and write to any storage location. The address input signal terminal of this RAMII is connected to a central control unit (not shown).
Address data is supplied from PU), and the terminal of the chip select signal (τ) is grounded. C not shown
The control signal WCKSWRT from the PU is the Nantes gate 1
2, and the output of this Nant gate 12 is input to the RAM
It is input to the write enable signal (WE) input terminal of No. 11. Further, the control signal WRT is RAMII
Output enable signal (TE) terminal and inverter 1
3 is entered. The output of this inverter 13 is input to a control terminal of a tri-state buffer 14. This tri-state buffer 14 has a control terminal of “0”.
” (low level) signal is applied to output the input signal, and a “1” (high level) signal is applied to the gate to have a high impedance state. From the data input/output terminal of RAMII, output data is applied to the output data flip-flop 15 at a predetermined timing to be described later, and data (DATA 0UT) is output in synchronization with the clock CLK applied to the flip-flop 15. . Input data (DATAIN) is input to the input data flip-flop 16, and is input to the RAMII via the tri-state buffer 14 in synchronization with a predetermined clock CLK given to the flip-flop 16 or an interrupt signal at the end of an operation. Input to the output terminal.

An example of the operation of the waveform information processing section of the electronic musical instrument having the above configuration will be described. This waveform information processing unit handles data of AX type,
Data is classified into AY type and AZ type, and processing is performed using different operations for each type of data. Here, the AX type is data that cannot be rewritten (reading, operation, writing), the AY type is data that is rewritten by calculations and the calculation time is relatively short, and the AZ type is data that cannot be rewritten by calculations. This is data that requires a relatively long calculation time.

The control method and operation of each of the AX type, AY type, and AZ type will be explained below with reference to FIGS. 2 to 4. Note that in these figures, operations for time division channel "n" are represented by thick lines. Also, the first half of the time division channel is written (WRITE), and the second half is read (RE).
AD).

FIG. 2 is a timing chart showing the processing operation of AX type data. The time division channels are allocated between the rising edge of the clock CLK and the next rising edge, and the control signal WCK is a signal that becomes "1" approximately in the middle of the first half and the second half of each time division channel, and the control signal WRT is a signal that becomes "1" at approximately the center of the first half and the second half of each time division channel. This is a signal that is normally "0" except at certain times. In Figure 2, when reading first, time division channel "n-1"
In the second half of , address data rnJ is given to RAMII, and at this time, WRT is "0" and Wπ signal is "1",
The Hyakucho signal becomes "0" and the data is finalized with a delay from Ilo to RAMII access time. This I10 signal is applied to the output data flip-flop 15 and output as a DATA OUT signal in synchronization with the clock CLK.

At this time, the tristate buffer 14 is in a high impedance state with "1" being applied to its control terminal. Next, when writing new data, the value of data WA given to the first half of the time division channel of the address signal is determined to the desired time division channel value, and the desired data WB is given as the DATA IN signal. , and set the WRT signal to "1" in the first half of any time-division channel. FIG. 2 shows a case where the WRT signal is set to "1" in the first half of time division channel "n". As a result, when the WCK signal is "1", the WE double signal rlj,
The Oπ signal becomes “1” and the tri-state buffer 14
is opened and data WB is written to RAMII. According to this control method, when writing data WB, there is no need to wait until the timing of a desired time division channel to execute the write, and writing can be executed in any time division channel. Generally, in order to shorten the write execution time, writing is executed in the time-sharing channel that comes first temporally after a write execution command is issued.

FIG. 3 is a timing chart showing the processing operation of AY type data. This process requires a relatively short calculation time, and ends while the Wπ signal reaches "0" in the first half of the time-division channel, as shown in the figure. The read operation is the same as that of the AX type, so a description thereof will be omitted. When rewriting data by calculation, first
The OUT signal is determined during the time-division channel, and calculations are performed on other data that are also determined during the time-division channel, and the results of the calculation are written into the same RAM II again. In order to rewrite this AY type data, the WRT signal becomes a periodic signal that becomes "1" in the first half of each time-divided channel. Therefore, the WE multiplication signal WCK signal and the WRT signal are both "1" and become a periodic signal that is "0" in the interval, and the calculation result data that has already been completed and fixed at the rising edge of the Wπ signal is used as input data. From the flip-flop 16 to the tri-state buffer 14 and back to RA
Written to MII. When writing new data, the writing is executed by preparing the data to be written, waiting for a desired time division channel, and selecting the prepared data instead of the calculation result.

FIG. 4 is a timing chart showing the processing operation of AZ type data. This process takes a relatively long calculation time, and ends in the latter half of the time-division channel, as shown in the figure. The read operation is the same as the AX type and AY type, and the operation to write new data is as follows.
Since it is the same as the AY type, the explanation will be omitted. When rewriting data by calculation, the calculation time for AZ type data is relatively long, and writing cannot be performed within a time division channel like AY type, so the calculation result is transferred to the clock CLK.
The signal is once received by the input data flip-flop 16, which is used as a DATA IN signal. Since it is the time division channel "fi+l" that the calculation result for the time division channel "n" is determined as the DATA IN signal, rnJ is given to the address signal value in the first half of this time division channel "n+1", and the data Writing is performed.

Note that the above operation example shows three types: AX type, AY type, and AZ type, but even if the calculation time is longer than the AZ type, the address can be sent to the time division channel where the calculation result is determined as the DATAIN signal. Similar control is possible by providing a signal value.

FIG. 5 is a timing chart showing another example of the operation of the waveform information processing section of the electronic musical instrument. In the operation examples shown in FIGS. 2 to 4 above, the execution time when newly writing AX type data is shortened, but in the case of AY type data and AZ type data, the timing of the desired time division channel is reduced. had to wait. The operation example shown in FIG. 5 allows this to be performed without waiting for timing, similar to AX type data.

First, the time division channel is divided into three or more, and in addition to periodic reading and writing, sections are provided for writing according to commands. In the example shown in Figure 5, the time-sharing channel is divided into three sections, the first section is for periodic writing based on calculation results, the second section is for writing based on instructions, and the third section is for periodic reading. It is applied. When writing new data, write the desired data as DATAI.
WRT in the second section of any time-sharing channel.
Just set the signal to "1". Periodic reading and writing are similar to the previous example.

As described above, in this embodiment, when the circuit is configured with an integrated circuit, the circuit scale of the RAM, per unit storage capacity, is smaller than that of the shift resist, so the circuit scale of the LSI or the like is reduced. In addition, desired data can be immediately written to a desired time-division channel without waiting for timing, regardless of the data processing method, so the execution time required for data writing is significantly shortened.

Note that the present invention is not limited to the embodiments, as long as the time-division channel is divided into a plurality of sections, and sections for reading and old data are provided in each section. Further, the clock CLK applied to the input data flip-flop 16 may be a sufficiently fast clock or an interrupt signal for completion of calculation.

〔Effect of the invention〕

As explained above, according to the present invention, by configuring the data register with RAM, classifying data by usage method and calculation processing time, and providing address signals and other control signals to the RAM configuring the data register, Since the execution time for data writing can be shortened and the response time to the performance of the electronic musical instrument can be shortened, good performance conditions can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a waveform information processing section of an electronic musical instrument according to an embodiment of the present invention, FIG. 2 is a timing chart showing the processing operation of AX type data according to an embodiment of the present invention, and FIG. FIG. 4 is a timing chart showing a processing operation of AY type data according to an embodiment of the present invention, FIG. 4 is a timing chart showing a processing operation of AZ type data according to an embodiment of the present invention, and FIG. FIG. 6 is a block diagram of an address generation circuit for reading waveform information of a conventional electronic musical instrument. 11...RAM. 12... Nant gate, 13... Inverter, 14... Tri-state buffer, 15... Flip-flop for output data, 16...
Flip-flop for input data. Patent applicant Casio Computer Co., Ltd. LLI ≦ ≦α Figure 2 Figure 3 Figure 6

Claims (1)

[Claims] An electronic musical instrument equipped with waveform information processing means that operates on a plurality of time-division channels, comprising: a storage means for temporarily storing data in a randomly accessible manner in correspondence with each channel; an allocation means for sequentially allocating channel time as processing time for that channel in a time-division manner; reads the data corresponding to the channel allocated by the allocation means from the storage means, and also reads the data of any channel that has been commanded to be changed to the arbitrary channel of the storage means in another interval. a reading control means for writing in a corresponding location; a timing for reading data from the storage means by controlling the reading control means according to the type of data; and a reading control means for writing data to a corresponding location; An electronic musical instrument characterized by comprising: a timing specifying means for specifying the timing of writing to the storage means;