JPH0191551A - Multiplex data link - Google Patents

Abstract

PURPOSE:To correctly inform error notice to all LAN controllers without reducing the data transmission efficiency by adding an error code to a signal outputted based on the OR condition of the error code of the inputted signal and the check of an error check code. CONSTITUTION:Means 404, 405, OR, 407, 408 adding an error code for error notice are provided on a signal outputted based on the OR condition being the confirmation of the production of an error by the check of an error check code and the addition of the error code to inform the production of the error to the inputted signal for each of LAN controllers 30, 41-4n constituting peripheral processor. Thus, after the error production is confirmed by LAN controllers 30, 41-4n, an error code is added to succeeding all signals and the error notice is applied correctly without lowering the data transmission efficiency.

Description

[Detailed Description of the Invention] (Industrial Application Field) This invention enables various sensors and actuators used in various industrial machines, NG machines, automatic guided vehicles, robots, etc. to be integrated into a central processing unit in a controller. Regarding multiplex data links suitable for centralized management, it is particularly important to provide peripheral processing devices that indirectly manage each of the various sensors and actuators mentioned above, and to serially connect these peripheral processing devices in a circular manner via the central processing unit. The present invention relates to implementation of a peripheral processing device configuration and a signal protocol suitable for monitoring the presence or absence of errors between these peripheral processing devices with respect to connected multiple data links.

[Conventional technology]

FIG. 7 shows the overall configuration of the multiplex data link described above.

That is, in this FIG. 7, 10 is a machine controller that centrally controls the target machine as the controller for control, 21 to 2n are the above-mentioned sensors or actuators disposed in each part of the machine, and 30 is LAN arranged in the machine controller 10 as the central processing unit
(local area network) controller, 41
4n is a LAN controller which is arranged as the peripheral processing device corresponding to each of the plurality of sensors or actuators 21 to 2n and relays and processes various data (sensor data or actuator control data) with the LAN controller 30. As mentioned above, in this multiplex data link, the LAN controller 30 as the central processing unit and the LAN controller 4 as the peripheral processing unit are used.
1 to 4n are connected in series in a ring shape in the manner shown in FIG.

Further, FIG. 8 shows an example of a protocol for signals SO to 3n that are transmitted between the respective LAN controllers 30.41 to 4n in such a multiplex data link.

That is, in this example, the signal 5o-sn includes a data string consisting of a string of sensor data indicating the sensor output from each sensor or control data indicating the control content for controlling the drive mode of each actuator, and this data. A start code is arranged in a straight line in the column and has a predetermined logical structure of a plurality of bits (e.g. 8 bits) and indicates the beginning of the data string; ) A stop code that indicates the end of the same data string with a predetermined logical structure (different from the logical structure of the start code), and the above L for searching for the occurrence of an error between each port (between each LAN controller).
and an error check code that is generated in each of the AN controllers and added as a code signal consisting of a predetermined number of bits (for example, 1 bit) immediately after the stop code, and each LAN controller 30. 41 to 4n, the data (
It also knows whether an error has occurred based on the above-mentioned error check code check (by CRC check method, vertical/horizontal parity check method, etc.).

[Problem that the invention seeks to solve]

In such a multiplex data link, it is certainly possible to effectively achieve data exchange and error checking by adopting signals having the above protocol as signals transmitted between the respective LAN controllers. However, when it comes time to confirm the occurrence of an error and notify it to the next-stage LAN controller or the central LAN controller 30, the following steps are performed depending on the various transmission forms that can be adopted for these signals. I was faced with the problems shown below.

Below, based on FIGS. 7 and 8, - as an example, L
The explanation assumes that an error occurs during signal (data) transmission between the AN controller 41 and the LAN controller 42. In addition, the TO shown in FIG.
O-'01. It is assumed that "11-'12°T22." each represents a time.

In this case, for example, the LAN controller 42
After receiving all the signals S1 transmitted from the controller 41, this is sent as the signal S2 to the LAN controller 43.
send to. Therefore, in this case, the LAN controller 42 can reliably check for errors that have occurred between the LAN controller 41 and this LAN controller 42, and the next LAN controller 4
3, it is also possible to take measures such as "stopping signal transmission" or "sending a signal to notify of an error". However, in this case, a data delay corresponding to the time (Tol-To) occurs between all the LAN controllers, and the efficiency of the data link decreases.

(2) When the LAN controller transmits the signals SO to Sn without any time delay, that is, in the eighth example, when the above 6 o'clock clock is set in the relationship -Zj-.

In this case, for example, the LAN controller 42
Before receiving all the signals S1 transmitted from the controller 41, a signal 82(7) is subsequently transmitted to the LAN controller 43. Therefore, in this case, the data delay described above can be reduced, but on the other hand,
When the LAN controller 42 is able to check and confirm the error that occurred at the gate between the controller 41 and this LAN controller 42, the reception of the signal S2 transmitted from this LAN controller 42 to the LAN controller 43 has also been completed. So, in the end, LAN
It is not possible to sufficiently notify the controller 43 and thereafter of the error.

That is, although the efficiency as a data link can be maintained at a high level, there is a high possibility that the sensor data or actuator malfunctions of the sensors or actuators 23 to 2n arranged corresponding to the LAN controller 43 and thereafter will be erroneously reported.

The present invention was made in view of these circumstances, and provides a multiplex data link that can accurately notify an error to a next-stage LAN controller and a central LAN controller without reducing data transmission efficiency as a data link. The purpose is to provide

[Means for solving problems]

In the present invention, each of the LAN controllers constituting the peripheral processing device is provided with an error code for notifying that the occurrence of an error has been confirmed by checking the error check code, and that the error has occurred in the input signal. Means is provided for adding an error code for this error notification to the output signal based on the logical sum condition that the error code is added.

[Operation] As a result, even when signals are transmitted without any time delay at each LAN controller as described above,
After the occurrence of an error is confirmed in the AN controller (peripheral processing '1A1iff) based on the above error check code check, the above is applied to the signals output from all subsequent LAN controllers (peripheral processing units). An error code will be added.This will ensure that error notifications are accurately sent to all subsequent LAN controllers (including the central AN controller) without reducing data transmission efficiency. Become.

〔Example〕

1 to 3 show an embodiment of a multiplex data link according to the present invention.

Figure 1 assumes that the data link has the configuration shown in Figure 7 above, and shows the LA as each peripheral processing device.
A specific example of the configuration of N controllers 41 to 4n is shown. Of course, these LAN controllers 41 to 4n all have the same configuration.

Now, as shown in FIG. 1, these LAN controllers 41 to 4 each receive the @ signal transmitted from the central AN controller 30 or the curved LAN controller and demodulate it as required. a start code detection circuit 402 that detects the start code indicating the head of a data string from the received and demodulated signal with a predetermined logical structure; Stop code detection circuit 40 that detects the stop code indicating the end of the data string
3, and the previous stage based on the error check code (generated and outputted as a code for searching for the presence or absence of an error through the error check code generation circuit 407 of the previous stage LAN controller, which will be described later) in the received demodulated signal. (previous port) and its own stage (own port), and an error check circuit 404 that checks whether an error has occurred between the same stage (previous port) and its own stage (own port), and an error code (based on the detection of error occurrence at the previous stage) that notifies the received demodulated signal of the occurrence of an error. An error code detection circuit 40 that monitors whether an error code (generated and added via an error code addition circuit 408 (described later) of the LAN controller) is added and detects if it is added.
5, an OR circuit OR which takes the logical sum of the error detection output from the error check circuit 404 and the error code detection output from the error code detection circuit 405, and the received demodulated signal (more precisely, the data string of these) and the sensor or A circuit that performs data conversion between the actuators 21 to 2n, and if this is a sensor, generates and outputs sensor data to be transferred from the own stage based on the sensor output of each corresponding sensor, and If this is an actuator, a data conversion circuit 406 generates and outputs a drive signal for driving the corresponding actuator based on control data for the corresponding actuator, and generates a new error check code based on the received demodulated signal. An error check code generation circuit 407 that outputs an error check code, a first switch circuit SW1 that controls opening/closing of input of the received demodulated signal to the error check code generation circuit 407, and a first switch circuit SW1 that generates the error code and generates the error code as necessary (described later). an error code addition circuit/108 for adding the error code (according to the selection by the second switch circuit l5W2) to the received demodulated signal; A second switch circuit that selectively outputs one of the signal (error check code) generated and output from the error check code generation circuit 407 and the signal (error code) output from the error code addition circuit 408 over time. SW2
and a transmitting circuit 4 which modulates the signal selectively output from the second switch circuit SW2 as required and sends it to the next stage LAN controller or the central LAN controller 30.
09, respectively.

Here, when the signal exchange between each LAN controller is performed by electrical communication via metal cables (rice pair cables, coaxial cables, etc.), the receiving circuit 401 includes an impedance matching circuit, a receiving amplifier,
If the configuration includes a demodulation circuit, etc., and the same signal transmission and reception is performed by optical communication via an optical fiber, the configuration includes an optical-to-electrical converter and a demodulation circuit (Manchester demodulation circuit or CM! demodulation circuit, etc.). The configuration is as follows.

On the other hand, in the case where the transmission circuit 409 also transmits and receives signals between the LAN controllers using the electrical communication,
The configuration includes a modulation circuit and a driver circuit, and in the case of optical communication, the configuration includes a modulation circuit and an electro-optical converter.

The error check circuit 404 also operates as described above.
This is a well-known circuit that performs the above error check using an RC check method, a vertical/horizontal parity check method, or the like.

In FIG. 1, for the sake of convenience, a detailed circuit for executing a sequence related to data exchange between the data conversion circuit 406 and the sensors or actuators 21 to 2n is not shown.

FIG. 2 is a timing chart showing an example of the operation of the LAN controller 42 among the LAN controllers 41 to 4n, and hereinafter, with reference to FIG. The signal processing operation will be explained in detail. In addition, in this embodiment, as is clear from FIG.
This method uses a method to transmit signals without causing any interference. Also, here as above, - as an example, LAN
It is assumed that an error occurs during signal transmission between the controller 41 and the LAN controller 42.

Now, suppose that there is a signal transmission from the previous stage LAN controller (LAN controller 41) to the next stage LAN controller (LAN controller 42) in the manner shown in FIG. , in the start code detection circuit 402, as shown in FIG.
The start code of this received signal is detected at the timing shown in b), and the first switch circuit SW1 is switched on (initially off) (see FIG. 2(g)). As a result, the error check code generation circuit 407
starts generating an error check code to be transmitted to the next stage LAN controller (LAN controller 43) based on the input signal (mainly data string).

Note that at this point, the second switch circuit SW2 is maintained in the initial state of terminal 1 manual selection state as shown in FIG. 2(h), and the start code and data string are The signal is applied as it is to the transmitting circuit 409 via the switch circuit SW2, and is transferred and outputted as a signal S2 to the next stage LAN controller (LAN controller 43) through the transmitting circuit 409 (see FIGS. 2(h) and (i)). . During this time, in the data conversion circuit 406, each corresponding sensor or actuator (22
) to perform the above-described data conversion (data generation) operation.

The stop code of the thus transmitted signal is then detected at the timing shown in FIG. 2(C).

When the stop code is detected in this way, the stop code detection circuit 403 switches the first switch circuit SW1 to the initial OFF state and the second switch circuit SW2 to the terminal 2 manual selection state (FIG. 2(C), (
(See (+) and (h)).

In response to this switching of the second switch circuit SW2, the error check code 2 newly generated by the error check code generation circuit 407 is selected from the second switch circuit SW2, following the detected stop code. The signal is output and transferred through the transmitting circuit 409 (see FIG. 2(i)).

In parallel with this, the error check circuit 404
Front stage LAN controller (LAN controller 41)
The error check code (error check code 1) transferred from the server is checked. As a result, if no data error has occurred, no signal will be output from the error check circuit 404, but as assumed here, if the error check code 1 confirms the occurrence of the error, At the same time as this confirmation, an error detection signal which becomes logic "1" level for a short time is outputted from the error check circuit 404 (see FIG. 2(d)). Therefore, during this period (while the error detection signal is being output), the output of the OR circuit OR is also logic "1".
This will be the n level.

The output of this OR circuit OR is the error check code transmission completion signal (see Fig. 2 (i) and (e) ) and is added to the second switch circuit SW2.

The second switch circuit SW2 outputs a logic "0#" signal according to the logic level of the signal applied from the OR circuit OR, on the condition that the transmission completion signal of the generated code from the error check code generation circuit 407 is applied. It is a switch circuit that is controlled to switch to the initial terminal 1 manual selection state if it is at the logic "1" level, and to the terminal 3 manual selection state if it is at the logic "1" level as in this example. In this case, at the same time as the error check code transmission completion signal is issued, this second switch circuit SW2 enters the terminal 3 manual selection state, and the signal transferred and outputted through the transmission circuit 409 has the error check code generated by the error check code generation circuit 407. Generated output error check code (
Following the error check code 2), an error code output from the error code adding circuit 408 is added (see FIGS. 2(h) and (i)).

Thereafter, when the error code adding circuit 408 completes adding the error code, the second switch circuit S
Issues an error code addition completion signal to W2 (second
(see Figures (i) and (f)), the second switch circuit SW
2 is in the initial state of terminal 1 manual selection state (Fig. 2 (h)
)reference).

By the above operation of the LAN controller 42, this L
From the AN controller 42 to the next stage LAN controller 4
An error code indicating that an error has occurred is appropriately added to the signal S2 transferred to the signal S2. The LAN controllers 43 and later detect the added error code through their error code detection circuits 405, and based on this detection, the output of the OR circuit OR when the error check code transmission completion signal is issued is the same as above. The logic level is set to "1n." That is, the signal to which the error code is added is transferred and output from all LAN controllers after the LAN controller 43.

FIG. 3 shows the signals @So, 81, 82, 33, . - This is a summary of the protocol based on the above assumption (an error occurs between the LAN controller 41 and the LAN controller 42) for Sn (see Figure 7).
By repeating the above-described operations in each of the AN controllers 4n to 4n, these AN controllers 41° respond to the sending of the signal SO having the form shown in FIG. 42.43
．． ...From 4n onwards, Fig. 3 (b) and (c
), (d) and (e) and their respective signals 81, 82, 83 . ...3n will be transmitted.

Then, only the output signal @Sn from the final n-th LAN controller 4n is taken into the central LAN controller 30. The machine controller 10 recognizes that an error has occurred in the data link based on the error code added to the signal Sn taken into the LAN controller 30.

As described above, according to this embodiment, even when the signals 5O-8n are transmitted between the LAN controllers without any time delay, that is, the time T added to the protocol shown in FIG. Regarding 0~'n3, these are '00=' 11= ” 21= T31= ” n
Even if it is set in a relationship such as l, the central L
Error notification can be effectively sent to all LAN controllers including the AN controller 30. In addition, more generally, for the above-mentioned time, T11<Tol・“21”12・’31”22°゛.

The error notification method according to this embodiment is effective when at least such a relationship is maintained.

By the way, according to the above embodiment, the central LAN controller 30 (machine controller 10) performs an error code based on the error code added to the signal 3n transmitted and output from the n-th port (n-th stage) LAN controller 4n. Although it is possible to know that an error has occurred in the data link, it is not possible to know in which part this error has occurred.

In view of these points of the above embodiment, FIGS. 4 to 6 show
This figure shows another embodiment of the multiplex data link according to the present invention, in which the central LAN controller 30 can be effectively notified of the location where the above-mentioned error has occurred.

That is, in this embodiment, as with the previous FIG. 1, FIG. 4 assumes that the data link has the configuration shown in FIG. An example of the configuration is shown in Figure 5.
An example of the operation of the LAN controller shown in the figure, and the sixth section
The figures each show an example of a protocol for each transmission signal that is particularly adopted in this embodiment. In this embodiment as well, the assumptions regarding the signal transmission method and error occurrence related to the illustrations in FIG. 5 and Wia diagram are the same as in the previous embodiment. It is assumed that an error occurs during signal transmission between the LAN controller 41 and the LAN controller 42. Furthermore, in FIG. 4, circuits that are the same as those shown in FIG. 1 are designated by the same reference numerals, and redundant explanation will be omitted.

Now, in this embodiment, each LAN controller 41 to 4n
As shown in FIG. 4, the circuit includes a four-man selection switch circuit SW2' as a second switch circuit, and further includes an error port end detection circuit 411 and an error port addition circuit 412.

Of these, the error port addition circuit 412 is connected to the central LAN controller 30 (machine controller 10
) on which the above error occurred (in this example, L
As error port information for identifying the AN controller 42), following the error code, the second
Logic "1" through input terminal 4 of switch circuit SW2'
It is a circuit that adds a level signal for example 1 bit,
After the error port information addition is completed, it operates to issue an error port addition completion signal to the second switch circuit SW2'.

Furthermore, when the error port end detection circuit 411 includes an error code in the signal input to its own port (more precisely, in the demodulated signal received by this reception circuit 401), the error port end detection circuit 411 detects the This is a circuit that is activated based on the detection output of this error code and detects the above-mentioned error port information that is subsequently added to the error code, as well as the break point of this information, that is, the error port information end, and detects the error port information end. Accordingly, it operates to output a detection signal indicating this to the second switch circuit SW2'.

As shown in FIG. 5(j), the second switch circuit SW2' is in the terminal 1 manual selection state in the initial state (in this state, the received demodulated signal is sent out as it is via the transmission circuit 409), and the Stop code detection output (Figure 5 (C)
) is added, the terminal 2 enters the manual selection state (in this state, the error check code generation circuit 407
(The newly generated error check code is sent out via the transmission circuit 409), and the output of the OR circuit OR when the error check code transmission completion signal (see FIG. 5(f)) is added. Based on the logic level, when this is #I logic "0" level (when no error occurs), the terminal is in the initial state of manual selection of one terminal, and the OR output of this OR circuit is also FA9 "1" level. (when the occurrence of an error is confirmed or when an error has already occurred), the terminal 3 enters the manual selection state (in this state, the error code output from the error code addition circuit 408 is sent to the transmission circuit 409). ), the error code addition completion signal (FIG. 5 (0)
)) is added to the error code detection circuit 40
Based on the detection output of 5 (OR circuit OR output), when this is at the logic "0" level, the terminal 4 enters the manual selection state (in this state, the error port information "1" output from the above error port addition circuit 412 is transmitted) 409), and similarly, this OR circuit OR output is the logic “
1" level, the error port end detection circuit enters the initial state where one terminal is manually selected (at this time, the error port information added to the signals up to the previous stage is sent out via the transmission circuit 409). When the above-mentioned detection signal from the error port addition circuit 411 is applied, the terminal 4 enters the manual selection state, and the error port addition completion signal (see FIGS. 5(k) and (h)) is added from the error port addition circuit 412. The selection (switching) operation is programmed in advance so that when the terminal is selected, the terminal returns to the initial one-terminal manual selection state.

Therefore, as in the example here, when an error occurs between the LAN controller 41 and the LAN controller 42 and this is confirmed by the LAN controller 42, the error occurs as shown in the timing chart of FIG. To,
Signal 31 with no error code added (Fig. 5(a)
)), an error code and error port information are added to the input of the signal S2 by the action of each of the circuits described above including the second switch circuit SW2' in the manner shown in FIG. It will be sent to the next LAN controller 43 as a.

Also, as a result, in the LAN controller 43,
The added error code and error port information end are detected in the manner shown by broken lines in FIGS. 5(a) and 5(e), and based on the above-described selection operation of the second switch circuit SW2', as shown in FIG. The signal S3, which is a transmission signal to the next LAN controller 44, is further transmitted in the manner shown in (d).
will be output. By repeating the same process in the LAN controllers after this LAN controller 44, the protocol of the signals 5o-sn transmitted between each LAN controller ends up having the form listed in FIG. 6. is determined.

As in the previous embodiment, only the signal 3n output from the last n-th LAN controller 4n is taken into the central LAN controller 30; however, in this embodiment, the central LAN controller 30 (machine controller 1
0) is an error that occurs in the data link due to the error code added to the signal 3n (see Figure 6(e)) and the error port information of (n-1> bits). The location (port) where the error occurred can also be recognized at the same time.In other words, the machine controller 1
0, in a data link that has nil ports (LAN controllers 41 to 4n) other than the central LAN controller 30, the occurrence of an error is first confirmed by the kth port (the second port in the above example). is added immediately after the above error code (+ to n-)
1) The address k of the port where the occurrence of the error has been confirmed can be known from the bit error port information.

As described above, according to the embodiment shown in FIGS. 4 to 6, even when the signals SO to Sn are transmitted between the similar LAN controllers without any time delay, the central Error notifications can be effectively sent to all LAN controllers including the LAN controller 30, and the central LAN controller 30 (machine controller 10) can also be notified of the location where the error has occurred. .

Note that the configurations of the peripheral LAN controllers 41 to 4n (FIGS. 1 and 4) shown in each of the above embodiments are merely examples, and the protocols shown in FIG. 3 or 6, respectively, may be implemented. It goes without saying that these LAN controllers 41 to 4n may be configured in any other manner as long as they are suitable.

(Effects of the Invention) As explained above, according to this light, (1) it is possible to accurately notify all required LAN controllers of errors without reducing data transmission efficiency as a data link;

(2) Due to the reason (2) above, it becomes possible to effectively prevent false notifications or malfunctions of each sensor or actuator to be managed.

- Since each LAN controller itself as a peripheral processing device does not require any address, etc., all can be shared, and mass production effects can be expected.

■ For the same reason as above ■, when adding, deleting, or replacing sensors or actuators,
There is no need to consider the signal transmission system, and modification of the machine becomes easy.

You can obtain many excellent effects such as.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a specific example of the configuration of each LAN controller that constitutes a peripheral processing device in an embodiment of the multiplex data link according to the present invention, and FIG. 2 shows an example of the operation of the LAN controller shown in FIG. 3 is a schematic diagram showing an example of the protocol of signals transmitted between each LAN controller in the same embodiment, and FIG. 4 is a diagram illustrating a peripheral processing device in another embodiment of the multiplex data link according to the present invention. A block diagram showing a specific configuration example of each LAN controller, FIG. 5 is a block diagram showing a specific configuration example of each LAN controller.
FIG. 6 is a timing chart showing an example of the operation of the N controller, FIG. 6 is a schematic diagram showing an example of the protocol of signals transmitted between each LAN controller in the embodiment shown in FIGS. FIG. 8 is a block diagram showing an overview of the configuration of a multiplex data link to which the invention is applied. FIG. 8 is a schematic diagram showing a transmission signal protocol normally employed in the multiplex data link shown in FIG.

Claims (3)

[Claims] (1) Combine data from multiple sensors or actuators into one
When communicating with and centrally managing one central processing unit, an error check code is sent along with the data to check for the occurrence of an error, corresponding to each of the plurality of sensors or actuators. A peripheral device that inspects the contents of this error check code in conjunction with the input of at least a signal, monitors the presence or absence of an error, and transmits and receives each data to and from each corresponding sensor or actuator, and outputs the signal. In a multiplex data link in which a processing unit is provided and these peripheral processing units are connected in series in a ring via the central processing unit, the occurrence of an error is confirmed in each of the peripheral processing units by checking the error check code. and that an error code for notifying the occurrence of an error is added to the input signal, and means for adding the error code to the output signal based on a logical sum condition. A multiplex data link featuring: (2) Combine data from multiple sensors or actuators into one
When communicating with and centrally managing one central processing unit, an error check code is sent along with the data to check for the occurrence of an error, corresponding to each of the plurality of sensors or actuators. A peripheral device that inspects the contents of this error check code in conjunction with the input of at least a signal, monitors the presence or absence of an error, and transmits and receives each data to and from each corresponding sensor or actuator, and outputs the signal. In a multiple data link in which a processing unit is provided and these peripheral processing units are connected in series in a ring via the central processing unit, the occurrence of an error is confirmed in each of the peripheral processing units by checking the error check code. and that an error code for notifying the occurrence of an error is added to the input signal, means for adding the error code to the output signal based on a logical sum condition; and the central processing unit. and means for further adding error port information to the output signal for identifying the port in which the occurrence of the error has been confirmed. (3) The error port information is a signal of a specific logic in units of 1 bit that is subsequently added to the error code, and after 1 bit is added at the port where the occurrence of the error has been confirmed, The multiplex data link according to claim 2, wherein one bit is added each time the data link passes through the link.