JPH0191479A - Semiconductor light emitting element and its manufacture - Google Patents

Semiconductor light emitting element and its manufacture

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Publication number
JPH0191479A
JPH0191479A JP62248080A JP24808087A JPH0191479A JP H0191479 A JPH0191479 A JP H0191479A JP 62248080 A JP62248080 A JP 62248080A JP 24808087 A JP24808087 A JP 24808087A JP H0191479 A JPH0191479 A JP H0191479A
Authority
JP
Japan
Prior art keywords
layer
absorption layer
light emitting
active layer
absorption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62248080A
Other languages
Japanese (ja)
Inventor
Takashi Tsubota
孝志 坪田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP62248080A priority Critical patent/JPH0191479A/en
Publication of JPH0191479A publication Critical patent/JPH0191479A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To prevent laser oscillation at the time of low temperature or large current, by forming, in a double hetero junction structure body, an absorption layer having energy gap smaller than that of an active layer, and forming thinly a clad layer between the active layer and the absorption layer in thickness equal to or less than 1mum. CONSTITUTION:At least on one side of a double hetero structure body, is arranged an absorption layer 15 whose energy gap is smaller than that of an active layer 9. A clad layer 10 between the active layer 9 and the absorption layer 16 is thinly formed in thickness equal to or less than 1mum. Therefore a light oozing out from the active layer 9 passes through the thin clad layer 10 and reaches the absorption layer 15. Since this light is absorbed by the absorption layer 15, positive feed back of the light does not occur. As a result, laser oscillation becomes hard to occur it the time of low temperature or large current.

Description

【発明の詳細な説明】 −(産業上の利用分野) 本発明は半導体発光素子及びその製造方法に関し、特に
光通信等に用いられる端面発光型発光ダイオード及びそ
の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION - (Industrial Application Field) The present invention relates to a semiconductor light emitting device and a method for manufacturing the same, and more particularly to an edge-emitting type light emitting diode used for optical communication and the like and a method for manufacturing the same.

(従来の技術) 従来、光通信用の光源として主に半導体レーザが挙げら
れる。この半導体レーザは、高出力、単−波長性及び高
応答速度性により長距離の大容量光通信に用いられてい
る。しかしながら半導体レーザは高価格でしかも温度特
性が悪いために短距離の中小容量の光通信には不向きで
、これにはLED%に端面発光型発光ダイオードが代り
に用いられる。この端面発光型発光ダイオードは、半導
体レーザと類似の構造のものが用いられ、発光領域とな
るV溝部の長さだけが短かくされている。
(Prior Art) Conventionally, a semiconductor laser is mainly used as a light source for optical communication. This semiconductor laser is used for long-distance, large-capacity optical communications due to its high output, single wavelength, and high response speed. However, semiconductor lasers are expensive and have poor temperature characteristics, making them unsuitable for short-distance, medium- and small-capacity optical communications, and edge-emitting light emitting diodes are used instead of LEDs for this purpose. This edge-emitting type light-emitting diode has a structure similar to that of a semiconductor laser, and only the length of the V-groove portion serving as the light-emitting region is shortened.

欠如、第4図の工程図を参照して従来の半導体発光素子
の一例の端面発光型発光ダイオードの製造方法について
以下に述べる。まず、第4図(a)に示すように、 Z
nドープで中ヤリャ濃度Np:5XlO”ctIM−3
のP型InP基板CP−InP基板)1上に、液相エピ
タキシャル成長法により、厚さ約1μm 、 7.nド
ーグでキャリヤ濃度Np ニア X 1017cm−3
にP−InPバッファ層2を形成した後、その上に厚さ
約0.5μm。
A method of manufacturing an edge-emitting type light emitting diode, which is an example of a conventional semiconductor light emitting device, will be described below with reference to the process diagram of FIG. First, as shown in Figure 4(a), Z
N-doped with medium concentration Np: 5XlO”ctIM-3
7. A P-type InP substrate (CP-InP substrate) 1 with a thickness of about 1 μm was grown by liquid phase epitaxial growth. Carrier concentration Np near x 1017cm-3 in n-dog
After forming a P-InP buffer layer 2 on it, a thickness of about 0.5 μm is formed thereon.

Snドーグでキャリヤ濃度Nn ”’ 5 X 101
7cm−”にN−1nPブロック層3を形成し、その後
、その上面に厚さ約1.5 ttm 、 Znドーグで
ギヤリヤ濃度Np = s x l□ xt帰−sにP
−InPブロック層4を成長させて形成する@上記3つ
の層を順次にエピタキシャル成長させる時には約600
℃のフンタクト温度で行なう。次に第4図(b)に示す
ように、P−1nPブロック層4の形成直後にCVD法
によシ350℃テSiO,膜5を約1500^厚に膜付
けし、ホ) IJソ工程を経て幅約1μmのストライブ
状のノターンを<oti>方向にホトレジスト膜6で形
成し* 5x02膜5のエツチングマスクを形成する。
Carrier concentration Nn ''' 5 x 101 with Sn dogu
An N-1nP block layer 3 is formed on the top surface with a thickness of about 1.5 ttm and a gear layer concentration Np = s x l□
-InP block layer 4 is grown and formed @ When the above three layers are sequentially epitaxially grown, the thickness of the InP block layer 4 is approximately 600
Carry out at normal temperature of °C. Next, as shown in FIG. 4(b), immediately after the formation of the P-1nP block layer 4, a SiO film 5 is deposited at 350° C. to a thickness of about 1500° by CVD method, and then an IJ process is performed. After that, stripe-like notars with a width of about 1 μm are formed in the <oti> direction using the photoresist film 6, thereby forming an etching mask for the *5×02 film 5.

次に、第4図(c)に示すように、HαとH,PO,の
容積化で3:1の混合液で約2℃においてエツチングを
行い、N−InPブロック層3を貫通するV溝部を形成
する。次に、弗酸によりSin、膜5を除去し、その直
後に第4図(d)に示すように、液相エピタキシャル成
長法により第2回目の液相エピタキシャル成長を行う。
Next, as shown in FIG. 4(c), etching is performed at about 2° C. using a 3:1 mixed solution of Hα, H, and PO to form a V-groove that penetrates the N-InP block layer 3. form. Next, the Sin film 5 is removed using hydrofluoric acid, and immediately thereafter, as shown in FIG. 4(d), a second liquid phase epitaxial growth is performed by a liquid phase epitaxial growth method.

この液相エピタキシャル成長は、厚さ約1μm、キャリ
ヤ濃度Nルミ5 X 1017cm−”の下側クラッド
層としてのP−InPクラッド層8゜λf=1,3μm
(但し、λ?は対応する層のエネルギーギヤツプに相対
応する光の波長である。)、厚さ約0,15/jFFJ
厚1幅約2ttmのP−InGaAsP活性層9゜厚さ
約1.5μm、キャリヤ濃度Nn≧5XIO17個−3
の上側クラッド層としてのN−InPクラッド層10.
厚さ約1 pm 、λf=1,2μmのN−InGaA
sPキャッグ層11を順次層成1させる。次に%N −
InGaA+sPキャップ層11上にAu Ge Ni
電極12を、P−InP基板l側にAu Zn電極13
を各々約3000^厚に形成する。その後、第4図(6
)に示すように骨間を行い、素子の光出力のある両側面
に対し例えばAZtO,膜14をス・9ツタ法にて約2
000λ厚に膜付けし、両端面の反射率を小さくする。
This liquid phase epitaxial growth was performed using a P-InP cladding layer as a lower cladding layer with a thickness of approximately 1 μm and a carrier concentration of Nlumi 5×1017 cm−”.
(However, λ? is the wavelength of light corresponding to the energy gap of the corresponding layer.), thickness approximately 0.15/jFFJ
P-InGaAsP active layer 9° thick, about 2 ttm wide, about 1.5 μm thick, carrier concentration Nn≧5XIO17 -3
N-InP cladding layer 10 as the upper cladding layer.
N-InGaA with a thickness of about 1 pm and λf=1.2 μm
The sP cap layer 11 is sequentially formed. Then %N −
Au Ge Ni on the InGaA+sP cap layer 11
The electrode 12 is placed on the P-InP substrate l side, and the Au Zn electrode 13 is placed on the P-InP substrate l side.
are each formed to a thickness of about 3000^. After that, Figure 4 (6
), the film 14 of, for example, AZtO is coated on both sides of the device where the optical output is located, using the S.9.
The film is applied to a thickness of 000λ to reduce the reflectance of both end faces.

か\る構成の半導体発光素子に対して、 AuZn電極
13をグラス、AuGeNi 11極12をマイナスに
して通電すると、N−InPグロック層3とP−InP
ブロック層4の界面で逆バイアス状態となり、電流はN
−InPブロックJ−3のV溝エツチングされた所だけ
を通って流れ、電流の狭窄ができ、発光再結合して光を
放出する。
When a semiconductor light emitting device having such a configuration is energized with the AuZn electrode 13 made of glass and the AuGeNi 11 electrode 12 made negative, the N-InP Glock layer 3 and the P-InP
A reverse bias state occurs at the interface of the block layer 4, and the current is N
- The current flows only through the V-groove etched portion of the InP block J-3, creating a current constriction, and radiative recombination occurs to emit light.

(発明が解決し、ようとする問題点) しかしながら、以上述べた半導体発光素子及びその製造
方法であっても周囲温度が低くなり半導体発光素子の発
光効率が良くなった場合又は半導体発光素子に流れる電
流が大電流になった場合、反射防止膜としてのM、0.
膜14でなるべく外部に光を射出させるだけではレーザ
発振の抑制力が足シす、レーザ発振を開始してしまい、
半導体レーザのもつ種々の欠点例えば温度特性が悪い等
と同じ上述の欠点全有してしまうと云う問題点がめった
(Problems to be Solved and Attempted by the Invention) However, even with the semiconductor light emitting device and its manufacturing method described above, if the ambient temperature becomes lower and the luminous efficiency of the semiconductor light emitting device improves, or When the current becomes a large current, M, 0.
If only the film 14 allows the light to be emitted to the outside as much as possible, the suppressing power for laser oscillation will be insufficient, and the laser oscillation will start.
The problem is that it has all of the above-mentioned drawbacks, such as the various drawbacks of semiconductor lasers, such as poor temperature characteristics.

本発明は、以上述べた反射防止膜だけではレーザ発振の
抑制力が不充分である問題点を咋去し、低温や大電流で
もレーザ発振しない安定性の優れた半導体発光素子及び
その製造方法を提供することを目的とする。
The present invention eliminates the problem that the antireflection film alone has insufficient suppressive power for laser oscillation, and provides a highly stable semiconductor light emitting device that does not oscillate even at low temperatures or large currents, and a method for manufacturing the same. The purpose is to provide.

(問題点を解決するための手段) 本発明に係る半導体発光素子は、ダブルヘテロ接合構造
体の少なくとも一側に活性層よりエネルギーギヤツプの
小さな吸収層を設け、活性層と吸収層との間のクラッド
層を略1μm以下に薄くしたものである。
(Means for Solving the Problems) The semiconductor light emitting device according to the present invention is provided with an absorption layer having a smaller energy gap than the active layer on at least one side of the double heterojunction structure, so that the active layer and the absorption layer are connected to each other. The cladding layer in between is thinned to approximately 1 μm or less.

本発明に係る半導体発光素子の製造方法は、半導体基板
上に電流ブロック層と電流ブロック層を貫通するV溝を
形成し、■溝を埋めるようにしてダブルヘテロ接合構造
体とこれの少なくとも一側に設けられる吸収層を順次に
成長させ、吸収層と接触するクラッド層の厚さを略1μ
m以下に小さくし、次にキャップ層を成長させ、この後
に半導体基板側及びキャップ層側に各々合金属を形成す
るようにしたものである。
A method for manufacturing a semiconductor light emitting device according to the present invention includes forming a current blocking layer and a V-groove penetrating the current blocking layer on a semiconductor substrate, and forming a double heterojunction structure and at least one side of the double heterojunction structure by filling the grooves. The thickness of the cladding layer in contact with the absorption layer is approximately 1 μm by sequentially growing the absorption layer provided on the
m or less, then a cap layer is grown, and then an alloy metal is formed on the semiconductor substrate side and the cap layer side, respectively.

(作用) 本発明によれば活性層からにじみ出之光が薄いクラッド
層を通過して吸収層に到達し、吸収層で吸収されるため
に光の正のフィード/?ツクが起こらず、低温時や大電
流時でもレーザ発振が起きにくい。
(Function) According to the present invention, light leaking from the active layer passes through the thin cladding layer, reaches the absorption layer, and is absorbed by the absorption layer, resulting in a positive feed/? No damage occurs, and laser oscillation is less likely to occur even at low temperatures or at high currents.

(実施例) 以下、本発明の実施例を図面に基づいて詳細に説明する
。第1図は本発明の一実施例に係る工程図でおる。第1
図において、第4図と同符号の部分は従来のものと同じ
ものであり、第1図(IL)〜第1図(c)に示す各工
程は、第4図(a)〜第4図(c)の従来の各工程に対
応し、■溝7を形成した後に810゜膜5を除去する迄
の工程は従来と同じであるのでその説明を省略する。第
2図にチップ外観の概略を示すように、■溝7は厚さり
、=100μmのチップの全長り、=350μmに対し
、Ls= l 50 ttmの長さだけ設けている。
(Example) Hereinafter, an example of the present invention will be described in detail based on the drawings. FIG. 1 is a process diagram according to an embodiment of the present invention. 1st
In the figure, the parts with the same symbols as in FIG. 4 are the same as those in the conventional one, and each process shown in FIG. 1 (IL) to FIG. Corresponding to the conventional steps in (c), the steps from (1) to removing the 810.degree. film 5 after forming the grooves 7 are the same as the conventional steps, so their explanation will be omitted. As shown in FIG. 2, the chip appearance is schematically shown. The groove 7 is thick and has a length of Ls=l 50 ttm with respect to the total length of the chip, which is 100 μm, and is 350 μm.

次に第1図(d)に示すように、コンタクタ温度的59
5℃において第2回目の液相エピタキシャル成長を行う
。この液相エピタキシャル成長は、V溝7を埋めるよう
にして、厚さ約1μm、キャリヤ濃度Nルミ7 X 1
0 ” an−”のP−InPクラッド層8.厚さ約0
.15μm、λP=1.3μmのP−InGaAsP活
性層9゜厚さ約0.2μm、キャリヤ濃度Nn≧7X1
017側−3ON−InPクラッド層10.厚さ約0.
5pm、λ2=1.5μmの上側吸収層としてのN−I
nGaAsP吸収層15、厚さ約1 jam 、λf=
1.211mのN−1nGaAsPキャップ層1lt−
順次に成長させる。なお%P−InGaAsP活性層9
の形成位置は、V溝7の内部でN−InPブロック層3
の間取上の位置にすればよい。
Next, as shown in FIG. 1(d), the contactor temperature 59
A second liquid phase epitaxial growth is performed at 5°C. This liquid phase epitaxial growth fills the V-groove 7 to a thickness of approximately 1 μm and a carrier concentration of Nlumi 7×1.
0 "an-" P-InP cladding layer 8. Thickness approx. 0
.. 15 μm, λP=1.3 μm P-InGaAsP active layer 9° thickness about 0.2 μm, carrier concentration Nn≧7X1
017 side-3ON-InP cladding layer 10. Thickness approximately 0.
N-I as upper absorption layer with 5pm, λ2=1.5μm
nGaAsP absorption layer 15, thickness approximately 1 jam, λf=
1.211m of N-1nGaAsP cap layer 1lt-
Grow sequentially. Note that %P-InGaAsP active layer 9
The formation position of the N-InP block layer 3 is inside the V-groove 7.
The location should be on the floor plan.

又、本実施例ではP−InPクラッド層8からN−In
GaAsP吸収膚15迄吸収管1溝迄を埋めるように設
けている。その後、抵抗加熱型真空蒸着によりN−In
GaAsPキャッグ層11側にAu Ge Ni電極1
2f、3000^厚、P−InP基板1側にAu Zn
電極13を3000λ厚に膜付けし、窒素雰囲気中で約
420℃の熱処理を行って合金Nを形成する。後の工程
は骨間等を行って素子化するが公知なのでその説明を省
略する。
Further, in this embodiment, N-InP is formed from the P-InP cladding layer 8.
The GaAsP absorption skin 15 is provided so as to fill up to one groove of the absorption tube. After that, N-In was deposited by resistance heating vacuum evaporation.
Au Ge Ni electrode 1 on the GaAsP cap layer 11 side
2f, 3000^ thickness, Au Zn on P-InP substrate 1 side
The electrode 13 is deposited to a thickness of 3000λ and heat treated at about 420° C. in a nitrogen atmosphere to form alloy N. The subsequent step is to perform interosseous surgery to form elements, but since this is well known, the explanation thereof will be omitted.

次に動作について説明する。通電により P−InGa
AsP活性層9に従来と同様に光が発生する。
Next, the operation will be explained. When energized, P-InGa
Light is generated in the AsP active layer 9 as in the conventional case.

この光の一部は比較的に薄く形成されたN−InPクラ
ッド層10ににじみ出てN−InGaAsP吸収層15
に到達する。N−InGaAsP吸収層15はP−In
GaAsP 活性N 9のエネルギーギャップより低い
エネルギーギャップを有しており、その到達した光を吸
収してしまう。これによりP−InGaAsP活性層9
を含むダブルヘテロ接合構造体内でのレーザ発振が抑制
される。
A part of this light oozes out to the N-InP cladding layer 10 formed relatively thin and is transmitted to the N-InGaAsP absorption layer 15.
reach. The N-InGaAsP absorption layer 15 is made of P-In
GaAsP has an energy gap lower than that of active N 9 and absorbs the light that reaches it. As a result, the P-InGaAsP active layer 9
Laser oscillation within the double heterojunction structure containing the double heterojunction structure is suppressed.

第3図は本発明の他の一実施例を示す工程図で、第1図
の和尚部分には同符号を付しである。構造的にはP −
InGaAs P活性層9をP−InPクラッド層8と
N−InPクラッド層10とで挾んだダブルヘテロ接合
構造体をN−InGaAsP吸収層15と下側吸収層と
してのP−InGaAsP吸収層16とで挾んだもので
らる。製法は、第3図(a)に示したようにV溝7全形
成する迄は第1の実施例と同じで、第3図(b)K示し
たように第1の実施例と異なる点はP−1nPクラッド
層8を工ぎタキシャル成長する直前にP−InGaAs
P e、収層16をエピタキシャル成長させる。その他
の工程は第1の実施例と同じであるが、P−InGaA
sP吸収層16は厚さ約0.Sμm、  λt=1.5
Amに、P−InPクラッド層8は厚さ約0.1μmK
 、 P −InGaAsP活性層9はλF=1,3/
Jmi厚さ約0.15μm、幅約2Amに、N−InP
クラッド層10は厚さ約0.1μmに、 N−InGa
AsP吸収層15はλ?=1.5/J?tl、厚さ約0
.5μm、 N −InGaAsPキャップ層11はλ
F=1.2μm、厚さ約1μmに形成される。
FIG. 3 is a process diagram showing another embodiment of the present invention, in which the priest portions in FIG. 1 are given the same reference numerals. Structurally P −
A double heterojunction structure in which an InGaAsP active layer 9 is sandwiched between a P-InP cladding layer 8 and an N-InP cladding layer 10 is used as an N-InGaAsP absorption layer 15 and a P-InGaAsP absorption layer 16 as a lower absorption layer. You can get something sandwiched between them. The manufacturing method is the same as the first embodiment until the entire V-groove 7 is formed as shown in FIG. 3(a), and the difference from the first embodiment is as shown in FIG. 3(b)K. Immediately before forming the P-1nP cladding layer 8 and taxially growing the P-InGaAs
Pe, epitaxially grow the condensation layer 16. Other steps are the same as in the first example, except that P-InGaA
The sP absorption layer 16 has a thickness of approximately 0.0 mm. Sμm, λt=1.5
Am, the P-InP cladding layer 8 has a thickness of about 0.1 μmK.
, P-InGaAsP active layer 9 has λF=1,3/
Jmi thickness of about 0.15μm, width of about 2Am, N-InP
The cladding layer 10 has a thickness of approximately 0.1 μm and is made of N-InGa.
AsP absorption layer 15 is λ? =1.5/J? tl, thickness approximately 0
.. 5 μm, N-InGaAsP cap layer 11 is λ
It is formed to have F=1.2 μm and a thickness of about 1 μm.

又、P−InPクラッド層8の成長においては、コンタ
クト時の過飽和度が14℃以上の状態で行う。
Further, the growth of the P-InP cladding layer 8 is performed in a state where the degree of supersaturation at the time of contact is 14° C. or higher.

これにより、  P−InGaAsP吸収層16のメル
トバックを防ぐことができる。本実施例では吸収層を2
層設けているためにより効果的に光を吸収して発振を抑
制する。
Thereby, meltback of the P-InGaAsP absorption layer 16 can be prevented. In this example, two absorbent layers are used.
The layered structure absorbs light more effectively and suppresses oscillation.

〔発明の効果〕〔Effect of the invention〕

以上、詳細に説明したように本発明によれば、ダブルヘ
テロ接合構造体の少なくとも一側に活性層のエネルギー
ギャップより小さいエネルギーギャップを有する吸収層
を形成し、活性層と吸収層間のクラッド層を薄く1μm
以下に形成するようKしたので、活性層から上下方向に
もれた光の一部が吸収層に吸収されるためにレーザ発振
が起こりにく\、半導体発光素子の安定化の向上が期待
出来る。
As described above in detail, according to the present invention, an absorption layer having an energy gap smaller than the energy gap of the active layer is formed on at least one side of the double heterojunction structure, and a cladding layer between the active layer and the absorption layer is formed. 1μm thin
Since K is formed as below, a part of the light leaking from the active layer in the vertical direction is absorbed by the absorption layer, making it difficult for laser oscillation to occur, and it is expected that the stability of the semiconductor light emitting device will be improved. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例による半導体発光素子の工程
図、第2図は上記一実施例によるチップ外観の概略図、
第3図は本発明の他の実施例による半導体発光素子の工
程図、第4図は従来の半導体発光素子の工程図である。 図中、l・・・P−InP基板、3・・・N−InPブ
ロック層、4・・・P−InPブロック層、7・・・V
S、S・・・P−InPクラッド層、9 =・P −I
nGaAsP活性層、1O−−−N−InPクラッド層
、l 1 =−N −InGaAsPキャッグ層、l 
2− AuGeNi電極、13 ・= AuZn電極、
15−N −InGaAsP吸収層、l 6−P −I
nGaAsP吸収層・ 第1図 一飯砲停止n+、、7゛外寮ffi/)、R,ala第
2図 第3図 ノiゴ払尋θσ)きト≦繭:イ本発光t)sフエf、i
tシ第4図
FIG. 1 is a process diagram of a semiconductor light emitting device according to an embodiment of the present invention, FIG. 2 is a schematic diagram of the appearance of a chip according to the above embodiment,
FIG. 3 is a process diagram of a semiconductor light emitting device according to another embodiment of the present invention, and FIG. 4 is a process diagram of a conventional semiconductor light emitting device. In the figure, 1...P-InP substrate, 3...N-InP block layer, 4...P-InP block layer, 7...V
S, S...P-InP cladding layer, 9 = P-I
nGaAsP active layer, 1O---N-InP cladding layer, l 1 =-N-InGaAsP cap layer, l
2- AuGeNi electrode, 13 ・= AuZn electrode,
15-N-InGaAsP absorption layer, l6-P-I
nGaAsP absorption layer ・ Fig. 1 One-shot stop n+,,7゛outerial ffi/), R, ala Fig. 2 Fig. 3 f,i
Figure 4

Claims (3)

【特許請求の範囲】[Claims] (1)活性層を両クラッド層で挾んだダブルヘテロ接合
構造体を有する半導体発光素子において、ダブルヘテロ
接合構造体の少なくとも一側に活性層よりエネルギーギ
ヤツプの小さな吸収層を設け、 上記活性層と吸収層とで挾まれたクラッド層の厚さを略
1μm以下にしたことを特徴とする半導体発光素子。
(1) In a semiconductor light emitting device having a double heterojunction structure in which an active layer is sandwiched between both cladding layers, an absorption layer having a smaller energy gap than the active layer is provided on at least one side of the double heterojunction structure, and the above-mentioned A semiconductor light emitting device characterized in that a cladding layer sandwiched between an active layer and an absorption layer has a thickness of approximately 1 μm or less.
(2)半導体基板上に電流ブロック層を形成する第1工
程と、 上記電流ブロック層を貫通するV溝を形成する第2工程
と、 上記V溝を埋めるようにして下側クラッド層、活性層、
上側クラッド層及び上記下側クラッド層下と上側クラッ
ド層上の少なくとも一方に設けられ、上記活性層よりエ
ネルギーギャップの小さい吸収層を順次エピタキシャル
成長させ、上記活性層と吸収層で挾まれるクラッド層を
略1μm以下に形成すると共にキヤツプ層をエピタキシ
ャル成長させる第3工程と、 上記半導体基板側及びキヤツプ層側に各々合金層を形成
する第4工程とを備えた半導体発光素子の製造方法。
(2) a first step of forming a current blocking layer on the semiconductor substrate; a second step of forming a V-groove penetrating the current blocking layer; a lower cladding layer and an active layer filling the V-groove; ,
An upper cladding layer and an absorption layer provided under at least one of the lower cladding layer and the upper cladding layer and having a smaller energy gap than the active layer are sequentially grown epitaxially, and the cladding layer sandwiched between the active layer and the absorption layer is formed. A method for manufacturing a semiconductor light emitting device, comprising: a third step of forming an alloy layer to a thickness of approximately 1 μm or less and epitaxially growing a cap layer; and a fourth step of forming an alloy layer on the semiconductor substrate side and the cap layer side, respectively.
(3)上記下側吸収層の次に上記下側クラッド層を液相
エピタキシャル成長させて形成する場合、上記下側クラ
ッド層の融液の過飽和度を上記下側吸収層のメルトパッ
クを防ぐ所定温度以上にすることを特徴とする特許請求
の範囲第2項記載の半導体発光素子の製造方法。
(3) When the lower cladding layer is formed next to the lower absorption layer by liquid phase epitaxial growth, the degree of supersaturation of the melt in the lower cladding layer is set at a predetermined temperature that prevents melt-packing of the lower absorption layer. A method for manufacturing a semiconductor light emitting device according to claim 2, characterized in that the above steps are performed.
JP62248080A 1987-10-02 1987-10-02 Semiconductor light emitting element and its manufacture Pending JPH0191479A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62248080A JPH0191479A (en) 1987-10-02 1987-10-02 Semiconductor light emitting element and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62248080A JPH0191479A (en) 1987-10-02 1987-10-02 Semiconductor light emitting element and its manufacture

Publications (1)

Publication Number Publication Date
JPH0191479A true JPH0191479A (en) 1989-04-11

Family

ID=17172909

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62248080A Pending JPH0191479A (en) 1987-10-02 1987-10-02 Semiconductor light emitting element and its manufacture

Country Status (1)

Country Link
JP (1) JPH0191479A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6050827A (en) * 1982-12-29 2000-04-18 Sharp Kabushiki Kaishi Method of manufacturing a thin-film transistor with reinforced drain and source electrodes
JP4856280B1 (en) * 2011-06-03 2012-01-18 等 川上 scissors

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6050827A (en) * 1982-12-29 2000-04-18 Sharp Kabushiki Kaishi Method of manufacturing a thin-film transistor with reinforced drain and source electrodes
JP4856280B1 (en) * 2011-06-03 2012-01-18 等 川上 scissors

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