JPH01829A - Differential encoding error correction device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a differential coding (DPCM) decoder device, and particularly relates to an error correction device when an error occurs during recording, reproduction, or transmission. .

(Prior art) The most significant bit (MSB) of a differentially encoded (DPCM) signal
) is l'lsB of the linear pulse coded modulation (PCM) signal
, the positive differential coefficient at the sample point of the original signal (
(increase) and negative (decrease) signs), and there is no prior art that utilizes this information for error correction.

(Problems to be Solved by the Invention) Unlike linear PCM, when an error occurs in the process of recording, reproducing, and transmitting DPC1 words, the generated error propagates to subsequent signals. In particular, since the MSB of the signal is a bit that indicates an increase or decrease in the difference value, an error will have a large effect on the decoded signal. As a countermeasure, MS
It is possible to use a strong correction code only for B, but
It is often inappropriate if storage capacity or transmission capacity is limited.

Therefore, an object of the present invention is to detect and correct errors in the MSB during recording/reproduction or decoding on the receiving side of transmission, by using information held by the MSB of the DPCH, without adding a new correction code. The present invention aims to provide a differential encoding error correction device that can perform the following steps.

(Means for solving the problem) In order to achieve this object, the differential encoding error correction device of the present invention provides a device for decoding a differentially encoded signal, in which when fs is the sampling frequency, the original signal is to fs
the difference code to be decoded only when it is confirmed by the detecting means that no frequency component of fs/4 or higher is included; 1, 0, 1. or "0, 1.OJ" of the continuous 3-bit pattern of the most significant bit of the signal is corrected to "1, l, IJ, "0, o, o, respectively It is characterized by this.

(Embodiments) The apparatus of the present invention will be described in detail below by way of embodiments with reference to the accompanying drawings. Before going into the description of the embodiments, in order to facilitate understanding of the present invention, the principle of error correction will be explained.

FIG. 2 shows a diagram for explaining the error correction principle of the present invention.

The analog signal 11 is subjected to differential pulse sign ratio modification 8m (DPCM) at a sampling frequency fs. The MSB of this time difference signal indicates an increase or decrease in the difference value. This is r
□ is defined as an increase, and "1" is defined as a decrease.

At this time, if the frequency component included in the original signal is fs74 or less, the MSB value should have at least two successive values of "0" or "1," so the receiving side receives three consecutive difference signals. If the MSB of ``0, 1. o,oJ.

An example of this error pattern is shown by MSB (El) in FIG. " is corrected to "1". However, if the error occurs at the MSB (E2) error bit 15 r OJ in FIG. 2, the error cannot be detected.

FIG. 1 shows a basic circuit diagram of the device of the present invention.

Using 1-sample delay elements 1 (DI) and 2 (nz), three consecutive MSB values are converted to comparator 3 (
CI) and 4 (Cz). SW5 is normally on the a side, and SW8 is closed only when the frequency information or frequency component detection circuit 9, which will be described later, detects that the original signal does not contain frequency components of fs74 or higher. When C2 detects the error patterns "0, 1.OJ" and "1, O, IJ, it immediately goes to the b side and inverts the sign of the second MSB to correct the error bit.

Then, with the next sampling clock, SW5 returns to the a side and begins detecting the next error pattern.

The operation of the apparatus of the present invention has been explained above, and a method for efficiently and accurately using the error correction circuit shown in FIG. 1 in combination with a transmission system will be described in detail below.

First, a method of error correction using frequency information of the original analog signal will be explained.

DPCM (The message is divided into blocks of a certain length of time on the transmitting side, for example, 1 block is about 1 m5ec, and it is determined whether there is a frequency component of f, /4 or more in the block, that is, "0, 1.OJ," Whether a pattern of 1, O, or IJ exists or not is multiplexed into the above-mentioned DPCM signal by using a 1-bit control code per block as frequency information.For example, when a component of fJ4 or higher is present, it is "1", and when it is not present, it is multiplexed. If the frequency information detection circuit 9 is provided on the receiving side and the SW 8 is closed by the output of the detection circuit 9 only when the frequency information bit is "0", erroneous correction can be prevented. Can be done.

Next, a method of performing error correction without using the above-mentioned frequency information will be described.

In digital recording, reproduction, and transmission, since data is protected by adding a correction code in most cases, the device of the present invention is used in combination with error detection information. In other words, when all errors occur (in a state where no errors occur, F is added to the original signal)
, 74 or more frequency components are included, the operation of the apparatus of the present invention is stopped, and the apparatus of the present invention is operated only when an error occurs and is detected.

Further, by constantly operating the device of the present invention when the error rate exceeds a certain value, a double correction function is provided in case there is a mistake in error detection using the correction code.

If the original signal contains frequency components of F, 74 or higher, the three consecutive MSBs are N, O, IJ or "0".
, 1. OJ, and there is a possibility that the receiving side will erroneously detect this as an error pattern. As a countermeasure against this problem, there is a method in which the receiving side determines that this is a signal with originally high frequency components and stops making corrections in a section where MSB inversions occur continuously. - For example, when an error pattern is detected continuously on the receiving side, that is, consecutive MSB r
A, B.

There is C, DJ, rA, B, CJ and rB, C1D.”
If both are error patterns, it is assumed that there is a high possibility that the original signal is a signal with a frequency component of F, 74 or higher, rather than a code error, and the probability of incorrect correction is reduced by stopping correction. Can be done.

FIG. 3 shows an embodiment of the apparatus of the present invention as a concrete implementation circuit. Even if an error pattern is detected by the comparators 3 and 4, no correction is made immediately, and two consecutive patterns are observed by the 1-sample delay element 6 (C3). If two non-consecutive error patterns are detected, the M
Correction of SB is performed. If an error pattern is detected twice consecutively, the NAND gate will have a zero output and the 2
AND gates and l sample delay element 7 (C4
), two consecutive corrections are prohibited.

(Effects of the Invention) As described above, by using the device of the present invention, for example, a control signal of only 1 bit/block can be transmitted as frequency information from the transmitting side to the receiving side, or an appropriate control signal can be sent to the receiving side. By simply providing a frequency component detection means, it is possible to greatly improve errors in the MSB of differentially encoded signals, which have the greatest effect on received signals during recording/reproduction or transmission. A corrective effect can be obtained.

[Brief explanation of the drawing]

FIG. 1 shows a principle circuit diagram related to the device of the present invention, FIG. 2 shows a diagram for explaining the error correction principle of the present invention, and FIG. 3 shows an embodiment of the present invention. The circuit diagram for this is shown. 1.2, 6.7...1 sample delay element 3.4...
3-bit comparator 5.8...switch

Claims (1)

[Claims] 1. In a device that decodes a differentially encoded signal, when the device uses f_s as the sampling frequency, the original signal has f_
A means for detecting whether a frequency component of s/4 or higher is included, and the difference is to be decoded only when it is confirmed by the detecting means that a frequency component of f_s/4 or higher is not included. "1, 0, 1" or "0, 1, 0" of the consecutive 3-bit pattern of the most significant bit of the encoded signal
'' to ``1, 1, 1'' and ``0, 0, 0'', respectively.