JPH0181794U - - Google Patents
Info
- Publication number
- JPH0181794U JPH0181794U JP1987177477U JP17747787U JPH0181794U JP H0181794 U JPH0181794 U JP H0181794U JP 1987177477 U JP1987177477 U JP 1987177477U JP 17747787 U JP17747787 U JP 17747787U JP H0181794 U JPH0181794 U JP H0181794U
- Authority
- JP
- Japan
- Prior art keywords
- processing unit
- central processing
- memory
- write
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Information Transfer Systems (AREA)
- Dram (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987177477U JPH0181794U (en:Method) | 1987-11-24 | 1987-11-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987177477U JPH0181794U (en:Method) | 1987-11-24 | 1987-11-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0181794U true JPH0181794U (en:Method) | 1989-05-31 |
Family
ID=31469139
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987177477U Pending JPH0181794U (en:Method) | 1987-11-24 | 1987-11-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0181794U (en:Method) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7203809B2 (en) | 1994-01-21 | 2007-04-10 | Renesas Technology Corp. | Data transfer control method, and peripheral circuit, data processor and processing system for the method |
-
1987
- 1987-11-24 JP JP1987177477U patent/JPH0181794U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7203809B2 (en) | 1994-01-21 | 2007-04-10 | Renesas Technology Corp. | Data transfer control method, and peripheral circuit, data processor and processing system for the method |
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