JPH01759A - Bidirectional control rectifier semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention (Industrial Application Field) The present invention relates to a bidirectionally controlled rectifying semiconductor device such as a triac, and particularly relates to an improvement for achieving higher sensitivity.

(Prior Art) A triac, which is a type of bidirectionally controlled rectifying semiconductor device, has conventionally had a cross-sectional structure as shown in FIG. In the figure, 40 is an N-type substrate, 41 and 42 are P-type layers, and 4
3, 44, and 45 are N-type layers, respectively.

On the front surface, an electrode T1 is formed continuously on the surfaces of the P-type layer 41 and the N-type layer 43, and a gate electrode G is continuously formed on the surfaces of the N-type layer 44 and the P-type layer 41, and further on the entire back surface. The electrode T2 is formed.

This triac has a general silice gate structure formed by a gate electrode G and a P-type layer 41 below it, and an N-type layer 43 . NPN l-run lister structure consisting of a P-type layer 41 and an N-type substrate 40, an N-type layer 44, and a P-type layer 4
1 and an NPN transistor structure consisting of an N-type substrate 40.
The type layer 44 and the P type layer 41 form a junction gate structure.

By the way, there are I, n, III, and IV modes for turning on a triac having such a structure. ■Mode utilizes the gate structure of the general thyristor described above, and is turned on by applying a positive trigger to the gate electrode G when the electrode T1 has negative polarity and the electrode T2 has positive polarity. There is. Mode (2) utilizes the above-mentioned junction gate structure, and is turned on by applying a negative trigger to the gate electrode G when the electrode T1 is of negative polarity and the electrode T2 is of positive polarity. ■The mode uses the remote gate structure described above, and the electrode T
It is turned on by applying a trigger of negative polarity to the gate electrode G when the electrode T1 has positive polarity and the electrode T2 has negative polarity. Furthermore, mode (2) utilizes the remote gate structure described above, and is turned on by applying a positive trigger to the gate electrode G when the electrode T1 is of positive polarity and the electrode T2 is of negative polarity.

By the way, in order to achieve high gate sensitivity with a conventional triac, it is necessary to reduce the reactive current component that flows to the surface of the P-type base made of the P-type layer 41 and does not contribute as an injection current. For this purpose, measures are used such as lowering the impurity concentration on the surface of the P-type layer and forming a wall of an N-type diffusion layer in the P-type layer 41 to prevent the flow of current.

However, no matter which method is used, there is a trade-off between gate sensitivity and other main characteristics; for example, increasing gate sensitivity reduces dv/dt resistance, worsens high-temperature characteristics, etc. The negative effects of this occur. Also,
Due to the operating principle of the triac, it is essential that the N-type emitter made of the N-type layer 43 has a shorted structure, so there is a limit to how high the sensitivity can be achieved by controlling diffusion.

For this reason, conventional triacs have a drawback in that it is difficult to manufacture triacs with gate sensitivity to the extent that they can be directly driven by the output of an IC (semiconductor integrated circuit).

(Problems to be Solved by the Invention) In this way, in the conventional bidirectional control rectifier semiconductor device, the dv/
A drawback is that it is difficult to increase gate sensitivity without impairing characteristics such as dt tolerance. Therefore, this invention
It is an object of the present invention to provide a bidirectionally controlled rectifying semiconductor device that can increase gate sensitivity without impairing characteristics such as v/dt tolerance.

[Structure of the Invention] (Means for Solving the Problems) A bidirectionally controlled rectifying semiconductor device of the present invention includes a first conductive layer of a first conductivity type and a first conductive layer separated from each other on one surface of the first conductive layer. second, third and fourth conductive layers of a second conductivity type provided in a surface region of the second conductivity layer; second and fifth conductive layers of a first conductivity type provided in a surface region of the second conductivity layer; and the third conductive layer. a sixth conductive layer of the first conductivity type provided on the surface region of the fourth conductive layer; a seventh conductive layer of the first conductivity type provided on the surface region of the fourth conductive layer; The 81st conductivity type of the second conductivity type provided in
, i;/a conductive layer, a ninth conductive layer of the first conductivity type provided in the surface area of the eighth conductive layer, and a ninth conductive layer provided so as to continuously cover the surfaces of the second and fifth conductive layers. a first electrode,
a second electrode connected to each of the fourth and sixth conductive layers; a third electrode provided so as to continuously cover the surfaces of the eighth and ninth conductive layers; and a second electrode connected to the fourth and sixth conductive layers. It is characterized by comprising a first wiring that connects the surfaces of the second conductive layer and the third conductive layer, and a second wiring that connects the surfaces of the second conductive layer and the seventh conductive layer.

(Function) When a negative trigger signal is applied to the second electrode as a gate electrode, the TS6 conductive layer, the third conductive layer, and the first
The auxiliary thyristor consisting of the conductive layer and the eighth conductive layer is turned on, and the on-current at this time is transmitted through the first wiring to the fifth conductive layer, the second conductive layer, the first conductive layer, and the eighth conductive layer. Supplied as gate current to the main thyristor.

When a positive trigger signal is applied to the second electrode, the auxiliary thyristor consisting of the seventh conductive layer, the fourth conductive layer, the first conductive layer, and the eighth conductive layer is turned on, and the on-current at this time is The current is supplied to the main thyristor as a gate current through the wiring No. 2.

Since the second electrodes connected to the fourth and sixth conductive layers of both auxiliary thyristors are not provided continuously on the third and seventh conductive layers, respectively, the reactive current components of both auxiliary thyristors are sufficient. becomes smaller and more sensitive. Therefore, the sensitivity of the operation in the ■ mode and ■ mode is particularly increased.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings. 1st
The figure is a sectional view showing the element structure when the controlled rectification semiconductor device of the present invention is implemented as a triac, and FIG. 2 is a pattern plan view of the triac as seen from the gate electrode side.

When configuring an element with a withstand voltage of about 600V, the thickness is 2
A substrate having a thickness of about 50 μm and a resistivity of about 40 Ω·cm is prepared, and a five-layer structure as shown in the figure is obtained using well-known oxidation, impurity diffusion, and lithography techniques. That is, N type substrate 1
P-type layers 11, 12, and 13 are formed on one surface of 0, separated from each other.

Here, the surface impurity concentration of these P-type layers is 1 to 2×10
17/Cm2, and the diffusion depth xj is 40 to 50
It is set to μm. An N-type layer 14 with a shorted structure is formed in the surface area of the P-type layer 11, an N-type layer 15 is formed in the surface area of the P-type layer 12, and an N-type layer 16 is formed in the surface area of the P-type layer 13.
are formed respectively. Here, the surface impurity concentration of these N-type layers is set to about 1021/cm2, and the diffusion depth xj is set to about 20 μm or less.

An electrode T1 is provided on the surface of the N-type layer 14. Furthermore, a gate electrode G is provided on the surface of the N-type layer 15 and the surface of the P-type layer 13.

Further, the surface of the P-type layer 12 and the surface of the P-type layer 11 are connected by a wiring 17, and the surface of the N-type layer 16 and the surface of the P-type layer 11 are connected to each other by a wiring 17.
It is connected to the surface by a wiring 18.

A P-type layer 19 is formed on the other surface of the N-type substrate 10. The surface impurity concentration of this P-type layer 19 is set to 1 to 2 x 1017/cm2 as described above, and the diffusion depth xj is set to 40 to 50 um. Also, this P
An N-type layer 20 is formed on the surface region of the type layer 19.

The surface impurity concentration of this N-type layer 20 is 102 as described above.
The diffusion depth xj is approximately 1/Cm2, and the diffusion depth xj is 20μm.
It has been kept below the level.

Here, the N-type layer 14, the P-type layer 11. The N-type substrate 10 and the P-type layer 19 constitute a unidirectional main thyristor.
The type layer 20, the P type layer 19, the N type substrate 10, and the P type layer 11 constitute the main thyristor in the other direction. Furthermore, N-type layer 1
G, P-type layer 13, N-type substrate 10 and P-type layer 19 constitute an auxiliary silicon risk for positive polarity gate input, and N-type layer 15, P-type layer 12, N-type substrate IO and P-type layer 19 constitute negative polarity. The sexual gate constitutes an auxiliary cyrisk to human power.

Next, the operation of the triac having such a configuration will be explained.

First, the operation in the ■mode (T2 is positive polarity, G is positive polarity) is the same as the general Cyrisk operation, and by applying a positive trigger signal to the gate electrode G, the N-type layer 1
6 to the P-type layer 13, and as a result, the N-type layer 1G, the P-type layer 13, the N-type substrate 10 and the P-type layer 1
Auxiliary Sailisk consisting of 9 turns on. The on-current at this time is supplied to the P-type layer 11 via the wiring 18 as a gate current.

Here, in the above-mentioned auxiliary silicon risk, the gate electrode G is connected only to the surface of the P-type layer 13, and the invalid component of the gate current is extremely reduced. After this, electron injection occurs from the N-type layer 14 to the P-type layer 11, and as a result, the N-type layer 14,
The main thyristor consisting of the P-type layer 11, the N-type substrate IO and the P-type layer 19 is turned on.

This kind of gate trigger operation is called amplification gate operation. For example, the auxiliary thyristor is turned on with a gate current of about several μA, and the on-current at this time is about several hundred mA at maximum, so the main thyristor is turned on sufficiently. can be put into a state. In this way, the gate sensitivity during operation in the ■mode can be made extremely high.

■The operation in the mode (T2 is positive polarity and G is negative polarity) is the same as general thyristor operation, and by applying a negative trigger signal to the gate electrode G, the N-type layer 15 changes to the P-type layer. Electron injection occurs in 12, which causes the N-type layer I
5. The auxiliary silicon layer consisting of the P-type layer 12, the N-type substrate 10 and the P-type layer 19 is turned on. The on-current at this time first flows into the gate circuit, is limited by the gate resistance, and after the gate potential becomes a positive potential with respect to T1, is supplied to the P-type layer 11 as a gate current via the wiring 17. Ru. Here, in this auxiliary thyristor, the gate electrode G is connected only to the surface of the N-type layer 15, so that the invalid component of the gate current is extremely reduced. After this, electrons are injected from the N-type layer 14 to the P-type layer 11 in the same way as in the above case, and as a result, the N-type layer 14, the P-type layer 11, and the N-type substrate I
The main silicon risk consisting of O and P type layers 19 is turned on.

This type of gate trigger operation is called junction gate operation. For example, the auxiliary thyristor is turned on with a gate current of about a few μA, and the on-current is about several hundred mA at maximum, so the main thyristor must be turned on sufficiently. be able to. In this way, the gate sensitivity during operation in the ■mode can also be made extremely high.

In addition, in the case of mode (2) (T2 is negative polarity, G is negative polarity), by applying a negative trigger signal to the gate electrode G, the N-type layer 15, the P-type layer 12, and the N-type substrate 10 are An NPN transistor consisting of a remote gate operates. In this operation, first, electrons injected from the N-type layer 15 to the P-type layer 12 reach the N-type substrate 10, and the P-type layer 12 and N
By strongly biasing the junction with the mold substrate 10, P
Holes are injected from the type layer 12 into the N-type substrate 10 . When these holes reach the P-type layer 19 and flow laterally, a voltage drop occurs and electron injection from the N-type layer 20 begins. As a result, the P-type layer 11, the N-type substrate 10, the P-type layer 19, and the N-type layer 2
The main thyristor consisting of 0 is turned on. Such a gate trigger operation is called a remote gate operation.

Furthermore, in the case of mode (2) (T2 is negative polarity and G is positive polarity), a positive trigger signal is applied to the gate electrode G, thereby causing the N-type layer 1B, the P-type layer 13 and the N-type substrate 1
NPN consisting of 0 ) run lister performs remote gate operation, P-type layer 11SNJ42u board 1 as in mode ■
0, the main thyristor consisting of the P-type layer 19 and the N-type layer 2o is turned on.

In the ■ mode and ■ mode, the large gate current as in the ■ mode and ■ mode is not supplied to the main sirisk, so that the gate sensitivity is lower than in the ■ mode and ■ mode. However, in the auxiliary thyristor, since the reactive component of the gate current is not very small, the gate sensitivity in the (1) mode and (2) mode can be improved compared to the conventional one.

Therefore, in the triac of the above embodiment, the gate sensitivity in modes I to ■ can be reduced to several μA. Generally I.C.
Since the maximum output current is about 5 mA, the triac of the above embodiment can be sufficiently driven by the output current of the IC.

Furthermore, triacs have a unique mode that is triggered by dv/dt during commutation, and this tolerance is generally
It is called fE dv/dt. This mode is caused by the behavior of residual carriers during commutation, and the reason is that the triac of the above embodiment is divided into a main thyristor and an auxiliary thyristor, and the main thyristor and auxiliary thyristor are placed apart. Due to the synergistic effect, this commutation dv/dt tolerance can also be improved. On the other hand, with conventional equipment, even if the gate sensitivity of modes 1 to ■ could be designed to be around 5 mA, the gate sensitivity of mode ■ would be around 20 mA, four times these, and could not be driven directly by the output current of the IC. .

FIG. 3 is a sectional view showing the element structure when the present invention is implemented in another triac. In the triac of this embodiment, the P-type layer 12 of the auxiliary thylisk is integrated with the P-type layer 11 of the main thylisk. According to such a configuration, there is no need to separate the P-type layer 12 and the P-type layer 11 from each other, so that the device area can be reduced.

Here, in the triac of each of the above embodiments, the dv/dt tolerance is determined by a highly sensitive auxiliary signal. Therefore, if resistors r1 and r2 are inserted between the N-type layer 15 and the P-type layer 12 or 11 and between the N-type layer 1G and the P-type layer 13 as shown in FIG. 3, the gate sensitivity will be reduced. It is possible to improve the dv/dt tolerance, although it decreases somewhat. The resistance values of these resistors r1 and r2 are such that the PN junction voltage is 0.6V and the gate input current of the main thyristor is 5mA.
When set to 0.6V15mA, i.e. 1000
adjusted accordingly.

By the way, if you use a triac with the configuration shown in Figure 1 above,
The detailed operation when operating in this mode is as follows. When a negative trigger signal is applied to the gate electrode G,
A PN consisting of an N-type layer 15 and a P-type layer 12 of the auxiliary thyristor.
The junction is forward biased, and a current flows from the electrode T1 to the gate electrode G via the P-type layer 11 and the wiring 17. and,
NP consisting of an N-type layer 15, a P-type layer 12 and an N-type substrate 10
The sum of the current amplification factor αN of the N transistor and the current amplification factor αP of the PNP transistor consisting of the P-type layer 12, the N-type substrate 10, and the P-type layer 19 is the sum of the current amplification factor αN of the N-type transistor
1 with an auxiliary thyristor consisting of a type substrate 10 and a P type layer 19.
When the voltage is exceeded, this auxiliary thyristor is turned on, and a current flows through a gate circuit (not shown) connected to the gate electrode G. This current is limited by a gate resistor (not shown) provided in the gate circuit, and the gate potential is lower than the electrode T1.
When the potential becomes positive with respect to the P-type layer 12, excess holes in the P-type layer 12 are now discharged. That is, current begins to flow toward electrode T1, and the main thyristor begins to turn on.

The sensitivity during operation in this (2) mode is improved compared to the conventional device as shown in FIG.

However, it is still lower than when operating the amplification gate in mode ■.

FIG. 4 is a sectional view showing the element structure when the present invention is implemented in yet another triac. The difference between the triac of this embodiment and the one shown in FIG.
Another N-type layer 21 is formed separately from the N-type layer 15. And the above distribution t! 111
7 is formed so as to connect the surface of this N-type layer 21, the surface of P-type layer 12, and the surface of P-type layer 11.

In this triac, the N-type layer 2I is newly added to 1[/
By doing this, a junction thyristor consisting of an N-type layer 21, a P-type layer 12, an N-type substrate io, and a P-type layer 19 is added to the one shown in FIG.

In this triac, in mode (2) in which the electrode T2 is of positive polarity and the gate electrode G is of negative polarity, the auxiliary thyristor consisting of the N-type layer 15, the P-type layer 12, the N-type substrate 10, and the P-type layer 19 is first activated. Turn on. After this, when the gate potential becomes positive with respect to the electrode T1 as described above,
This time, current flows from the P-type layer 12 to the N-type layer 21, and the current flows from the P-type layer 12 to the N-type layer 21. The junction silicon layer consisting of the P-type layer 12, the N-type substrate 10, and the P-type layer 19 starts to turn on. Then, this on-current is supplied as a gate current to the P-type layer 11 via the wiring 17, and the N-type layer 14, the P-type layer 11, and the N-type substrate IO
and the main silicon risk consisting of the P-type layer 19 is turned on. In this case, the junction silicon risk consisting of the N-type layer 21, the P-type layer 12, the N-type substrate 10, and the P-type layer 19 is
4. It functions as an amplification gate for the main silicon layer composed of the P-type layer 11, the N-type substrate 10, and the P-type layer 19, and the sensitivity at this time is improved compared to the case of FIG.

The operations other than the above-mentioned mode (2) are the same as the triac shown in FIG. 1, so the explanation thereof will be omitted. Note that in the triac shown in FIG. 4, the P-type layer 12 is similar to the case shown in FIG.
can also be formed integrally with the P-type layer 11.

[Effects of the Invention] As explained above, according to the present invention, it is possible to provide a bidirectional control rectifier semiconductor device that can increase gate sensitivity without impairing characteristics such as dv/dt tolerance.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the configuration of an apparatus according to an embodiment of the present invention;
FIG. 2 is a pattern plan view of the device of the above embodiment, FIG. 3 is a sectional view showing the configuration of another embodiment of the device of the present invention, and FIG. 4 is a sectional view showing the structure of still another embodiment of the device of the present invention. figure,
FIG. 5 is a sectional view of a conventional device. lO...N type substrate, 11.12.13.19...P
Type layer, 14, 15.16.20.21...N type layer, 1
7.18... Wiring, rl, r2... Resistance, Tl, T
2... Electrode, G... Gate electrode. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 3

Claims (3)

[Claims] (1) a first conductive layer of a first conductivity type; second, third, and fourth conductive layers of a second conductivity type provided separately from each other on one surface of the first conductive layer; a fifth conductive layer of the first conductivity type provided in the surface area of the second conductive layer; a sixth conductive layer of the first conductivity type provided in the surface area of the third conductive layer; a seventh conductive layer of the first conductivity type provided on the surface region; an eighth conductive layer of the second conductivity type provided on the other surface of the first conductive layer; and a seventh conductive layer of the second conductivity type provided on the surface region of the eighth conductive layer. a ninth conductive layer of a first conductivity type provided; a first electrode provided so as to continuously cover the surfaces of the second and fifth conductive layers; and each of the fourth and sixth conductive layers. a second electrode connected to the second electrode; a third electrode provided to continuously cover the surfaces of the eighth and ninth conductive layers; and a third electrode connected to the surfaces of the second conductive layer and the third conductive layer. A bidirectionally controlled rectifying semiconductor device comprising: a first wiring that connects; and a second wiring that connects surfaces of the second conductive layer and the seventh conductive layer. (2) The bidirectionally controlled rectifying semiconductor device according to claim 1, wherein the second conductive layer and the third conductive layer are integrated. (3) a first conductive layer of a first conductivity type; second, third, and fourth conductive layers of a second conductivity type provided separately from each other on one surface of the first conductive layer; a fifth conductive layer of the first conductivity type provided in the surface area of the second conductive layer; a sixth conductive layer of the first conductivity type provided in the surface area of the third conductive layer; a seventh conductive layer of the first conductivity type provided on the surface region; an eighth conductive layer of the second conductivity type provided on the other surface of the first conductive layer; and a seventh conductive layer of the second conductivity type provided on the surface region of the eighth conductive layer. a ninth conductive layer of a first conductivity type provided; a tenth conductive layer of a first conductivity type provided in a surface region of the third conductive layer, separated from the sixth conductive layer; , a first electrode provided so as to continuously cover the surface of the fifth conductive layer, a second electrode connected to each of the fourth and sixth conductive layers, and the eighth and ninth conductive layers. a third electrode provided so as to continuously cover the surface of the layer; a first wiring connecting the surfaces of each of the second conductive layer, the third conductive layer, and the tenth conductive layer; 1. A bidirectionally controlled rectifying semiconductor device, comprising: a second wiring connecting the surfaces of the second conductive layer and the seventh conductive layer.