JPH0173956U - - Google Patents
Info
- Publication number
- JPH0173956U JPH0173956U JP17021387U JP17021387U JPH0173956U JP H0173956 U JPH0173956 U JP H0173956U JP 17021387 U JP17021387 U JP 17021387U JP 17021387 U JP17021387 U JP 17021387U JP H0173956 U JPH0173956 U JP H0173956U
- Authority
- JP
- Japan
- Prior art keywords
- transparent conductive
- conductive surface
- chip
- electrode
- transparent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 2
- 230000003287 optical effect Effects 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案に係る半導体装置の模型的構成
図、第２図および第３図はそれぞれ透明電極板の
他例を示す正面図および斜視図、第４図は本考案
品の特性図、第５図は従来の半導体装置の模型的
構成図である。
２…一方のリード端子、３…他方のリード端子
、４…半導体光素子チツプ、５…一方の電極、６
…導電性接着剤（銀ペースト）、５…他方の電極
、１０，１７，１９…透明電極板、１１，１８，
２０…ガラス基板、１２…透明導電面（透明導電
薄膜）、１３…保持枠。
FIG. 1 is a schematic block diagram of a semiconductor device according to the present invention, FIGS. 2 and 3 are front and perspective views showing other examples of transparent electrode plates, respectively, and FIG. 4 is a characteristic diagram of the product of the present invention. FIG. 5 is a schematic diagram of a conventional semiconductor device. 2... One lead terminal, 3... Other lead terminal, 4... Semiconductor optical element chip, 5... One electrode, 6
... Conductive adhesive (silver paste), 5... Other electrode, 10, 17, 19... Transparent electrode plate, 11, 18,
20... Glass substrate, 12... Transparent conductive surface (transparent conductive thin film), 13... Holding frame.
Claims (1)
能を有する半導体光素子チツプと、このチツプへ
の接続用の一対のリード端子と、ガラス基板の少
なくとも一面に透明導電面を設けた透明電極板と
を備え、前記チツプの一方の電極が導電性接着剤
を介して一方の前記リード端子に電気的接続状態
に接着され、少くとも一方のリード端子が前記透
明電極板に固着された保持枠により固定されて前
記チツプの他方の電極が前記透明導電面に対向さ
れているとともに、この他方の電極が導電性接着
剤を介して前記透明導電面に電気的接続状態に接
着され、他方の前記リード端子が前記透明導電面
に電気的接続状態に接着されてなることを特徴と
する半導体装置。 A semiconductor optical device chip that has a photoelectric conversion function by passing current between a pair of electrodes, a pair of lead terminals for connection to this chip, and a transparent electrode plate having a transparent conductive surface on at least one surface of a glass substrate. one electrode of the chip is electrically connected to one of the lead terminals via a conductive adhesive, and at least one lead terminal is fixed by a holding frame fixed to the transparent electrode plate. The other electrode of the chip is opposed to the transparent conductive surface, the other electrode is electrically connected to the transparent conductive surface via a conductive adhesive, and the other lead terminal is connected to the transparent conductive surface. A semiconductor device, characterized in that the semiconductor device is bonded to the transparent conductive surface in an electrically connected state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17021387U JPH0173956U (en) | 1987-11-06 | 1987-11-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17021387U JPH0173956U (en) | 1987-11-06 | 1987-11-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0173956U true JPH0173956U (en) | 1989-05-18 |
Family
ID=31460962
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17021387U Pending JPH0173956U (en) | 1987-11-06 | 1987-11-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0173956U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4826980A (en) * | 1971-08-12 | 1973-04-09 | ||
| JPS6236561B2 (en) * | 1981-07-06 | 1987-08-07 | Yokokawa Denki Kk |
-
1987
- 1987-11-06 JP JP17021387U patent/JPH0173956U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4826980A (en) * | 1971-08-12 | 1973-04-09 | ||
| JPS6236561B2 (en) * | 1981-07-06 | 1987-08-07 | Yokokawa Denki Kk |
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