JPH0167581U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main parts of an IC testing device according to this invention, FIG. 2 is a block diagram showing another example, and FIG. 3 is a block diagram showing a part of a conventional IC testing device.

Claims (1)

[Claims for Utility Model Registration] A test pattern memory and a control pattern memory are each read out by an address signal from an address generation circuit, and a timing signal is generated from a timing generator by a timing selection signal read out from the control pattern memory, In an IC test device that controls the test pattern read from the test pattern memory using the timing signal and supplies the test pattern to the IC device under test, the timing selection register stores the timing selection signal and the timing selection signal of the timing selection register. a switching circuit that switches and supplies the timing selection signal from the control pattern memory to the timing generator; a test pattern counter that counts the number of generated test patterns; and a pattern number register that stores the number of test patterns to be switched. and a coincidence detection circuit that detects coincidence between the number of test patterns in the pattern number register and the count value of the test pattern counter and switches the switching circuit to the timing selection register side.