JPH0160944B2 - - Google Patents
Info
- Publication number
- JPH0160944B2 JPH0160944B2 JP55189543A JP18954380A JPH0160944B2 JP H0160944 B2 JPH0160944 B2 JP H0160944B2 JP 55189543 A JP55189543 A JP 55189543A JP 18954380 A JP18954380 A JP 18954380A JP H0160944 B2 JPH0160944 B2 JP H0160944B2
- Authority
- JP
- Japan
- Prior art keywords
- data
- semiconductor device
- image
- processing
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 31
- 238000012545 processing Methods 0.000 claims description 21
- 238000007689 inspection Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 10
- 238000003384 imaging method Methods 0.000 claims 4
- 238000002788 crimping Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000002950 deficient Effects 0.000 description 3
- 230000005856 abnormality Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000007781 pre-processing Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
- G01N21/956—Inspecting patterns on the surface of objects
Description
【発明の詳細な説明】
本発明は、加工された半導体装置を検査する際
に適用して好ましい半導体装置の組み立て検査方
法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for assembling and inspecting semiconductor devices that is preferably applied to inspecting processed semiconductor devices.
一般に、物品を加工した後それが正常な状態を
維持しているか否かを検査することは不可欠であ
る。 Generally, after processing an article, it is essential to inspect whether it maintains a normal condition.
従来、そのような検査を行なうための方式とし
ては、
(1) 対象物品の映像をメモリ内に取り込み、画像
処理に依つて目的とする映像を認識する方式。 Conventionally, methods for conducting such inspections include: (1) A method in which an image of the target item is captured into memory and the target image is recognized through image processing.
(2) 規準となる映像と逐一比較して目的とする映
像を認識する方式。(2) A method of recognizing the target image by comparing it point-by-point with a standard image.
などが実施されている。しかしながら、(1)の方式
では多量のデータ処理が必要であり、(2)の方式で
は、相互比較すべき二つの映像をＸ，Ｙ，Ｚの３
次元回転方向、加工誤差も含めて位置合せをしな
ければならない。etc. are being carried out. However, method (1) requires a large amount of data processing, and method (2) requires two images to be compared with each other to be
Positioning must be done taking into account the dimensional rotational direction and machining errors.
本発明は、加工前及び加工後の半導体装置の映
像を比較することに依り、簡単且つ容易に該半導
体装置の検査を行うことができるようにするもの
であり、以下、これを詳細に説明する。 The present invention enables inspection of a semiconductor device simply and easily by comparing images of the semiconductor device before and after processing, and this will be explained in detail below. .
第１図ａは加工前の半導体装置の要部平面説明
図を、また、第１図ｂは加工後の半導体装置の要
部平面説明図をそれぞれ表している。 FIG. 1A shows a plan view of the main part of the semiconductor device before processing, and FIG. 1B shows a plan view of the main part of the semiconductor device after processing.
図に於いて、１は半導体装置、２は半導体チツ
プ、３は半導体チツプ２上のボンデイング・パツ
ド、４は基板上のボンデイング・パツド（２次パ
ツド）、５は配線材料（Au）であるワイヤをそれ
ぞれ表す。 In the figure, 1 is the semiconductor device, 2 is the semiconductor chip, 3 is the bonding pad on the semiconductor chip 2, 4 is the bonding pad (secondary pad) on the substrate, and 5 is the wire which is the wiring material (Au). respectively.
第１図ｂに見られる半導体装置１、即ち、ワイ
ヤ・ボンデイングを終了後のものについては通常
次の項目について検査を行なう。 The semiconductor device 1 shown in FIG. 1B, ie, after wire bonding is completed, is usually inspected for the following items.
(イ) ワイヤの有無
(ロ) 半導体チツプの欠け、割れ、
(ハ) パツドとワイヤの位置ずれ、接着不良
(ニ) ワイヤの断線、隣接ワイヤ相互の接触或いは
接近
本発明を実施して前記の如き検査を行なう認識
装置の一例が第２図に示されている。(a) Presence or absence of wires (b) Chips or cracks in the semiconductor chip (c) Misalignment or poor adhesion between pads and wires (d) Disconnection of wires or contact or closeness of adjacent wires An example of a recognition device for performing such a test is shown in FIG.
図に於いて、１１は被加工品搬送装置、１２は
供給側容器、１３は受取側容器、１４は映像読取
系であるテレビジヨン・カメラ、１５はワイヤ・
ボンダ、１６は光源、１７は映像信号デイジタル
化回路、１８は画像データ前処理回路、１９は検
査論理回路、２０は制御系、２１は画像メモリ、
２２は各種Ｉ／Ｏをそれぞれ示す。尚、１は被検
半導体装置である。 In the figure, 11 is a workpiece conveyance device, 12 is a supply side container, 13 is a receiving side container, 14 is a television camera that is an image reading system, and 15 is a wire
16 is a light source, 17 is a video signal digitization circuit, 18 is an image data preprocessing circuit, 19 is an inspection logic circuit, 20 is a control system, 21 is an image memory,
22 indicates various I/Os. Note that 1 is a semiconductor device to be tested.
本装置にて検査を行なうには、メモリ２１に基
準データを入力しておく必要があり、これはテイ
ーチ・イン（Teach In）と呼ばれている。第３
図ａにはテイーチ・インすべき基準データが示さ
れている。即ち、加工前の半導体装置の映像Ｔ１
を基にしてパツド位置及びその大きさをレチク
ル・マーク指示に依り作り出し基準パツド部デー
タＴ３を得る。また、加工前の半導体装置の映像
Ｔ１及び加工後の映像Ｔ２の差を検出して基準加
工部データＴ４を得る。これ等基準データを予め
メモリ２１に記憶させるものとする。 In order to perform an inspection with this device, it is necessary to input reference data into the memory 21, and this is called teach-in. Third
Diagram a shows the reference data to be taught in. That is, the image T1 of the semiconductor device before processing
Based on this, the pad position and its size are created according to the reticle mark instructions to obtain reference pad portion data T3. Further, the difference between the image T1 of the semiconductor device before processing and the image T2 after processing is detected to obtain reference processed portion data T4. It is assumed that these reference data are stored in the memory 21 in advance.
このようなテイーチ・イン終了後、実際に検査
される被検半導体装置１が製造工程を流れる場合
を第２図及び第３図ｂに依り説明する。 A case in which the semiconductor device 1 to be tested actually goes through the manufacturing process after the teach-in is completed will be described with reference to FIGS. 2 and 3b.
半導体装置１は搬送装置１１に依り供給側容器
１２から受取側容器１３に向つて搬送される。そ
してテレビジヨン・カメラ１４で撮像され位置検
出用マークを用いて位置検知される。その際の撮
像が第３図ｂにＡ１として表わされている。この
映像Ａ１と基準パツド部データＴ３と位置合せし
てからパツド部データＡ３を得る。即ち、加工前
の基準パツド部データＴ３と被検査半導体装置の
加工前の映像Ａ１とをパターン・マツチング法で
完全に重なるように映像Ａ１を移動させ、重ね合
わされる前の位置から完全に重ね合わされた際の
位置までの移動距離を求め、この誤差分だけ基準
パツド部データＴ３を移動させた新たなパツド部
データＡ３を得るものである。その結果、半導体
装置１は位置ずれを補正されながらワイヤ・ボン
ダ１５の動作領域に送られ、ワイヤ・ボンデイン
グ（加工）される。その後、さきに加工前の撮像
を行なつた位置まで戻し、加工後の撮像を行なつ
て映像Ａ２を得てこれと撮像Ａ１と比較し加工部
データＡ４を得る。 The semiconductor device 1 is transported by a transport device 11 from a supply container 12 to a receiving container 13 . Then, an image is taken by the television camera 14, and the position is detected using a position detection mark. The image captured at that time is shown as A1 in FIG. 3b. After aligning this image A1 with the reference pad part data T3, pad part data A3 is obtained. That is, the unprocessed reference pad part data T3 and the unprocessed image A1 of the semiconductor device to be inspected are moved using a pattern matching method so that they completely overlap, and the image A1 is completely overlapped from the position before being overlapped. The moving distance to the position at the time of the change is determined, and new pad part data A3 is obtained by moving the reference pad part data T3 by this error. As a result, the semiconductor device 1 is sent to the operation area of the wire bonder 15 while the positional deviation is corrected, and wire bonded (processed). Thereafter, it is returned to the position where the image before processing was previously taken, and the image after processing is taken to obtain image A2, which is compared with image A1 to obtain processed portion data A4.
前記諸データをもとに加工部分データの比較に
よる検査を実行してから被検半導体装置１は所定
の受取側容器１３に送入される。 After performing an inspection by comparing processed portion data based on the various data, the semiconductor device 1 to be tested is sent to a predetermined receiving container 13.
第４図乃至第８図は検査の内容を具体的に説明
する為のデータ説明図である。 FIG. 4 to FIG. 8 are data explanatory diagrams for specifically explaining the contents of the examination.
第４図は半導体装置の有無を検査する場合であ
り、データＴ３と映像Ａ１の位置合せに依る。 FIG. 4 shows a case where the presence or absence of a semiconductor device is inspected, and it depends on the alignment of data T3 and image A1.
第５図はパツドとワイヤ圧着部の位置ずれを検
査する場合であり、データＴ３（或いはデータＡ
３）とデータＡ４を基に検出された圧着部位置に
関するデータＡ４′とを比較し、データＴ３（或
いはデータＡ３）のパツドの圧着位置に対するワ
イヤ圧着点の位置ずれを検出している。位置ずれ
は第５図ｂに見られるようにΔx，Δyで表わされ
る。尚Ｗはワイヤ、P1，P2はパツドを示してい
る。 Figure 5 shows the case of inspecting the positional deviation between the pad and the wire crimping part, and data T3 (or data A
3) and data A4' regarding the position of the crimping part detected based on the data A4, the positional deviation of the wire crimping point with respect to the crimping position of the pad of data T3 (or data A3) is detected. The positional deviation is represented by Δx and Δy, as seen in FIG. 5b. Note that W indicates a wire, and P 1 and P 2 indicate pads.
第６図は圧着部の面積を検査する場合であり、
データＡ３或いはデータＴ３とデータＡ４とを比
較し、データＡ３などで指示される検出窓エリア
（パツド・エリア）内に占めるワイヤ圧着部の面
積及びそこからはみ出た面積を検出する。第６図
ｂには圧着が正常に行なわれている場合（左側）
とはみ出た場合（右側）とが示されている。 Figure 6 shows the case of inspecting the area of the crimped part.
Data A3 or data T3 and data A4 are compared to detect the area of the wire crimping portion occupying within the detection window area (pad area) indicated by data A3 and the like and the area protruding from the area. Figure 6b shows a case where crimping is performed normally (left side)
and the case where it protrudes (on the right) are shown.
第７図はワイヤ位置の不良を検査する場合であ
り、データＴ４，Ａ４を拡大処理したデータＴ４
ｌ，Ａ４ｌと元の映像データとを比較したものの
マツチングをとり、各々他からはみ出した部分を
検知することに依り第７図ｂに見られるように加
工ワイヤの不足At及び余分Orを検出する。また、
同様にしてワイヤの断線も検査でき、更にまた、
ワイヤの細りはデータＡ４を縮小処理して細りの
部分が断線しているデータに変換してから第７図
に見られる手法を採ることに依り検出できる。 FIG. 7 shows a case where defective wire positions are inspected, and data T4 is obtained by enlarging data T4 and A4.
1 and A4l are compared with the original video data and matched, and by detecting the parts of each protruding from the others, the insufficient At and excess Or of the processed wire are detected as shown in FIG. 7b. Also,
In the same way, wire breaks can be inspected, and furthermore,
The thinning of the wire can be detected by reducing the data A4 and converting it into data in which the thinned portion is broken, and then employing the method shown in FIG. 7.
加工後、半導体装置に割れ、欠けを生じていれ
ばデータＡ４に変化分としてその映像が入つてい
るから、それとデータＴ４を比較すれば検出でき
る。 If the semiconductor device is cracked or chipped after processing, it can be detected by comparing it with the data T4 since the data A4 contains an image of the change.
第８図は隣接ワイヤ相互の接触、接近を検査す
る場合であり、データＡ４に於ける交点を検知す
ることに依り“接触”を、またデータＡ４を拡大
処理して得たデータＡ４ｌで重なり部を検出して
“接近”をそれぞれ見出すことができる。尚、デ
ータＡ４ｄでは接触（または接近）したパターン
Ncが示されている。 Figure 8 shows the case of inspecting mutual contact and approach between adjacent wires. "Contact" is detected by detecting intersections in data A4, and overlapping areas are detected by data A4l obtained by enlarging data A4. It is possible to find "approach" by detecting the following. In addition, in data A4d, the contact (or approach) pattern
N c is shown.
前記実施例に於いて、加工後の半導体装置にワ
イヤが欠落していることが発見された場合、その
アドレスをワイヤ・ボンダにフイード・バツクし
て再ワイヤリングを行なわせたり、再ワイヤリン
グ専用のワイヤ・ボンダを連結しておいてそれに
再ワイヤリングを行なわせるようにしても良い。
また、検査の結果、異常が発見されたときは、異
常警告を発したり、位置ずれや加工強度を改める
よう加工機に制御信号をフイード・バツクするこ
となどは容易である。更にまた、検査内容を外部
からの指示で変更、増減することも簡単に行なう
ことができる。 In the above embodiment, if it is discovered that a wire is missing in the semiconductor device after processing, the address is fed back to the wire bonder to perform rewiring, or a wire dedicated for rewiring is used. - It is also possible to connect the bonder and have it perform rewiring.
Furthermore, if an abnormality is found as a result of the inspection, it is easy to issue an abnormality warning or feed back a control signal to the processing machine to correct positional deviation or processing strength. Furthermore, the inspection contents can be easily changed, increased or decreased based on instructions from outside.
以上の説明で判るように、本発明に依れば次の
ような効果が得られる。 As can be seen from the above explanation, the following effects can be obtained according to the present invention.
(1) 加工前と加工後の映像を比較して加工部のデ
ータを検出しているので、加工の前後に於いて
対象とされているのは常に同一半導体装置であ
つて、半導体装置の回転、水平方向の傾き、焦
点深度、半導体装置毎の性状相違などは考慮す
る必要がなく、加工部だけを単なる二次元的位
置合せで検査できる。(1) Data on the processed part is detected by comparing images before and after processing, so the target is always the same semiconductor device before and after processing, and the rotation of the semiconductor device There is no need to consider horizontal tilt, depth of focus, and differences in properties of each semiconductor device, and only the processed portion can be inspected by simple two-dimensional alignment.
(2) 被加工部データと加工部データとは混在して
いないので別個に取扱うことができ、認識処理
は容易である。(2) Since the processed part data and the processed part data are not mixed, they can be handled separately, and recognition processing is easy.
(3) 加工系と加工後検査系とを同一系で実現して
いるから、不良品のフイード・バツクが可能で
あり、不良警告を最も早く出すことができる。(3) Since the processing system and post-processing inspection system are implemented in the same system, it is possible to feed back defective products and issue defective warnings as quickly as possible.
第１図ａ，ｂは加工前及び加工後の半導体装置
の説明図、第２図は本発明を実施する装置の一例
を表わす説明図、第３図は基準データと被検半導
体装置データの説明図、第４図乃至第８図は検査
手順を表わす為のデータ説明図である。
図に於いて、１は半導体装置、１１は搬送装
置、１２，１３は容器、１４はテレビジヨン・カ
メラ、１５はワイヤ・ボンダ、１６は光源、１７
はデイジタル化回路、１８は前処理回路、１９は
論理回路、２０は制御系、２１はメモリ、２２は
Ｉ／Ｏである。
1a and 1b are explanatory diagrams of a semiconductor device before and after processing, FIG. 2 is an explanatory diagram showing an example of a device implementing the present invention, and FIG. 3 is an explanation of reference data and test semiconductor device data. 4 to 8 are explanatory diagrams of data for representing the inspection procedure. In the figure, 1 is a semiconductor device, 11 is a transport device, 12 and 13 are containers, 14 is a television camera, 15 is a wire bonder, 16 is a light source, and 17
18 is a digitizing circuit, 18 is a preprocessing circuit, 19 is a logic circuit, 20 is a control system, 21 is a memory, and 22 is an I/O.
Claims (1)
映像信号を映像信号デイジタル化回路にてデイジ
タル化してメモリに格納し、加工後の半導体装置
を再び撮像系で撮像して得た映像信号を映像信号
デイジタル化回路にてデイジタル化してさきにメ
モリに格納したデータと検査論理回路にて比較す
ることにより加工部データを得て検査することを
特徴とする半導体装置の組み立て検査方法。1 A video signal obtained by imaging an unprocessed semiconductor device with an imaging system is digitized by a video signal digitization circuit and stored in a memory, and a video signal obtained by imaging the semiconductor device after processing with an imaging system again 1. A method for assembling and inspecting a semiconductor device, characterized in that processed part data is obtained and inspected by digitizing the data in a video signal digitizing circuit and comparing it with data previously stored in a memory in an inspection logic circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18954380A JPS57113356A (en) | 1980-12-30 | 1980-12-30 | Article inspection system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18954380A JPS57113356A (en) | 1980-12-30 | 1980-12-30 | Article inspection system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57113356A JPS57113356A (en) | 1982-07-14 |
| JPH0160944B2 true JPH0160944B2 (en) | 1989-12-26 |
Family
ID=16243064
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18954380A Granted JPS57113356A (en) | 1980-12-30 | 1980-12-30 | Article inspection system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57113356A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0357138U (en) * | 1989-10-09 | 1991-05-31 |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5942436A (en) * | 1982-08-09 | 1984-03-09 | Sumitomo Electric Ind Ltd | Method for inspecting solderless terminal |
| JPS61193053A (en) * | 1985-02-22 | 1986-08-27 | Hitachi Ltd | Method for inspection by image processing |
| JP2609594B2 (en) * | 1986-11-28 | 1997-05-14 | 株式会社日立製作所 | Defect inspection equipment |
| JPH04263233A (en) * | 1991-02-18 | 1992-09-18 | Ushio Kk | Image processor |
| CN110118777A (en) * | 2019-04-30 | 2019-08-13 | 北京航天自动控制研究所 | A kind of control system system integration Smart Verify platform |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5588347A (en) * | 1978-12-27 | 1980-07-04 | Fujitsu Ltd | Automatic aligning system |
| JPS55165647A (en) * | 1979-06-11 | 1980-12-24 | Mitsubishi Electric Corp | Device for automatically detecting whether wire bonding position is right or wrong |
-
1980
- 1980-12-30 JP JP18954380A patent/JPS57113356A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5588347A (en) * | 1978-12-27 | 1980-07-04 | Fujitsu Ltd | Automatic aligning system |
| JPS55165647A (en) * | 1979-06-11 | 1980-12-24 | Mitsubishi Electric Corp | Device for automatically detecting whether wire bonding position is right or wrong |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0357138U (en) * | 1989-10-09 | 1991-05-31 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57113356A (en) | 1982-07-14 |
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