JP2001176941A - Method for recognizing wafer coordinate of automatic defect detector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for recognizing a wafer coordinate of an automatic defects detector capable of enhancing coordinate precision and obtaining accurately a defective recognition image with high magnification. SOLUTION: The automatic defect detector extracts actual defective portions on a wafer under test as an image by means of a review SEM in reference to defective coordinate data obtained from the wafer. In step 3, an arbitrary image data in a point of origin of a chip are stored when a coordinate data is incorporated to obtain an alignment coordinate with respect to the wafer under test. In step 4, difference in the alignment coordinate is corrected by temporarily shifting the image data in the point of origin of the chip to origin coordinate of the defective chip in reference to the defective coordinate data to be superposed with each other. Thereafter, the image data is transferred to the defective portion corresponding to the defective coordinate data obtained in step 1 on the basis of the corrected alignment coordinate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of semiconductor devices, and more particularly, to the inspection of defects for each chip in a wafer process.
The present invention relates to a wafer coordinate recognition method of an automatic defect detection device for recognizing and detecting a defective portion.

[0002]

2. Description of the Related Art A scanning electron microscope, so-called SEM (Sc
Anning Electron Microscope) is suitable for increasing the magnification of a sharp uneven image. A review SEM (or INLINE-) which observes the step coverage and particles of the interlayer insulating film and wiring on the wafer by applying this SEM.
There is an image recognition technology called SEM). An automatic defect detection device has been developed in which software is constructed together with the review SEM and an automatic defect inspection is systematized.

[0003] The automatic defect detection apparatus first performs a defect inspection optically on a wafer to be inspected, for example, by comparing areas of adjacent chips with each other at an appropriate magnification. That is, if an abnormality is found in the same area of the compared adjacent chip, defect coordinate data is acquired as a defective portion.

Next, the defect coordinate data and the wafer to be inspected are aligned, and a detailed defect review is performed by a review SEM. Eventually, wafer defect detection is automatically achieved by providing an SEM image of the defect at the optimal magnification.

[0005] FIG. 4 shows an example applied to an automatic defect detection device.
FIG. 5 is a plan view for explaining a wafer alignment method in a review SEM. In the review SEM, for example, two points A1 and B1 are indicated with respect to the wafer WF to be inspected (the operator may point and indicate). The coordinates of each chip are obtained by calculation based on the points A1 and B1 (alignment coordinate acquisition). With such alignment coordinates, data of origin coordinates in each chip is also obtained.

The defect coordinate data of the wafer to be optically inspected is information on the distance from the chip origin, and the review SEM moves to the position indicated by the defect coordinate data based on the alignment coordinates. Accordingly, the automatic defect detection device provides an operator with an SEM image of an actual abnormal portion (defect portion) on the inspection target wafer at an optimum magnification.

[0007]

As described above, the review SEM uses the alignment coordinates obtained as described above to move to a defect location corresponding to the defect coordinate data.
However, the wafer coordinates determined by calculation such as the alignment coordinates are not matched at all with the distortion of the wafer to be inspected and the distortion generated at the time of exposure. As a result, an error occurs in the actual coordinates with respect to each chip origin.

Particularly, in a chip area near the periphery of the wafer, an error between the actual chip origin and the calculated chip origin becomes large. As a result, when moving to a defective portion using the alignment coordinates, the SEM image with a high magnification may not be able to accurately detect the defect.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object thereof is to provide a method of recognizing a wafer coordinate of an automatic defect detection apparatus capable of improving a coordinate accuracy and accurately obtaining a defect recognition image with a high magnification. To provide.

[0010]

According to the present invention, there is provided a method of recognizing wafer coordinates of an automatic defect detection apparatus, comprising the steps of: referring to defect coordinate data obtained from a wafer to be inspected; Regarding automatic defect detection to be extracted as, when aligning coordinate data with the inspected wafer to obtain alignment coordinates, image data of an arbitrary chip origin is stored, and the defect coordinate data is stored based on the alignment coordinates. When moving to a defective portion according to the above, the error of the alignment coordinates is corrected by temporarily moving to the origin coordinates of the defective chip with reference to the defect coordinate data and overlapping with the image data of the chip origin. It is characterized by putting.

According to the wafer coordinate recognizing method of the present invention, when moving to a defect location according to defect coordinate data, first,
Correct the alignment coordinate error once. Since each piece of defect coordinate data is information on the distance from the chip origin having a defect, the defect coordinate data can be accurately and accurately moved from the chip origin with the error corrected to the defect location.

[0012]

FIG. 1 is a flowchart for explaining a wafer coordinate recognition method of an automatic defect detection apparatus according to an embodiment of the present invention. In step 1, defect coordinate data is obtained from the wafer to be inspected. That is, the defect inspection is performed while comparing, for example, optically adjacent regions of each chip with the inspection target wafer at an appropriate magnification. That is, if an abnormality is found in the same area of the compared adjacent chip, defect coordinate data is acquired as a defective portion.

In step 2, predetermined data including defect coordinate data is sent to the review SEM (also called INLINE-SEM). In step 3, the coordinate data is matched with the wafer to be inspected to obtain alignment coordinates. That is, the alignment coordinates are obtained by calculation in the same manner as described with reference to FIG.

In the present invention, when acquiring the alignment coordinates in step 3, image data of an arbitrary chip origin is stored. Originally, when the coordinates are set, the image of the corner of the predetermined chip is recognized, and the image data is stored. Steps 2 and 3 may be interchanged.

Next, in step 4, the defect coordinates are temporarily moved to the origin coordinates of the defective chip with reference to the defect coordinate data. This is, of course, the movement using the alignment coordinates, and the error is large or small depending on the position of the movement.

Therefore, the image of the actual coordinates of the origin of the chip and the image data of the origin of the chip taken at the time of the acquisition of the alignment coordinates are superimposed to correct the error of the alignment coordinates. In other words, if the origin coordinates of the actual chip deviate, the chip origin that would be nearby is recognized,
Fine movement is performed so as to overlap with the stored image data of the chip origin. The superimposition of the images should preferably have the same magnification. For example, the magnification may be adjusted by adjusting the magnification of the image data of the chip origin taken in at the time of obtaining the alignment coordinates.

Next, at step 5, the chip moves to a defective portion of the chip corresponding to the defect coordinate data. In this case, the movement is performed using the new alignment coordinates in which the error of the chip origin is corrected, and the movement can be performed accurately and accurately to the moving position. Thereafter, although not shown, an SEM image of an actual abnormal portion (defect portion) on the inspection target wafer is provided at an optimum magnification.

That is, according to the wafer coordinate recognition method of the present invention, when moving to a defective portion according to the defect coordinate data, first, an error in the alignment coordinate is temporarily corrected. Since each defect coordinate data is given by information on the distance from the chip origin having a defect, it is possible to move to the defect location accurately and accurately from the error corrected chip origin. As a result, it is possible to accurately detect a defect even in a high magnification SEM image.

FIGS. 2 (a) and 2 (b) are wafer plan views more specifically showing the main part of the wafer coordinate recognition method of the automatic defect detection device in FIG. FIG. 2B shows that image data of an arbitrary chip origin is stored at the same time as the acquisition of the alignment coordinates in the above step 3. That is, for the wafer WF to be inspected, first, the points A1 and B1 for setting the alignment coordinates are determined (FIG. 2A). At this time, for example, a predetermined area of the point A1 is stored as image data (see FIG. 2).
(B)).

FIG. 3 is an enlarged plan view of a chip area in a wafer to be inspected WF, showing more specifically a main part of a method of recognizing a wafer coordinate of the automatic defect detection apparatus in FIG. The figure represents step 4 above. First, the chip once moves to the origin coordinates (X1, Y1) based on the alignment coordinates of the chip CHIP with reference to the defect coordinate data. Thereby, the chip origin overlapping with the image data of the previous point A1 is recognized, and the error of the chip origin of the alignment coordinates is corrected (chip origin coordinates (X2, Y2)).

By the above-described superposition recognition of the image data,
In the calculation, the alignment coordinates which looked like a wavy line are corrected in error, and almost coincide with the actual wafer coordinates as shown by a solid line. Thus, the defect coordinate data can be used to accurately and accurately move from the chip origin to the defect location D (arrow 3).
1).

As described above, according to the method of the above embodiment,
When moving to the defect location according to the defect coordinate data, the error is corrected so that the calculated alignment coordinates match the actual wafer to be inspected. As a result, it is possible to match the distortion of the inspected wafer itself and the distortion generated at the time of exposure, and the respective defect coordinate data can be accurately determined from the chip origin corrected by the error and accurately even if the magnification is high. You can move to the location.

[0023]

As described above, according to the present invention, when moving to a defect location according to defect coordinate data, first,
Correct the alignment coordinate error once. This allows
It is possible to provide a wafer coordinate recognition method of an automatic defect detection device capable of improving the coordinate accuracy and accurately obtaining a defect recognition image with a high magnification.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a wafer coordinate recognition method of an automatic defect detection device according to an embodiment of the present invention.

FIGS. 2A and 2B are wafer plan views more specifically showing a main part of a wafer coordinate recognition method of the automatic defect detection device in FIG.

FIG. 3 is an enlarged plan view of a chip area in a wafer to be inspected, showing more specifically a main part of a wafer coordinate recognition method of the automatic defect detection device in FIG. 1;

FIG. 4 is a review SE applied to an automatic defect detection device.
FIG. 9 is a plan view for explaining a wafer alignment method in M.

[Description of Signs] 1-5: Processing step D: Defect location CHIP: Chip WF: Wafer to be inspected

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Claims (2)

[Claims] The present invention relates to automatic defect detection in which a review SEM refers to defect coordinate data acquired from a wafer to be inspected and extracts an actual defect location on the wafer to be inspected as an image by a review SEM. When acquiring the alignment coordinates, the image data of an arbitrary chip origin is stored, and when moving to a defect location corresponding to the defect coordinate data based on the alignment coordinates, referring to the defect coordinate data. A method of recognizing a wafer coordinate of an automatic defect detection device, wherein the method temporarily shifts to the origin coordinate of a defective chip and corrects the error of the alignment coordinate by superimposing the image data on the chip origin. 2. The automatic defect detection device according to claim 1, wherein when correcting the error of the alignment coordinates, the magnification of the image data at the chip origin stored at the time of acquiring the alignment coordinates to be superimposed is matched. Wafer coordinate recognition method.