JPH0160844B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer control device, and particularly to a data transfer control device that can efficiently control large amounts of data from a processor.

In conventional data transfer control devices, when the data memory capacity exceeds the memory space of the processor, there have been methods to expand the memory space using address switching methods such as pacing, or to store data in external memory using a channel. The latter has drawbacks such as complicated page control, an increase in the number of channels, and troublesome control of each channel from the processor.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data transfer control device that can efficiently use a memory with a large address space, such as a data memory, by a processor with a narrow address space.

The present invention takes advantage of the fact that among the data signals handled by the data transfer control device, only the header portion must be directly controlled by the data transfer control device. The first memory is directly connected to the processor by a bus, and the first memory is connected by a bus independent of the processor. The address conversion circuit converts the processor bus and connects it to the second memory bus.

An embodiment of the present invention will be described with reference to the drawings. 1st
The figure is a system configuration diagram in this embodiment.
is an 8-bit microprocessor (MPU), 5 is a first memory (MEM) connected directly from the processor by a bus (MPU bus) 103, and 9 is connected by a bus DBM bus (104) independent of the processor. The second memory (DBM) 7 converts the processor bus and connects it to the second memory bus. The address conversion circuit (ADRC) 3 converts the facsimile image signal into sub-blocks of 510 bytes. Multiplexer (FCAP),
10 is from the facsimile multiplexer (FCAP)
a multiplex transfer device (FTC) for storing a 510-byte facsimile image signal in a data buffer memory (DBM) via a DBM bus 104; 4 a PT bus interface unit for controlling the interface with the CPRE1; (PTBI), 8 is a disk interface unit (DiU) that transmits and receives image signals according to the signal from PDCH 11, 1 is a central processing system unit (CPRE) that controls the entire system, 11 is an image signal magnetic disk channel, Reference numeral 12 indicates a magnetic disk device DKU that stores image signals.

Next, the operation of receiving a facsimile image signal will be explained. Facsimile multiplexer (FCAP) 3
The encoded facsimile image signal is
Transfer speed by sub-blocking in units of 510 bytes
The data is transferred to the data transfer control device 2 (PBE) according to the present invention via a 64 kb/s transmission line 105.
Next, under the control of an 8-bit microprocessor (MPU) 6, 10 multiplex transfer units (FTC)
The facsimile image signal in units of 510 bytes from the FCAP 3 is stored in the DBM 9 via the DBM bus 104. PBE2 stores 8 subblocks of facsimile image signals from the same line and sends them via PTBI4.
Report to CPRE11.

In order to identify the stored 4080-byte image signal, the information (16 bytes) from CPRE1 is converted by the address conversion circuit (ADRC) from MPU6 under the buffer management of MPU, and then sent to DBM9. Stored in the header section of the file.

In addition, under the control of the CPRE, the second memory DBM9 receives an image signal transfer request from the PDCH11.
Transfer speed from 4096 bytes via DIU8
Image signals are stored in a magnetic disk unit (DKU) 12 via an 800KB/S PIX bus 102 under PDCH control.

Next, the transmission operation will be explained. The image signals stored in the magnetic disk unit (DKU) 12 are
In response to a transfer request from FCAP3, data is stored in DBM9 in units of 4096 bytes via DIU8 under the control of PDCH11, and the header part (16 bytes) of the 4096 bytes is read out via the address conversion circuit from MPU6 and the information from CPRE1 is stored. After comparing and confirming that it is the image signal to be sent, it is sent to the FCAP 3 via the FTC 10.

A memory configuration for efficiently converting and matching data during data transfer between devices having different transfer units and transfer speeds is shown below.

As shown in Fig. 2, the transfer control device according to the present invention has 4096 bytes on two sides for transmission and reception (sides A and B for IC and OG), and has an independent memory configuration for FCAP. Taking advantage of the fact that only the header section must be directly controlled by the processor, the image signal buffer memory area is divided into an accessible area and a non-accessible area from the processor, and the address signal from the processor is simply converted to the accessible area. This was made possible. FIG. 3 shows an address conversion method. The processor address has a 16-bit word structure, and the DBM address has a 20-bit word word structure. X at DBM address
is an address in the header, and is a 4-bit address in the header part.
00000000, which represents a 16-byte address, is the PIX part that is not accessed from the processor, and FCPN is
FCAP number, IC/OG indicates IC/OG line, LN indicates line number, and A/B indicates A/B side. As shown in FIG. 3, conversion from a processor address to a DBM address is performed through an address conversion circuit.

By adopting such a memory configuration, it is possible to provide a unique data buffer memory without being limited by the address space of the processor. Although this embodiment is an example of a storage system for facsimile image signals, it can also be applied to a system that transfers signals composed of a data section that does not require involvement from the processor and a control section that should be controlled by the processor, such as an audio storage system. applicable.

In this embodiment, as shown in Figures 2 and 3, we are dealing with a memory area that can be accessed directly from the processor (16 bytes on each side), a non-accessible area (4080 bytes on each side), and fixed-length data. In the case of variable length data shown in Fig. 4, the maximum header length and maximum data length are taken into consideration, depending on the actual situation of the equipment used.
By using a suitable address conversion circuit, the buffer memory can be divided into a direct access area and a non-access area.

As explained above, according to the present invention, even if the address space of the processor is narrow, buffer memory with a wide address space can be directly accessed by having a simple address conversion function. This has the effect of providing buffer memory.

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram of an embodiment of the present invention, FIG. 2 is a memory configuration diagram of a data buffer memory (DBM) according to the present invention, and FIG. 3 is a diagram of address conversion when accessing the DBM from a processor according to the present invention. The explanatory diagram, FIG. 4, shows an application example of the present invention. DESCRIPTION OF SYMBOLS 1... Central processing system unit, 2... Data transfer control device, 3... Facsimile multiplexing device, 4... PT bus interface unit, 5... First memory, 6
...Microprocessor, 7.Address conversion circuit,
8...Disk interface unit, 9...Second memory, 10...Multiple transfer device, 11...Picture signal magnetic disk channel, 12...Magnetic disk device.

Claims (1)

[Claims] 1. In a data transfer control device for controlling data transfer between two devices having different transfer units and transfer speeds, a first device connected to a first device via a bus interface unit, 1 bus 103 and a processor 6 provided on the first bus 103
a data memory 9 which is divided into a directly accessible area and a non-accessible area of the processor 6 and stores data signals from the device using a second bus 104; 1 bus 103
and is connected to the second bus 104 for loading the data into the data memory 9, and controls the header section of the transfer data from the processor 6 to a directly accessible area of the data memory 9. A data transfer control device characterized in that it sets an address bit corresponding to a non-accessible area of a data memory 9 to "0" and is provided with an address conversion circuit 7 that simply converts an address signal from the processor 6.