JPH0159332U - - Google Patents
Info
- Publication number
- JPH0159332U JPH0159332U JP15399887U JP15399887U JPH0159332U JP H0159332 U JPH0159332 U JP H0159332U JP 15399887 U JP15399887 U JP 15399887U JP 15399887 U JP15399887 U JP 15399887U JP H0159332 U JPH0159332 U JP H0159332U
- Authority
- JP
- Japan
- Prior art keywords
- output
- input
- matrix switch
- switch circuit
- branch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011159 matrix material Substances 0.000 claims description 10
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Electronic Switches (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15399887U JPH0159332U (cs) | 1987-10-09 | 1987-10-09 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15399887U JPH0159332U (cs) | 1987-10-09 | 1987-10-09 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0159332U true JPH0159332U (cs) | 1989-04-13 |
Family
ID=31430334
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15399887U Pending JPH0159332U (cs) | 1987-10-09 | 1987-10-09 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0159332U (cs) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010210608A (ja) * | 2009-03-11 | 2010-09-24 | Star Technologies Inc | 組合せ型スイッチングマトリクスの構築方法およびその半導体装置の試験システム |
-
1987
- 1987-10-09 JP JP15399887U patent/JPH0159332U/ja active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010210608A (ja) * | 2009-03-11 | 2010-09-24 | Star Technologies Inc | 組合せ型スイッチングマトリクスの構築方法およびその半導体装置の試験システム |
US8310264B2 (en) | 2009-03-11 | 2012-11-13 | Star Technologies Inc. | Method for configuring combinational switching matrix and testing system for semiconductor devices using the same |