JPH0158473B2 - - Google Patents

Info

Publication number
JPH0158473B2
JPH0158473B2 JP56145090A JP14509081A JPH0158473B2 JP H0158473 B2 JPH0158473 B2 JP H0158473B2 JP 56145090 A JP56145090 A JP 56145090A JP 14509081 A JP14509081 A JP 14509081A JP H0158473 B2 JPH0158473 B2 JP H0158473B2
Authority
JP
Japan
Prior art keywords
lsi
integrated circuit
circuit
timer
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56145090A
Other languages
Japanese (ja)
Other versions
JPS5782789A (en
Inventor
Junzo Murata
Takashi Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Maxell Ltd
Original Assignee
Hitachi Maxell Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Maxell Ltd filed Critical Hitachi Maxell Ltd
Priority to JP56145090A priority Critical patent/JPS5782789A/en
Publication of JPS5782789A publication Critical patent/JPS5782789A/en
Publication of JPH0158473B2 publication Critical patent/JPH0158473B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Clocks (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は計時カウンタ回路やメモリ回路など
が集積化された時計用大規模集積回路を有効的に
活用した電子式タイマ装置に関するもので、簡単
な構成でストツプウオツチ機能をもたせた電子式
タイマ装置を提供することを目的する。[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to an electronic timer device that effectively utilizes a large-scale integrated circuit for watches in which a time counter circuit, a memory circuit, etc. are integrated. An object of the present invention is to provide an electronic timer device having a stopwatch function with a simple configuration.

〔従来の技術および問題点〕 従来、この種のストツプウオツチ機能を備えた
電子式タイマ装置は、ストツプウオツチのための
計時カウンタ回路を有していないため、ストツプ
ウオツチを作動させると、タイマ設定時刻や現在
時刻がずれるという欠点がある。[Prior art and problems] Conventionally, electronic timer devices with this type of stopwatch function do not have a time counter circuit for the stopwatch, so when the stopwatch is activated, the timer setting time and current time are It has the disadvantage that it may shift.

このためにストツプウオツチ機能を複合させよ
うとすると、全く別個のストツプウオツチ専用の
回路を設ける必要がありコスト高になる。 Therefore, if a stopwatch function is to be combined, it is necessary to provide a completely separate circuit dedicated to the stopwatch, which increases the cost.

〔解決するための手段〕[Means to solve]

この発明は上記欠点を解消するために、設定時
刻にタイマ作動信号を発生する時刻設定用の第１
の時計用大規模集積回路LSI1と、所定時間計数
後にタイマ停止信号を発生する時間計数用の第２
の時計用大規模集積回路LSI2と、通常は第２の
集積回路LSI2をリセツト状態に拘束し、上記第
１の集積回路LSI1からのタイマ作動信号をうけ
ることにより上記第２の集積回路LSI2のリセツ
ト状態を解除させ、計時を開始させるリセツト解
除回路CLCとから成るタイマ機能を有す電子式
タイマ装置であつて、上記リセツト解除回路
CLCと別個に独立して、上記第２のLSI2のリセ
ツト状態を解除して計時動作のできる入力回路
INCを上記第２の集積回路LSI2に接続したもので
ある。 In order to solve the above-mentioned drawbacks, this invention provides a first time setting device that generates a timer activation signal at a set time.
large-scale integrated circuit LSI 1 for clocks, and a second circuit for time counting that generates a timer stop signal after counting a predetermined time.
The large-scale integrated circuit LSI 2 for watches and usually the second integrated circuit LSI 2 are held in a reset state, and the second integrated circuit is activated by receiving a timer operation signal from the first integrated circuit LSI 1 . An electronic timer device having a timer function consisting of a reset release circuit CLC that releases the reset state of LSI 2 and starts timing, the reset release circuit
An input circuit that can release the reset state of the second LSI 2 and perform timekeeping operation independently of the CLC.
INC is connected to the second integrated circuit LSI 2 .

〔実施例〕〔Example〕

以下、この発明の実施例を図面にしたがつて説
明する。 Embodiments of the present invention will be described below with reference to the drawings.

第１図において、LSI1，LSI2は図示されない
計時カウンタ回路やメモリ回路などを集積化した
時計用大規模集積回路で、第１の集積回路LSI1
は設定時刻にタイマ作動信号を生起する時刻設定
用であり、第２の集積回路LSI2は所定時間計時
後にタイマ停止信号を生起する時計計時用であ
る。TDCは上記集積回路LSI1，LSI2各表示出力
端子X1，X2に表示切換回路GCを介して共通接続
された時・分・秒単位の表示回路、FFCはタイ
マ出力発生用のフリツプフロツプ回路で、このフ
リツプフロツプ回路FFCのセツト入力端子SEお
よびリセツト入力端子REには、上記集積回路
LSI1，LSI2の各タイマ・アウト端子TO1，TO2
がそれぞれ電気的に接続されている。CLCは第
２の集積回路LSI2を常時はリセツト状態に拘束
し、第１の集積回路LSI1からタイマ作動信号を
受けて上記第２の集積回路LSI2のリセツト状態
を解除させ、第２の集積回路LSI2の計時を開始
させるリセツト解除回路で、たとえばスイツチン
グトランジスタTR、抵抗R1，R2、ダイオ−ドD1
〜D3などからなり、ダイオ−ドD1〜D3の各カソ
−ド極側が上記集積回路LSI2の時刻セツト入力
端子Ｓ，Ｆ，SEC（ＳはSLOW送り、ＦはFast送
り、SECは秒リセツト）にそれぞれ電気的に接続
され、またフリツプフロツプ回路FFCの出力端
子ＱがスイツチングトランジスタTRのベ−ス極
に接続されている。 In FIG. 1, LSI 1 and LSI 2 are large-scale integrated circuits for watches that integrate time counter circuits, memory circuits, etc. (not shown), and the first integrated circuit LSI 1
is for time setting to generate a timer activation signal at a set time, and the second integrated circuit LSI 2 is for clock timing to generate a timer stop signal after counting a predetermined time. TDC is a display circuit for hours, minutes, and seconds that is commonly connected to the display output terminals X 1 and X 2 of the above integrated circuits LSI 1 and LSI 2 through the display switching circuit GC, and FFC is a flip-flop circuit for generating timer output. The above integrated circuit is connected to the set input terminal SE and reset input terminal RE of this flip-flop circuit FFC.
Timer out terminals TO 1 and TO 2 of LSI 1 and LSI 2
are electrically connected to each other. The CLC normally restrains the second integrated circuit LSI 2 in the reset state, receives a timer activation signal from the first integrated circuit LSI 1 , releases the reset state of the second integrated circuit LSI 2 , and resets the second integrated circuit LSI 2. This is a reset release circuit that starts the time measurement of the integrated circuit LSI 2 , and includes, for example, a switching transistor TR, resistors R1 , R2 , and a diode D1.
~ D3, etc., and the cathode side of each diode D1 ~ D3 is connected to the time set input terminals S, F, SEC of the integrated circuit LSI 2 (S is SLOW feed, F is Fast feed, SEC is The output terminal Q of the flip-flop circuit FFC is connected to the base pole of the switching transistor TR.

上記集積回路LSI1と集積回路LSI2の時刻セツ
ト入力端子Ｓ，Ｆ，SECは、それぞれに入力され
る信号電圧によつて、表示回路TDCの表示状態
を切換えるようにそれぞれの集積回路LSI1、集
積回路LSI2の中でプログラム化されており、Ｓ，
Ｆ，SECすべてに“１”が入力されるとオ−ルリ
セツトされて、待機状態となりＳ，Ｆ，SECに
“０”が入力されると計時開始すると同時に表示
回路TDCには時・分単位で表示し、SECが“１”
でＳとＦが“０”の場合には分・秒単位で表示す
る。 The time set input terminals S, F, and SEC of the integrated circuit LSI 1 and the integrated circuit LSI 2 are configured to switch the display state of the display circuit TDC according to the signal voltage input to each of the integrated circuits LSI 1 and LSI 2 , respectively. It is programmed in the integrated circuit LSI 2 , and S,
When "1" is input to all of F and SEC, all reset is performed and the device goes into standby state. When "0" is input to S, F and SEC, timekeeping starts and at the same time the display circuit TDC shows the hour and minute units. displayed, SEC is “1”
If S and F are "0", it will be displayed in minutes and seconds.

上記各集積回路LSI1，LSI2の各タイマ・オ
フ・イン端子TI1，TI2にはフリツプフロツプ回
路FFCの出力端子Ｑおよび反転出力端子がそ
れぞれ電気的に接続されている。RCは、ラジオ
などの電子装置（図示せず）の電源を開閉させる
リレ−回路である。 The output terminal Q and the inverted output terminal of the flip-flop circuit FFC are electrically connected to the timer off-in terminals TI 1 and TI 2 of the integrated circuits LSI 1 and LSI 2 , respectively. RC is a relay circuit that opens and closes power to an electronic device (not shown) such as a radio.

INCは上記第１の集積回路LSI1と第２の集積回
路LSI2との間に介挿された入力回路で、第１の
集積回路LSI1からのタイマ作動信号がない場合
に、同様の信号電圧Vcを第２の集積回路LSI2側
に印加加させる開閉スイツチS1と分・秒単位と時
単位の表示切換用常閉スイツチS2とストツプウオ
ツチ動作切換スイツチS3とを有している。 INC is an input circuit inserted between the first integrated circuit LSI 1 and the second integrated circuit LSI 2 , and when there is no timer activation signal from the first integrated circuit LSI 1 , a similar signal is input. It has an open/close switch S1 for applying voltage Vc to the second integrated circuit LSI 2 side, a normally closed switch S2 for switching the display between minutes/seconds and hours, and a stopwatch operation switching switch S3 . .

以上の構成を有する電子式タイマ装置におい
て、まず設定時刻になると第１の集積回路LSI1
からタイマ作動信号が上記フリツプフロツク回路
FFCに印加されると上述のリセツト解除回路
CLCのスイツチングトランジスタTRが導通状態
となり、第２の集積回路LSI2の時刻セツト入力
端子に全て“０”が入力され、第２の集積回路
LSI2の計時が開始し、タイマ機能がスタ−トす
る。 In the electronic timer device having the above configuration, first, when the set time comes, the first integrated circuit LSI 1
The timer activation signal is output from the above flip-flop circuit.
When applied to FFC, the reset release circuit described above
The switching transistor TR of the CLC becomes conductive, and all "0"s are input to the time set input terminals of the second integrated circuit LSI 2 .
LSI 2 starts measuring time and the timer function starts.

第２の集積回路LSI2の計時が所定時間行われ
ると、第２の集積回路LSI2から上記フリツプフ
ロツク回路FFCにタイマ作動停止信号が入力さ
れ、トランジスタTRがOFFとなり上記入力端子
に全て“１”が入力され、待機状態に戻り、タイ
マ機能は終了する。 When the second integrated circuit LSI 2 measures time for a predetermined period of time, a timer operation stop signal is input from the second integrated circuit LSI 2 to the flip-flop circuit FFC, the transistor TR is turned off, and all the input terminals are set to "1". is input, the device returns to the standby state, and the timer function ends.

また以上のようなタイマ機能としての利用以外
に、入力回路INCのスイツチS3を図示の実線位置
のままでスイツチS1を閉成すると、第２の集積回
路LSI2の時刻セツト入力端子Ｓ，Ｆ，SECに
“１”、“１”、“１”が印加され、上記集積回路
LSI2はストツプウオツチ動作の待機状態にセツ
トされる。スイツチS3を点線位置に切換えると上
記時刻セツト入力端子Ｓ，Ｆ，SECのうちSECの
みに電圧信号が印加され、３つの端子には“０”、
“０”、“１”となり、計時を開始すると同時に表
示回路TDCに分・秒単位で表示される。この時
常閉スイツチS2を開放すれば上記時刻セツト入力
端子Ｓ，Ｆ，SECが“０”、“０”、“０”となるた
め、表示回路TDCの分・秒単位の表示が時・分
単位に切換つて表示される。スイツチS3を１点鎖
線位置に切換えると、時刻セツト入力端子Ｓ，
Ｆ，SECが“１”、“０”、“１”となり、計時デ−
タを保留したまま、上記計時動作が停止され、そ
の計時がホ−ルドされる。ホ−ルドと同時に、タ
イムカウントが休止し、計つた時間を表示回路
TDCで表示する。ここで再度ストツプウオツチ
動作を行いたい時は、スイツチS3を実線位置まで
戻すことにより入力端子Ｓ，Ｆ，SECが“１”、
“１”、“１”となり、オ−ルクリアされて待機状
態に戻すことができる。 In addition to the above-mentioned use as a timer function, if the switch S3 of the input circuit INC is left in the solid line position shown in the figure and the switch S1 is closed, the time set input terminal S of the second integrated circuit LSI 2 , “1”, “1”, “1” is applied to F, SEC, and the above integrated circuit
LSI 2 is set to a standby state for stopwatch operation. When the switch S 3 is switched to the dotted line position, a voltage signal is applied to only SEC among the time set input terminals S, F, SEC, and the three terminals are set to "0",
They become "0" and "1" and are displayed in minutes and seconds on the display circuit TDC at the same time as timing starts. At this time, if the normally closed switch S2 is opened, the time set input terminals S, F, and SEC become "0", "0", and "0", so that the display circuit TDC displays the minutes and seconds. The unit is switched and displayed. When the switch S3 is moved to the position indicated by the dashed dotted line, the time set input terminals S,
F, SEC become “1”, “0”, “1”, and the clock data
The above-mentioned time measurement operation is stopped and the time measurement is held while the data is kept on hold. At the same time as the hold, the time count stops and the circuit that displays the measured time
Display in TDC. If you want to perform the stop watch operation again, return the switch S3 to the solid line position so that the input terminals S, F, SEC become "1".
The flag becomes "1", "1", all cleared and the state can be returned to the standby state.

〔効果〕〔effect〕

以上の構成を有すこの発明によれば、設定時刻
にタイマ作動信号を発生する時刻設定用の第１の
時計用大規模集積回路LSI1と、所定時間計数後
にタイマ停止信号を発生する時間計数用の第２の
時計用大規模集積回路LSI2と、通常は第２の集
積回路LSI2のリセツト状態に拘束し、上記第１
の集積回路LSI1からのタイマ作動信号をうける
ことにより上記第２の集積回路LSI2のリセツト
状態を解除させ、計時を開始させるリセツト解除
回路CLCとから成るタイマ機能を有す電子式タ
イマ装置であつて、上記リセツト解除回路CLC
と別個に独立して、上記第２の集積回路LSI2を
リセツト状態を解除して、計時動作のできる入力
回路INCを上記第２の集積回路LSI2を接続させた
ことによりタイマ機能に関係なくストツプウオツ
チ動作を駆動させることができるため、ストツプ
ウオツチ動作によつてタイマ設定時刻や現在時刻
がずれるおそれがない電子式タイマ装置を提供す
ることができる。 According to the present invention having the above configuration, the first clock large-scale integrated circuit LSI 1 for time setting generates a timer activation signal at a set time, and the time counter generates a timer stop signal after counting a predetermined time. Normally, the second large-scale integrated circuit LSI 2 for watches is held in a reset state, and the first large-scale integrated circuit LSI 2 is
An electronic timer device having a timer function and comprising a reset release circuit CLC that releases the reset state of the second integrated circuit LSI 2 and starts time measurement upon receiving a timer activation signal from the integrated circuit LSI 1 . If the above reset release circuit CLC
By separately and independently releasing the reset state of the second integrated circuit LSI 2 and connecting the input circuit INC capable of timekeeping operation to the second integrated circuit LSI 2 , regardless of the timer function. Since the stopwatch operation can be driven, it is possible to provide an electronic timer device in which there is no possibility that the timer setting time or the current time will deviate due to the stopwatch operation.

また、タイマ機能に必要な時間計数用の第２の
集積回路LSI2を入力回路INCを備えることによ
り、ストツプウオツチ機能に利用できるのでスト
ツプウオツチ用の専用回路を必要とせず、コスト
低減が図れるものである。 In addition, by providing the input circuit INC with the second integrated circuit LSI 2 for time counting required for the timer function, it can be used for the stopwatch function, so a dedicated circuit for the stopwatch is not required, and costs can be reduced. .

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明に係る電子式タイマ装置の一
例を示す電気回路図である。 LSI1……第１の集積回路、LSI2……第２の集
積回路、INC……入力回路。 FIG. 1 is an electrical circuit diagram showing an example of an electronic timer device according to the present invention. LSI 1 ...First integrated circuit, LSI 2 ...Second integrated circuit, INC...Input circuit.

Claims (1)

【特許請求の範囲】[Claims] １ 設定時刻にタイマ作動信号を発生する時刻設
定用の第１の時計用大規模集積回路LSI1と、所
定時間計数後にタイマ停止信号を発生する時間計
数用の第２の時計用大規模集積回路LSI2と、通
常は第２の集積回路LSI2をリセツト状態に拘束
し、上記第１の集積回路LSI1からのタイマ作動
信号をうけることにより上記第２の集積回路
LSI2のリセツト状態を解除させ、計時を開始さ
せるリセツト解除回路CLCとから成るタイマ機
能を有す電子式タイマ装置であつて、上記リセツ
ト解除回路CLCと別個に独立して、上記第２の
集積回路LSI2のリセツト状態を解除して計時動
作のできる入力回路INCを上記第２の集積回路
LSI2に接続したことを特徴とする電子式タイマ
装置。1. A first large-scale integrated circuit for a clock LSI 1 for time setting that generates a timer activation signal at a set time, and a second large-scale integrated circuit for a clock for time counting that generates a timer stop signal after counting a predetermined time. LSI 2 , usually the second integrated circuit LSI 2 , is held in a reset state, and the second integrated circuit is reset by receiving a timer activation signal from the first integrated circuit LSI 1 .
An electronic timer device having a timer function consisting of a reset release circuit CLC that releases the reset state of LSI 2 and starts timing, the second integrated circuit separately and independently of the reset release circuit CLC. The input circuit INC, which can release the reset state of circuit LSI 2 and perform timekeeping operation, is connected to the second integrated circuit mentioned above.
An electronic timer device characterized by being connected to LSI 2 .
JP56145090A 1981-09-14 1981-09-14 Timer device in electronic system Granted JPS5782789A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56145090A JPS5782789A (en) 1981-09-14 1981-09-14 Timer device in electronic system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56145090A JPS5782789A (en) 1981-09-14 1981-09-14 Timer device in electronic system

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP12328077A Division JPS5456477A (en) 1977-10-13 1977-10-13 Electronic timer

Publications (2)

Publication Number Publication Date
JPS5782789A JPS5782789A (en) 1982-05-24
JPH0158473B2 true JPH0158473B2 (en) 1989-12-12

Family

ID=15377143

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56145090A Granted JPS5782789A (en) 1981-09-14 1981-09-14 Timer device in electronic system

Country Status (1)

Country Link
JP (1) JPS5782789A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4990174A (en) * 1972-12-27 1974-08-28

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4990174A (en) * 1972-12-27 1974-08-28

Also Published As

Publication number Publication date
JPS5782789A (en) 1982-05-24

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